Pub Date : 2024-08-28DOI: 10.1109/TEMC.2024.3440919
Takuya Wadatsumi;Kazuki Monta;Yusuke Hayashi;Takuji Miki;Alkis A. Hatzopoulos;Adrijan Barić;Makoto Nagata
The backside of integrated circuits (ICs) in flip-chip assembly is susceptible to intentional electromagnetic interference due to its open surface. In this article, we propose a model in which conducted current noise from a localized area of the Si substrate on the chip-backside causes errors in complementary metal-oxide-semiconductor (CMOS) digital circuits. This model explains for the first time the mechanism of bit-flip errors in bistable circuits caused by high-voltage pulse (HVP) injection on the backside of the IC. The injected current from the backside of the IC not only flows into the power distribution network, but also charges the gate capacitance of the next stage via p–n junction diodes of body/drain or body/source in N-channel mosfet