Pub Date : 2024-03-08DOI: 10.1109/LES.2024.3398594
M. A. Sandoval-Chileño;N. Lozada-Castillo;R. Cortez;J. Vazquez-Arenas;A. Luviano-Juárez
Electric vehicles need continuous monitoring of the energy supply all the time to provide the user with accurate information about the available energy. However, an increase in the power consumed by the monitoring system may cause a significant decrease in the vehicle’s autonomy. This letter presents a monitoring and estimation system for an electric car with a hybrid energy supply based on supercapacitors and batteries based on an embedded system capable of monitoring the general current, the current from the battery system, the voltage in the battery system, the voltage in the supercapacitor system, estimating the value of the state of charge from batteries, and showing the measurements to the user with an OLED display. The proposed system performs similarly in the estimation but decreases the energy consumption by 99.9% concerning the laboratory systems.
{"title":"Low Consumption Monitoring and Estimation of the State of Charge System for a Hybrid Electric Vehicle","authors":"M. A. Sandoval-Chileño;N. Lozada-Castillo;R. Cortez;J. Vazquez-Arenas;A. Luviano-Juárez","doi":"10.1109/LES.2024.3398594","DOIUrl":"https://doi.org/10.1109/LES.2024.3398594","url":null,"abstract":"Electric vehicles need continuous monitoring of the energy supply all the time to provide the user with accurate information about the available energy. However, an increase in the power consumed by the monitoring system may cause a significant decrease in the vehicle’s autonomy. This letter presents a monitoring and estimation system for an electric car with a hybrid energy supply based on supercapacitors and batteries based on an embedded system capable of monitoring the general current, the current from the battery system, the voltage in the battery system, the voltage in the supercapacitor system, estimating the value of the state of charge from batteries, and showing the measurements to the user with an OLED display. The proposed system performs similarly in the estimation but decreases the energy consumption by 99.9% concerning the laboratory systems.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 3","pages":"311-314"},"PeriodicalIF":1.7,"publicationDate":"2024-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142090707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-07DOI: 10.1109/LES.2024.3373200
Jong-Bin Lee;Sang-Jae Kim;Wook-Hee Kim;Hyun-Wook Jin
ARINC-653, a standard of avionics software platform, defines the sampling communication port that provides only the latest message while discarding old messages. This sampling port is particularly efficient at transmitting sensing data that reflects the actual state of target system without message queueing delay. In this letter, we implement the ARINC-653 sampling port by exploiting remote direct memory access (RDMA) over Ethernet that can directly move data to/from remote memory without CPU intervention on the remote node. We propose two different designs to utilize two-sided RDMA and one-sided RDMA operations, respectively. Performance measurement results show that the sampling port over one-sided RDMA provides lower-communication latency, stronger temporal partitioning, and better-message timeliness than two-sided RDMA and Berkeley sockets-based implementations.
{"title":"RDMA-Based Sampling Port of ARINC-653","authors":"Jong-Bin Lee;Sang-Jae Kim;Wook-Hee Kim;Hyun-Wook Jin","doi":"10.1109/LES.2024.3373200","DOIUrl":"10.1109/LES.2024.3373200","url":null,"abstract":"ARINC-653, a standard of avionics software platform, defines the sampling communication port that provides only the latest message while discarding old messages. This sampling port is particularly efficient at transmitting sensing data that reflects the actual state of target system without message queueing delay. In this letter, we implement the ARINC-653 sampling port by exploiting remote direct memory access (RDMA) over Ethernet that can directly move data to/from remote memory without CPU intervention on the remote node. We propose two different designs to utilize two-sided RDMA and one-sided RDMA operations, respectively. Performance measurement results show that the sampling port over one-sided RDMA provides lower-communication latency, stronger temporal partitioning, and better-message timeliness than two-sided RDMA and Berkeley sockets-based implementations.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"437-440"},"PeriodicalIF":1.7,"publicationDate":"2024-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10459217","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140075555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-02DOI: 10.1109/LES.2024.3396058
Amir Hossein Ansari;Mohsen Ansari;Alireza Ejlali
To achieve high reliability, fault-tolerance techniques are exploited, but they may increase power consumption and temperature beyond safe limits. Therefore, power-aware fault-tolerance techniques should be used to manage power and temperature issues. We tolerate both permanent and transient faults through hybrid fault-tolerance techniques. In this letter, at first, we investigate how much power and temperature are increased when a hybrid fault-tolerance technique is applied to multicore embedded systems. Then, we propose a peak-power-aware hybrid fault-tolerant technique to meet the temperature constraint. Transient-temperature-based safe power (T-TSP) is a new power budgeting technique whose calculation is based on the current temperature of the processing core. Assigning dynamic budgets through T-TSP to processing cores allows us to effectively reach the full performance of processing cores. Experiments show that our proposed method reduces peak power and energy consumption on average by 13.5% (up to 50.7%) and 41.8% (up to 67.4%), respectively and improves the schedulability on average by 6.8% (up to 22.4%) compared to state-of-the-art methods while meeting the system reliability target.
{"title":"TAFT: Thermal-Aware Hybrid Fault-Tolerant Technique for Multicore Embedded Systems","authors":"Amir Hossein Ansari;Mohsen Ansari;Alireza Ejlali","doi":"10.1109/LES.2024.3396058","DOIUrl":"10.1109/LES.2024.3396058","url":null,"abstract":"To achieve high reliability, fault-tolerance techniques are exploited, but they may increase power consumption and temperature beyond safe limits. Therefore, power-aware fault-tolerance techniques should be used to manage power and temperature issues. We tolerate both permanent and transient faults through hybrid fault-tolerance techniques. In this letter, at first, we investigate how much power and temperature are increased when a hybrid fault-tolerance technique is applied to multicore embedded systems. Then, we propose a peak-power-aware hybrid fault-tolerant technique to meet the temperature constraint. Transient-temperature-based safe power (T-TSP) is a new power budgeting technique whose calculation is based on the current temperature of the processing core. Assigning dynamic budgets through T-TSP to processing cores allows us to effectively reach the full performance of processing cores. Experiments show that our proposed method reduces peak power and energy consumption on average by 13.5% (up to 50.7%) and 41.8% (up to 67.4%), respectively and improves the schedulability on average by 6.8% (up to 22.4%) compared to state-of-the-art methods while meeting the system reliability target.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"477-480"},"PeriodicalIF":1.7,"publicationDate":"2024-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140829504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new approximate full adder (FA) and a new approximate subtractor are presented, both of them have 8 transistors, and their areas are 0.1944 and $0.1689~mu $ m2, respectively. The FA experiences three errors, while the subtractor shows two errors. In both circuits, to improve the speed, output swing, and drivability, the gate diffusion input (GDI) and dynamic threshold (DT) techniques are implemented by carbon nanotube field effect transistor (CNTFET) technology. The FA and subtractor in order are embedded in an 8-bit ripple carry adder (RCA) and an 8-bit subtractor, then they make a new approximate multiplier-free discrete cosine transform (DCT). The 8-point approximate DCT manipulation requires only addition and no multiplication. So, computational complexity is brought down. The DCT shows power delay product (PDP), peak signal-to-noise ratio (PSNR), and a figure of merit (FoM) of 63.61 fJ, 34.96 dB, and 2.39, respectively. The features of the presented approximate DCT confirm its application for image compression and noise removal in medical images.
{"title":"A Multiplier-Free Discrete Cosine Transform Architecture Using Approximate Full Adder and Subtractor","authors":"Elham Esmaeili;Nabiollah Shiri;Mahmood Rafiee;Ayoub Sadeghi","doi":"10.1109/LES.2024.3395900","DOIUrl":"10.1109/LES.2024.3395900","url":null,"abstract":"A new approximate full adder (FA) and a new approximate subtractor are presented, both of them have 8 transistors, and their areas are 0.1944 and \u0000<inline-formula> <tex-math>$0.1689~mu $ </tex-math></inline-formula>\u0000m2, respectively. The FA experiences three errors, while the subtractor shows two errors. In both circuits, to improve the speed, output swing, and drivability, the gate diffusion input (GDI) and dynamic threshold (DT) techniques are implemented by carbon nanotube field effect transistor (CNTFET) technology. The FA and subtractor in order are embedded in an 8-bit ripple carry adder (RCA) and an 8-bit subtractor, then they make a new approximate multiplier-free discrete cosine transform (DCT). The 8-point approximate DCT manipulation requires only addition and no multiplication. So, computational complexity is brought down. The DCT shows power delay product (PDP), peak signal-to-noise ratio (PSNR), and a figure of merit (FoM) of 63.61 fJ, 34.96 dB, and 2.39, respectively. The features of the presented approximate DCT confirm its application for image compression and noise removal in medical images.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"441-444"},"PeriodicalIF":1.7,"publicationDate":"2024-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140829764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-28DOI: 10.1109/LES.2024.3371106
Dipesh;Urbi Chatterjee
Multiprocessor systems-on-chip (MPSoC) have emerged as highly versatile and efficient platforms suitable for a wide range of applications like multimedia applications and telecommunication architectures. One of the key components in MPSoC is the network-on-chip (NoC), which facilitates the interconnection of various processing elements (PEs), enabling efficient data communication. Several timing attacks, such as Earthquake attack, P+P Firecracker, and P+P Arrow, have been proposed on NoC that exploit the variations in execution times of operations to infer cryptographic keys. In this letter, we propose to leverage the timing attack on NoC to reverse engineer the mapping of each PE onto the MPSoC architecture. To the best of our knowledge, it is the first work that relies on creating the contention between the requests that are sent to different PEs and reveal the layout by just analyzing the reply latency. In the experimental setup, we are able to map PEs for MPSoC consists of Mesh, Torus, Point-to-Point, Ring, and Flattened Butterfly NoC topology with 100% accuracy that can be extremely useful for the attackers in the reconnaissance phase. Further, as the existing mitigation techniques to counter timing attacks are based on the assumption that the contention is created between the packets of secure-insecure domains, they will not be able to mitigate the proposed reverse engineering attack.
{"title":"Door Knock: Reverse Engineering the MPSoC Layout Through Timing Attack on NoC","authors":"Dipesh;Urbi Chatterjee","doi":"10.1109/LES.2024.3371106","DOIUrl":"https://doi.org/10.1109/LES.2024.3371106","url":null,"abstract":"Multiprocessor systems-on-chip (MPSoC) have emerged as highly versatile and efficient platforms suitable for a wide range of applications like multimedia applications and telecommunication architectures. One of the key components in MPSoC is the network-on-chip (NoC), which facilitates the interconnection of various processing elements (PEs), enabling efficient data communication. Several timing attacks, such as Earthquake attack, P+P Firecracker, and P+P Arrow, have been proposed on NoC that exploit the variations in execution times of operations to infer cryptographic keys. In this letter, we propose to leverage the timing attack on NoC to reverse engineer the mapping of each PE onto the MPSoC architecture. To the best of our knowledge, it is the first work that relies on creating the contention between the requests that are sent to different PEs and reveal the layout by just analyzing the reply latency. In the experimental setup, we are able to map PEs for MPSoC consists of Mesh, Torus, Point-to-Point, Ring, and Flattened Butterfly NoC topology with 100% accuracy that can be extremely useful for the attackers in the reconnaissance phase. Further, as the existing mitigation techniques to counter timing attacks are based on the assumption that the contention is created between the packets of secure-insecure domains, they will not be able to mitigate the proposed reverse engineering attack.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"449-452"},"PeriodicalIF":1.7,"publicationDate":"2024-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142797914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-28DOI: 10.1109/LES.2024.3371371
Raúl Eduardo Lopresti;Jorge Castiñeira Moreira;Luciana De Micco
Emerging communication standards prioritize both the assurance of secure and reliable communications as well as the reduction of transmission delay and latency. Nevertheless, the task of achieving these objectives presents a complex and demanding challenge. Ensuring secure transmissions while simultaneously minimizing error rates requires the implementation of multistage information processing techniques that integrate coding and encryption methods, which may unfortunately lead to an undesired increase in transmission delay and latency. This letter presents an innovative crypto-coding framework capable of concurrently achieving essential encryption and coding within a single, streamlined process. By leveraging this approach, we aim to address the tradeoff between security, efficiency, and transmission delay, thus contributing to the advancement of secure and efficient communication standards. In this letter, we present a comprehensive evaluation of the proposed scheme, assessing its impact on final system error probability, encryption efficacy, and the complexity of hardware implementation. Our findings shed light on the potential benefits of this approach for future communication standards.
{"title":"Crypto-Coding Scheme via Dynamic Interleaver for New Communication Standards","authors":"Raúl Eduardo Lopresti;Jorge Castiñeira Moreira;Luciana De Micco","doi":"10.1109/LES.2024.3371371","DOIUrl":"10.1109/LES.2024.3371371","url":null,"abstract":"Emerging communication standards prioritize both the assurance of secure and reliable communications as well as the reduction of transmission delay and latency. Nevertheless, the task of achieving these objectives presents a complex and demanding challenge. Ensuring secure transmissions while simultaneously minimizing error rates requires the implementation of multistage information processing techniques that integrate coding and encryption methods, which may unfortunately lead to an undesired increase in transmission delay and latency. This letter presents an innovative crypto-coding framework capable of concurrently achieving essential encryption and coding within a single, streamlined process. By leveraging this approach, we aim to address the tradeoff between security, efficiency, and transmission delay, thus contributing to the advancement of secure and efficient communication standards. In this letter, we present a comprehensive evaluation of the proposed scheme, assessing its impact on final system error probability, encryption efficacy, and the complexity of hardware implementation. Our findings shed light on the potential benefits of this approach for future communication standards.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 3","pages":"287-290"},"PeriodicalIF":1.7,"publicationDate":"2024-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140006552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The automated detection of tuberculosis (TB) and pneumonia (PN) from chest X-ray (CXR) images using artificial intelligence (AI) is challenging in clinical studies for rapid diagnosis and initiation of treatment. This letter proposes the field-programmable gate array (FPGA)-based hardware implementation of a novel lightweight deep convolutional neural network (DCNN) model to detect PN and TB ailments using CXR images. Initially, the proposed DCNN (consisting of ten layers) is trained using the Google Cloud central processing unit (CPU) to obtain the model weight and bias parameters. Then, the register transfer logic (RTL) for the trained DCNN model is generated by the VIVADO high-level synthesis (HLS) framework using HLS for machine learning (HLS4ML) with fixed-point representation (8 bit for integer and 12 bit for the fractional part). The hardware implementation of the suggested DCNN model is performed using the PYNQ-Z2 FPGA framework to detect TB and PN diseases automatically. The experimental results demonstrate that the proposed DCNN model has obtained accuracy values of 96.39% and 95.63% on the Google-Cloud CPU and PYNQ-Z2 FPGA frameworks using 422 CXR images in the inference phases. The inference time of the proposed DCNN model on the PYNQ-Z2 FPGA framework is reduced by 85.19% compared to the CPU-based implementation. The suggested DCNN model has only 1831 parameters, less than the transfer learning (TFL) and existing CNN-based models to detect TB and PN using CXR images.
{"title":"FPGA Implementation of the Proposed DCNN Model for Detection of Tuberculosis and Pneumonia Using CXR Images","authors":"Prabhav Guddati;Shaswati Dash;Rajesh Kumar Tripathy","doi":"10.1109/LES.2024.3370833","DOIUrl":"10.1109/LES.2024.3370833","url":null,"abstract":"The automated detection of tuberculosis (TB) and pneumonia (PN) from chest X-ray (CXR) images using artificial intelligence (AI) is challenging in clinical studies for rapid diagnosis and initiation of treatment. This letter proposes the field-programmable gate array (FPGA)-based hardware implementation of a novel lightweight deep convolutional neural network (DCNN) model to detect PN and TB ailments using CXR images. Initially, the proposed DCNN (consisting of ten layers) is trained using the Google Cloud central processing unit (CPU) to obtain the model weight and bias parameters. Then, the register transfer logic (RTL) for the trained DCNN model is generated by the VIVADO high-level synthesis (HLS) framework using HLS for machine learning (HLS4ML) with fixed-point representation (8 bit for integer and 12 bit for the fractional part). The hardware implementation of the suggested DCNN model is performed using the PYNQ-Z2 FPGA framework to detect TB and PN diseases automatically. The experimental results demonstrate that the proposed DCNN model has obtained accuracy values of 96.39% and 95.63% on the Google-Cloud CPU and PYNQ-Z2 FPGA frameworks using 422 CXR images in the inference phases. The inference time of the proposed DCNN model on the PYNQ-Z2 FPGA framework is reduced by 85.19% compared to the CPU-based implementation. The suggested DCNN model has only 1831 parameters, less than the transfer learning (TFL) and existing CNN-based models to detect TB and PN using CXR images.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"445-448"},"PeriodicalIF":1.7,"publicationDate":"2024-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140003875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-27DOI: 10.1109/LES.2024.3370634
Hassan Shabani Mputu;Ahmed-Abdel Mawgood;Atsushi Shimada;Mohammed S. Sayed
The current quality assessment for fruits and vegetables relies on subjective human judgment and manual inspection, resulting in inconsistencies and inefficiencies. Due to that, there is a need for a real-time system that can accurately and efficiently assess the quality of fruits and vegetables by analyzing various parameters, such as color, texture, size, and blemishes, to ensure consistency and reduce waste in the food supply chain. This study presents the development of a real-time tomato classification system using a hybrid model that combines convolutional neural network (CNN) and support vector machines (SVMs) deployed on the embedded single-board NVIDIA Jetson TX1. The selected CNN model EfficientNetB0 was used for feature extraction and SVM for classification. Notably, the EfficientNetB0-SVM hybrid model demonstrated impressive efficiency, achieving an average accuracy of 93.54% for classifying static tomato images stored in a board into healthy or reject with a testing time of 0.0216-s per image. Also, during real-time implementation, the proposed hybrid model attained an average inference speed of 15.6 frames per second (15.6 FPS), with an accuracy of 78.57% in classifying actual tomatoes into healthy or reject. The classification decision was taken based on 5 images for each tomato captured at different angles to ensure the detection of any blemishes from almost all sides of the tomato. The performance of the proposed model outperforms that of the state-of-the-art (SOTA) methods in accuracy, testing time per image, and real-time prediction accuracy.
{"title":"Real-Time Tomato Quality Assessment Using Hybrid CNN-SVM Model","authors":"Hassan Shabani Mputu;Ahmed-Abdel Mawgood;Atsushi Shimada;Mohammed S. Sayed","doi":"10.1109/LES.2024.3370634","DOIUrl":"10.1109/LES.2024.3370634","url":null,"abstract":"The current quality assessment for fruits and vegetables relies on subjective human judgment and manual inspection, resulting in inconsistencies and inefficiencies. Due to that, there is a need for a real-time system that can accurately and efficiently assess the quality of fruits and vegetables by analyzing various parameters, such as color, texture, size, and blemishes, to ensure consistency and reduce waste in the food supply chain. This study presents the development of a real-time tomato classification system using a hybrid model that combines convolutional neural network (CNN) and support vector machines (SVMs) deployed on the embedded single-board NVIDIA Jetson TX1. The selected CNN model EfficientNetB0 was used for feature extraction and SVM for classification. Notably, the EfficientNetB0-SVM hybrid model demonstrated impressive efficiency, achieving an average accuracy of 93.54% for classifying static tomato images stored in a board into healthy or reject with a testing time of 0.0216-s per image. Also, during real-time implementation, the proposed hybrid model attained an average inference speed of 15.6 frames per second (15.6 FPS), with an accuracy of 78.57% in classifying actual tomatoes into healthy or reject. The classification decision was taken based on 5 images for each tomato captured at different angles to ensure the detection of any blemishes from almost all sides of the tomato. The performance of the proposed model outperforms that of the state-of-the-art (SOTA) methods in accuracy, testing time per image, and real-time prediction accuracy.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"453-456"},"PeriodicalIF":1.7,"publicationDate":"2024-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140003877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-12DOI: 10.1109/LES.2024.3364698
Mitul Sudhirkumar Nagar;Aditya Mathuriya;Sohan H. Patel;Pinalkumar J. Engineer
Among various platforms for computer vision algorithms, FPGA has gained popularity as a low-power solution. These algorithms involve convolution operation which are extensively performed using signed multipliers. Hence, this work proposes high-speed and energy-efficient signed fixed-point multipliers for digital signal processing (DSP) applications. This work focuses on reducing the combinational path delay (CPD) using LUT-based Booth radix-4 partial product (PP) generation with Bewick’s sign extension and Dadda-based concurrent PP reduction with carry save adder (CSA) for Xilinx (now AMD) FPGA. The proposed design eliminates the requirement of a long carry chain for PP reduction. The proposed multiplier reduces CPD by 3%, 4%, and 16% compared to the state-of-the-art (SoA) multiplier for $8times 8$ , $16times 16$ , and $32times 32$ sizes, respectively. We have also analyzed our proposed $32times 32$ multiplier by pipelining, which offers CPD and EDP reduction by 12.28% and 19.47% at the cost of a 3% and 80% increase in LUTs and flip-flops, respectively, compared to the combinatorial multiplier.
{"title":"High-Speed Energy-Efficient Fixed-Point Signed Multipliers for FPGA-Based DSP Applications","authors":"Mitul Sudhirkumar Nagar;Aditya Mathuriya;Sohan H. Patel;Pinalkumar J. Engineer","doi":"10.1109/LES.2024.3364698","DOIUrl":"10.1109/LES.2024.3364698","url":null,"abstract":"Among various platforms for computer vision algorithms, FPGA has gained popularity as a low-power solution. These algorithms involve convolution operation which are extensively performed using signed multipliers. Hence, this work proposes high-speed and energy-efficient signed fixed-point multipliers for digital signal processing (DSP) applications. This work focuses on reducing the combinational path delay (CPD) using LUT-based Booth radix-4 partial product (PP) generation with Bewick’s sign extension and Dadda-based concurrent PP reduction with carry save adder (CSA) for Xilinx (now AMD) FPGA. The proposed design eliminates the requirement of a long carry chain for PP reduction. The proposed multiplier reduces CPD by 3%, 4%, and 16% compared to the state-of-the-art (SoA) multiplier for \u0000<inline-formula> <tex-math>$8times 8$ </tex-math></inline-formula>\u0000, \u0000<inline-formula> <tex-math>$16times 16$ </tex-math></inline-formula>\u0000, and \u0000<inline-formula> <tex-math>$32times 32$ </tex-math></inline-formula>\u0000 sizes, respectively. We have also analyzed our proposed \u0000<inline-formula> <tex-math>$32times 32$ </tex-math></inline-formula>\u0000 multiplier by pipelining, which offers CPD and EDP reduction by 12.28% and 19.47% at the cost of a 3% and 80% increase in LUTs and flip-flops, respectively, compared to the combinatorial multiplier.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"417-420"},"PeriodicalIF":1.7,"publicationDate":"2024-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139954504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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