Pub Date : 2023-11-03DOI: 10.1109/LES.2023.3329417
Luca Collini;Joey Ah-Kiow;Christian Pilato;Ramesh Karri;Benjamin Tan
Due to the increasing complexity of modern integrated circuits, high-level synthesis (HLS) is becoming a key technology in hardware design. HLS uses optimizations to assist during design space exploration. However, some of them can introduce security weaknesses. We propose an approach that leverages static analysis to identify a class of weaknesses in HLS-generated code. We show that some of these weaknesses can be corrected through the automatic generation of HLS directives. We evaluate our approach by comparing the static analysis results with formal verification. Our results show that the static approach has the same accuracy as formal methods while being $3times $ to $200times $ faster.
{"title":"Using Static Analysis for Enhancing HLS Security","authors":"Luca Collini;Joey Ah-Kiow;Christian Pilato;Ramesh Karri;Benjamin Tan","doi":"10.1109/LES.2023.3329417","DOIUrl":"10.1109/LES.2023.3329417","url":null,"abstract":"Due to the increasing complexity of modern integrated circuits, high-level synthesis (HLS) is becoming a key technology in hardware design. HLS uses optimizations to assist during design space exploration. However, some of them can introduce security weaknesses. We propose an approach that leverages static analysis to identify a class of weaknesses in HLS-generated code. We show that some of these weaknesses can be corrected through the automatic generation of HLS directives. We evaluate our approach by comparing the static analysis results with formal verification. Our results show that the static approach has the same accuracy as formal methods while being \u0000<inline-formula> <tex-math>$3times $ </tex-math></inline-formula>\u0000 to \u0000<inline-formula> <tex-math>$200times $ </tex-math></inline-formula>\u0000 faster.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 2","pages":"166-169"},"PeriodicalIF":1.6,"publicationDate":"2023-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134982022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-27DOI: 10.1109/LES.2023.3328223
Bhanprakash Goswami;Tamoghno Das;Manan Suri
This study investigates the reliability of commonly utilized digital spiking neurons and the potential side-channel vulnerabilities in neuromorphic systems that employ them. Through our experiments, we have successfully decoded the parametric information of Izhikevich and leaky integrate-and-fire (LIF) neuron-based spiking neural networks (SNNs) using differential power analysis. Furthermore, we have demonstrated the practical application of extracted information from the 92% accurate pretrained standard spiking convolution neural network classifier on the FashionMNIST dataset. These findings highlight the potential dangers of utilizing internal information for side-channel and denial-of-service attacks, even when using the usual input as the attack vector.
{"title":"Experimental Investigation of Side-Channel Attacks on Neuromorphic Spiking Neural Networks","authors":"Bhanprakash Goswami;Tamoghno Das;Manan Suri","doi":"10.1109/LES.2023.3328223","DOIUrl":"10.1109/LES.2023.3328223","url":null,"abstract":"This study investigates the reliability of commonly utilized digital spiking neurons and the potential side-channel vulnerabilities in neuromorphic systems that employ them. Through our experiments, we have successfully decoded the parametric information of Izhikevich and leaky integrate-and-fire (LIF) neuron-based spiking neural networks (SNNs) using differential power analysis. Furthermore, we have demonstrated the practical application of extracted information from the 92% accurate pretrained standard spiking convolution neural network classifier on the FashionMNIST dataset. These findings highlight the potential dangers of utilizing internal information for side-channel and denial-of-service attacks, even when using the usual input as the attack vector.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 2","pages":"231-234"},"PeriodicalIF":1.6,"publicationDate":"2023-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134883484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-26DOI: 10.1109/LES.2023.3327793
Mahendra Rathor;Anirban Sengupta
One of the dark side of horizontal semiconductor business model could be the supply of compromised computer-aided design (CAD) tools by an adversary to the designers. A compromised or black-hat high-level synthesis (HLS) tool may secretly insert Trojan into the design being synthesized to affect its functional or nonfunctional aspects. Recently, a black-hat HLS was presented which inserts fake operations during the scheduling process to enable battery exhaustion attack. In this letter, we present a framework to detect the fake operations inserted by a compromised HLS with the help of scheduling information provided by the tool. We implemented our detection framework on a number of benchmarks and analyzed the detection time and accuracy. We also analyzed the cost of fake operation insertion in terms of design area and delay overhead.
{"title":"Revisiting Black-Hat HLS: A Lightweight Countermeasure to HLS-Aided Trojan Attack","authors":"Mahendra Rathor;Anirban Sengupta","doi":"10.1109/LES.2023.3327793","DOIUrl":"10.1109/LES.2023.3327793","url":null,"abstract":"One of the dark side of horizontal semiconductor business model could be the supply of compromised computer-aided design (CAD) tools by an adversary to the designers. A compromised or black-hat high-level synthesis (HLS) tool may secretly insert Trojan into the design being synthesized to affect its functional or nonfunctional aspects. Recently, a black-hat HLS was presented which inserts fake operations during the scheduling process to enable battery exhaustion attack. In this letter, we present a framework to detect the fake operations inserted by a compromised HLS with the help of scheduling information provided by the tool. We implemented our detection framework on a number of benchmarks and analyzed the detection time and accuracy. We also analyzed the cost of fake operation insertion in terms of design area and delay overhead.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 2","pages":"170-173"},"PeriodicalIF":1.6,"publicationDate":"2023-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134883599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-19DOI: 10.1109/LES.2023.3325898
Bilal Mushtaq;Muhammad Abdul Rehman;Sohail Khalid;Majed Alhaisoni
This letter introduces a straightforward method for designing a tri-band bandpass filter using a loaded symmetrical dual-step impedance resonator (D-SIR) structure, augmented by multiple open and short circuit stubs. The resulting filter operates at 2.2, 7.9, and 14.1 GHz, showcasing high-band selectivity. Experimental measurements confirm six transmission zeros and six transmission poles across the passbands, yielding fractional bandwidth (FBW) of 42.6%, 63.8%, and 27.9%. Particularly noteworthy is the broader upper stopband rejection, enhancing the filter’s overall performance. The design achieves impressive performance metrics, with minimal insertion loss (IL) of 0.71, 0.87, and 0.76 dB, accompanied by substantial return loss (RL) of 23, 18, and 13.8 dB across the three passbands. Furthermore, the fabricated design have a compact size of ( $0.20times 0.15$ ) $lambda _{g}$ on a Rogers Duroid RT/5880 substrate. Remarkable agreement between measured and simulated results underscores its viability for Internet of Things-based communication systems.
{"title":"Design of Tri-Band Bandpass Filter Using Modified X-Shaped Structure for IoT-Based Wireless Applications","authors":"Bilal Mushtaq;Muhammad Abdul Rehman;Sohail Khalid;Majed Alhaisoni","doi":"10.1109/LES.2023.3325898","DOIUrl":"10.1109/LES.2023.3325898","url":null,"abstract":"This letter introduces a straightforward method for designing a tri-band bandpass filter using a loaded symmetrical dual-step impedance resonator (D-SIR) structure, augmented by multiple open and short circuit stubs. The resulting filter operates at 2.2, 7.9, and 14.1 GHz, showcasing high-band selectivity. Experimental measurements confirm six transmission zeros and six transmission poles across the passbands, yielding fractional bandwidth (FBW) of 42.6%, 63.8%, and 27.9%. Particularly noteworthy is the broader upper stopband rejection, enhancing the filter’s overall performance. The design achieves impressive performance metrics, with minimal insertion loss (IL) of 0.71, 0.87, and 0.76 dB, accompanied by substantial return loss (RL) of 23, 18, and 13.8 dB across the three passbands. Furthermore, the fabricated design have a compact size of (\u0000<inline-formula> <tex-math>$0.20times 0.15$ </tex-math></inline-formula>\u0000)\u0000<inline-formula> <tex-math>$lambda _{g}$ </tex-math></inline-formula>\u0000 on a Rogers Duroid RT/5880 substrate. Remarkable agreement between measured and simulated results underscores its viability for Internet of Things-based communication systems.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 2","pages":"194-197"},"PeriodicalIF":1.6,"publicationDate":"2023-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135057254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-19DOI: 10.1109/LES.2023.3325578
Muhammad Idrees;Sohail Khalid;Muhammad Abdulrehman;Bilal Mushtaq;Ali Imran Najam;Majed Alhaisoni
This letter presents the design of a microstrip-based diplexer for the applications of the Internet of Things (IoT). By incorporating stub-loaded coupled line resonators, the diplexer achieves significant enhancements in its passband performance. Specifically engineered to operate at precise frequencies of 2.55 and 3.94 GHz, the diplexer demonstrates improved isolation and selectivity through the integration of five transmission poles (TPs). A comprehensive analysis is conducted, evaluating crucial parameters, such as size, insertion loss, return loss, and isolation. The diplexer is fabricated on a compact Rogers Duroid 5880 substrate, and experimental measurements validate its effectiveness, exhibiting a low insertion loss of 0.3 dB at 2.55 GHz and 0.4 dB at 3.94 GHz, in close agreement with simulated predictions. The proposed design, featuring stub-loaded coupled line resonators, showcases highly promising passband characteristics, making it a compelling solution for efficient multiplexing of diverse frequency bands in wireless communication applications within the IoT and network-on-chip (NoC) domains.
{"title":"Design of a Stub-Loaded Coupled Line Diplexer for IoT-Based Applications","authors":"Muhammad Idrees;Sohail Khalid;Muhammad Abdulrehman;Bilal Mushtaq;Ali Imran Najam;Majed Alhaisoni","doi":"10.1109/LES.2023.3325578","DOIUrl":"10.1109/LES.2023.3325578","url":null,"abstract":"This letter presents the design of a microstrip-based diplexer for the applications of the Internet of Things (IoT). By incorporating stub-loaded coupled line resonators, the diplexer achieves significant enhancements in its passband performance. Specifically engineered to operate at precise frequencies of 2.55 and 3.94 GHz, the diplexer demonstrates improved isolation and selectivity through the integration of five transmission poles (TPs). A comprehensive analysis is conducted, evaluating crucial parameters, such as size, insertion loss, return loss, and isolation. The diplexer is fabricated on a compact Rogers Duroid 5880 substrate, and experimental measurements validate its effectiveness, exhibiting a low insertion loss of 0.3 dB at 2.55 GHz and 0.4 dB at 3.94 GHz, in close agreement with simulated predictions. The proposed design, featuring stub-loaded coupled line resonators, showcases highly promising passband characteristics, making it a compelling solution for efficient multiplexing of diverse frequency bands in wireless communication applications within the IoT and network-on-chip (NoC) domains.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 2","pages":"186-189"},"PeriodicalIF":1.6,"publicationDate":"2023-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135058234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-13DOI: 10.1109/LES.2023.3323635
Emre Bilgili;Arda Yurdakul
In deep learning inference, model parameters are pruned and quantized to reduce the model size. Compression methods and common subexpression (CSE) elimination algorithms are applied on sparse constant matrices to deploy the models on low-cost embedded devices. However, the state-of-the-art CSE elimination methods do not scale well for handling large matrices. They reach hours for extracting CSEs in a $200 times 200$ matrix while their matrix multiplication algorithms execute longer than the conventional matrix multiplication methods. Besides, there exist no compression methods for matrices utilizing CSEs. As a remedy to this problem, a random search-based algorithm is proposed in this letter to extract CSEs in the column pairs of a constant matrix. It produces an adder tree for a $1000 times 1000$ matrix in a minute. To compress the adder tree, this letter presents a compression format by extending the compressed sparse row (CSR) to include CSEs. While compression rates of more than 50% can be achieved compared to the original CSR format, simulations for a single-core embedded system show that the matrix multiplication execution time can be reduced by 20%.
{"title":"Common Subexpression-Based Compression and Multiplication of Sparse Constant Matrices","authors":"Emre Bilgili;Arda Yurdakul","doi":"10.1109/LES.2023.3323635","DOIUrl":"10.1109/LES.2023.3323635","url":null,"abstract":"In deep learning inference, model parameters are pruned and quantized to reduce the model size. Compression methods and common subexpression (CSE) elimination algorithms are applied on sparse constant matrices to deploy the models on low-cost embedded devices. However, the state-of-the-art CSE elimination methods do not scale well for handling large matrices. They reach hours for extracting CSEs in a \u0000<inline-formula> <tex-math>$200 times 200$ </tex-math></inline-formula>\u0000 matrix while their matrix multiplication algorithms execute longer than the conventional matrix multiplication methods. Besides, there exist no compression methods for matrices utilizing CSEs. As a remedy to this problem, a random search-based algorithm is proposed in this letter to extract CSEs in the column pairs of a constant matrix. It produces an adder tree for a \u0000<inline-formula> <tex-math>$1000 times 1000$ </tex-math></inline-formula>\u0000 matrix in a minute. To compress the adder tree, this letter presents a compression format by extending the compressed sparse row (CSR) to include CSEs. While compression rates of more than 50% can be achieved compared to the original CSR format, simulations for a single-core embedded system show that the matrix multiplication execution time can be reduced by 20%.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 2","pages":"82-85"},"PeriodicalIF":1.6,"publicationDate":"2023-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136304389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-05DOI: 10.1109/LES.2023.3322301
Lucas Castro;Jonathas Silveira;Rodrigo Zeli;Victor Araújo;Marcelo Guedes;Daniel Lazari;Rodolfo Azevedo;Lucas Wanner
In coherent optics transmission systems, the digital signal processor (DSP) application-specific integrated circuit (ASIC) is the most power-hungry part of the optical transceiver. Already in the edge of transistor technology, to achieve the power budget, we must look for opportunities to further optimize the designs. This letter explores a dynamic duty cycle for reducing the consumption in the pipeline of such DSP ASICs. We exploit the characteristics of estimator algorithms to introduce a dynamic duty cycle, reducing the mean consumption of designs originally constrained only for worst-case scenarios. We present the methodology to implement duty cycle control using the carrier frequency offset estimator (CFE) algorithm as case study, achieving in simulation level from 22% to 74% power consumption reduction in this algorithm, varying on-chip operation conditions.
{"title":"Exploring Dynamic Duty Cycling for Energy Efficiency in Coherent DSP ASIC","authors":"Lucas Castro;Jonathas Silveira;Rodrigo Zeli;Victor Araújo;Marcelo Guedes;Daniel Lazari;Rodolfo Azevedo;Lucas Wanner","doi":"10.1109/LES.2023.3322301","DOIUrl":"10.1109/LES.2023.3322301","url":null,"abstract":"In coherent optics transmission systems, the digital signal processor (DSP) application-specific integrated circuit (ASIC) is the most power-hungry part of the optical transceiver. Already in the edge of transistor technology, to achieve the power budget, we must look for opportunities to further optimize the designs. This letter explores a dynamic duty cycle for reducing the consumption in the pipeline of such DSP ASICs. We exploit the characteristics of estimator algorithms to introduce a dynamic duty cycle, reducing the mean consumption of designs originally constrained only for worst-case scenarios. We present the methodology to implement duty cycle control using the carrier frequency offset estimator (CFE) algorithm as case study, achieving in simulation level from 22% to 74% power consumption reduction in this algorithm, varying on-chip operation conditions.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 2","pages":"202-205"},"PeriodicalIF":1.6,"publicationDate":"2023-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136002620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-02DOI: 10.1109/LES.2023.3321599
Shuo Huai;Hao Kong;Shiqing Li;Xiangzhong Luo;Ravi Subramaniam;Christian Makaya;Qian Lin;Weichen Liu
Edge devices are increasingly utilized for deploying deep learning applications on embedded systems. The real-time nature of many applications and the limited resources of edge devices necessitate latency-targeted neural network compression. However, measuring latency on real devices is challenging and expensive. Therefore, this letter presents a novel and efficient framework, named EvoLP, to accurately predict the inference latency of models on edge devices. This predictor can evolve to achieve higher latency prediction precision during the network compression process. Experimental results demonstrate that EvoLP outperforms previous state-of-the-art approaches by being evaluated on three edge devices and four model variants. Moreover, when incorporated into a model compression framework, it effectively guides the compression process for higher model accuracy while satisfying strict latency constraints. We open-source EvoLP at https://github.com/ntuliuteam/EvoLP .
{"title":"EvoLP: Self-Evolving Latency Predictor for Model Compression in Real-Time Edge Systems","authors":"Shuo Huai;Hao Kong;Shiqing Li;Xiangzhong Luo;Ravi Subramaniam;Christian Makaya;Qian Lin;Weichen Liu","doi":"10.1109/LES.2023.3321599","DOIUrl":"10.1109/LES.2023.3321599","url":null,"abstract":"Edge devices are increasingly utilized for deploying deep learning applications on embedded systems. The real-time nature of many applications and the limited resources of edge devices necessitate latency-targeted neural network compression. However, measuring latency on real devices is challenging and expensive. Therefore, this letter presents a novel and efficient framework, named EvoLP, to accurately predict the inference latency of models on edge devices. This predictor can evolve to achieve higher latency prediction precision during the network compression process. Experimental results demonstrate that EvoLP outperforms previous state-of-the-art approaches by being evaluated on three edge devices and four model variants. Moreover, when incorporated into a model compression framework, it effectively guides the compression process for higher model accuracy while satisfying strict latency constraints. We open-source EvoLP at \u0000<uri>https://github.com/ntuliuteam/EvoLP</uri>\u0000.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 2","pages":"174-177"},"PeriodicalIF":1.6,"publicationDate":"2023-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135910262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Existing miniature DNA sequencing devices hold significant promise to serve as mobile/personal genomic analysis systems in the future. But a key challenge to this vision is the absence of adequate low-power bioinformatic computing ability within the sequencing device itself. In this letter, we discuss the design and demonstrate a system-on-chip (SoC) based on an accelerated RISC-V core for such a task. The chip was fabricated in 22-nm CMOS and executes almost $10times $ faster than a commercial mobile processor on a DNA sequence detection task while achieving $200times $ better energy efficiency.
现有的微型 DNA 测序设备很有希望成为未来的移动/个人基因组分析系统。但实现这一愿景的关键挑战在于测序设备本身缺乏足够的低功耗生物信息计算能力。在这封信中，我们讨论并演示了基于加速 RISC-V 内核的片上系统 (SoC)，以完成这样的任务。该芯片采用 22 纳米 CMOS 制造，在 DNA 序列检测任务上的执行速度比商用移动处理器快近 10 倍，同时能效比商用处理器高 200 倍。
{"title":"An SoC Design for Future Mobile DNA Detection","authors":"Yunus Dawji;Zhongpan Wu;Abel Beyene;Karim Hammad;Ebrahim Ghafar-Zadeh;Sebastian Magierowski","doi":"10.1109/LES.2023.3321587","DOIUrl":"10.1109/LES.2023.3321587","url":null,"abstract":"Existing miniature DNA sequencing devices hold significant promise to serve as mobile/personal genomic analysis systems in the future. But a key challenge to this vision is the absence of adequate low-power bioinformatic computing ability within the sequencing device itself. In this letter, we discuss the design and demonstrate a system-on-chip (SoC) based on an accelerated RISC-V core for such a task. The chip was fabricated in 22-nm CMOS and executes almost \u0000<inline-formula> <tex-math>$10times $ </tex-math></inline-formula>\u0000 faster than a commercial mobile processor on a DNA sequence detection task while achieving \u0000<inline-formula> <tex-math>$200times $ </tex-math></inline-formula>\u0000 better energy efficiency.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 2","pages":"86-89"},"PeriodicalIF":1.6,"publicationDate":"2023-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135846365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-29DOI: 10.1109/LES.2023.3321019
S. Ortega-Cisneros
Neural networks have been used for a long time for image detection and recognition applications due to their ability and efficiency in complex problem solving. Several researchers have chosen to design and develop hardware accelerators for the convolution layer due to the large computational expense consumed by this layer. For that reason, a system that performs indirect GEMM convolution is implemented in a FPGA in this letter. Thus, the input data is segmented and distributed into acceleration modules in a parallel and distributed manner using the Network-on-Chip (NoC) paradigm, and a systolic array (SA) is implemented for the matrix multiplication operation as processing blocks within each NoC Node. Synthesis and performance results show that the implementation of this system presents better results compared to the state of the art in areas, such as acceleration factor, consumption of resources, latency, and operational frequency.
{"title":"Design and Implementation of an NoC-Based Convolution Architecture With GEMM and Systolic Arrays","authors":"S. Ortega-Cisneros","doi":"10.1109/LES.2023.3321019","DOIUrl":"10.1109/LES.2023.3321019","url":null,"abstract":"Neural networks have been used for a long time for image detection and recognition applications due to their ability and efficiency in complex problem solving. Several researchers have chosen to design and develop hardware accelerators for the convolution layer due to the large computational expense consumed by this layer. For that reason, a system that performs indirect GEMM convolution is implemented in a FPGA in this letter. Thus, the input data is segmented and distributed into acceleration modules in a parallel and distributed manner using the Network-on-Chip (NoC) paradigm, and a systolic array (SA) is implemented for the matrix multiplication operation as processing blocks within each NoC Node. Synthesis and performance results show that the implementation of this system presents better results compared to the state of the art in areas, such as acceleration factor, consumption of resources, latency, and operational frequency.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 1","pages":"49-52"},"PeriodicalIF":1.6,"publicationDate":"2023-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135839036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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