Pub Date : 2020-04-20DOI: 10.33180/infmidem2020.101
M. Bhuiyan
The Charge Sensitive Amplifier (CSA) is the key module of the front-end electronics of various types of Silicon detectors and most radiation detection systems. High gain, stability, and low input noise are the major concerns of a typical CSA circuit in order to achieve amplified susceptible input charge (current) for further processing. To design such a low-noise, stable, and low power dissipation solution, a CSA is required to be realized a complementary metal-oxide-semiconductor (CMOS) technology with a compact design. This research reports a low-noise highly stabile CSA design considerations for Silicon detectors applications, which has been designed and validated in TSMC 0.35um CMOS process. In a typical CSA design, the detector capacitance and the input transistor’s width are the most dominating parameters for achieving low noise performance. Therefore, the Equivalent Noise Charge (ENC) with respect to those parameters has been optimized, for a set of detector capacitance from 0.2pF – 2pF. However, the parallel noise of the feedback was removed by adopting a voltage-controlled NMOS resistor, which in turn helped to achieve high stability of the circuit. The simulation results provided a baseline gain of 9.92mV/fC and show that ENC was found to be 42.5e – with 3.72 e – /pF noise slope. The Corner frequency exhibited by the CSA is 1.023GHz and the output magnitude was controlled at -56.8dB; it dissipates 0.23mW from with a single voltage supply of 3.3V with an active die area of 0.0049 mm 2 .
电荷敏感放大器(CSA)是各类硅探测器和大多数辐射探测系统前端电子器件的关键模块。高增益、稳定性和低输入噪声是典型CSA电路的主要关注点，以实现放大的敏感输入电荷(电流)，以便进一步处理。为了设计这样一个低噪声、稳定和低功耗的解决方案，CSA需要实现紧凑设计的互补金属氧化物半导体(CMOS)技术。本研究报告了一种低噪声高稳定的CSA设计考虑，用于硅探测器的应用，该CSA已在台积电0.35um CMOS工艺中设计和验证。在典型的CSA设计中，检测器电容和输入晶体管的宽度是实现低噪声性能的最主要参数。因此，等效噪声电荷(ENC)相对于这些参数进行了优化，一组检测器电容从0.2pF - 2pF。然而，通过采用压控NMOS电阻消除了反馈的并行噪声，从而有助于实现电路的高稳定性。仿真结果提供了9.92mV/fC的基线增益，并且发现ENC为42.5e -，噪声斜率为3.72 e - /pF。CSA显示的拐角频率为1.023GHz，输出幅度控制在-56.8dB;它从3.3V的单电压电源中耗散0.23mW，有效模面积为0.0049 mm 2。
{"title":"A 0.35μm Low-Noise Stable Charge Sensitive Amplifier for Silicon Detectors Applications","authors":"M. Bhuiyan","doi":"10.33180/infmidem2020.101","DOIUrl":"https://doi.org/10.33180/infmidem2020.101","url":null,"abstract":"The Charge Sensitive Amplifier (CSA) is the key module of the front-end electronics of various types of Silicon detectors and most radiation detection systems. High gain, stability, and low input noise are the major concerns of a typical CSA circuit in order to achieve amplified susceptible input charge (current) for further processing. To design such a low-noise, stable, and low power dissipation solution, a CSA is required to be realized a complementary metal-oxide-semiconductor (CMOS) technology with a compact design. This research reports a low-noise highly stabile CSA design considerations for Silicon detectors applications, which has been designed and validated in TSMC 0.35um CMOS process. In a typical CSA design, the detector capacitance and the input transistor’s width are the most dominating parameters for achieving low noise performance. Therefore, the Equivalent Noise Charge (ENC) with respect to those parameters has been optimized, for a set of detector capacitance from 0.2pF – 2pF. However, the parallel noise of the feedback was removed by adopting a voltage-controlled NMOS resistor, which in turn helped to achieve high stability of the circuit. The simulation results provided a baseline gain of 9.92mV/fC and show that ENC was found to be 42.5e – with 3.72 e – /pF noise slope. The Corner frequency exhibited by the CSA is 1.023GHz and the output magnitude was controlled at -56.8dB; it dissipates 0.23mW from with a single voltage supply of 3.3V with an active die area of 0.0049 mm 2 .","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"6 1","pages":"3-14"},"PeriodicalIF":1.2,"publicationDate":"2020-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74997699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-20DOI: 10.33180/infmidem2020.104
P. Petrović
A novel square-wave generator based on a single CCCII (current controlled conveyor), with only two external grounded passive components is proposed in this paper. The circuit provides precise, electronic controllable, voltage or current output square-wave signals. The simulation results using 0.18mm CMOS parameters and experimental verification confirm the feasibility of the proposed circuit. The proposed generator can operate very well up to 25MHz with nonlinearity less than 5%.
{"title":"Simple CMOS Square Wave Generator with Variable Mode Output","authors":"P. Petrović","doi":"10.33180/infmidem2020.104","DOIUrl":"https://doi.org/10.33180/infmidem2020.104","url":null,"abstract":"A novel square-wave generator based on a single CCCII (current controlled conveyor), with only two external grounded passive components is proposed in this paper. The circuit provides precise, electronic controllable, voltage or current output square-wave signals. The simulation results using 0.18mm CMOS parameters and experimental verification confirm the feasibility of the proposed circuit. The proposed generator can operate very well up to 25MHz with nonlinearity less than 5%.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"4 1","pages":"35-46"},"PeriodicalIF":1.2,"publicationDate":"2020-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84263882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-20DOI: 10.33180/infmidem2020.106
B. Ganji, Kamran Delfan Hemmati
In this paper a three-axis capacitor accelerator has been designed, analyzed and optimized using micro-electromechanical systems technology. The accelerometers are generally divided into three categories of single axis, two axes, and three axes in terms of their ability to measure acceleration. In the suggested structure, acceleration measurements are carried out on all three axes simultaneously using a mass and spring system, which makes it possible to achieve a high sensitivity at a low occupancy level without losing other accelerator factors. By taking difference in this structure, it is shown that each axis acceleration has a very low impact on the measured acceleration of the other two axes. If any external factor changes the value of a single capacitor, the original output of the capacitor does not change for detecting acceleration. In other words, the acceleration of any of these three axes, due to its designing features, does not influence the other two axes and the system performance cannot be disrupted by external factors. The other important characteristics of the accelerometers are dynamic range, operating frequency and sensitivity. This study covers a dynamic range up to 1000g and an operating frequency up to 20 kHz. The accelerometer sensitivity is 4fF/g in the z axis direction while it is 9fF/g in the x and y axes directions. In this paper, the simulation of the structure is performed using Intellisuite software. Moreover, a multi-objective genetic optimization algorithm has been used to determine the dimensions of the constituents of the spring and the weight.
{"title":"A Design and Optimization of a New, Three-Axis MEMS Capacitive Accelerometer with High Dynamic Range and Sensitivity","authors":"B. Ganji, Kamran Delfan Hemmati","doi":"10.33180/infmidem2020.106","DOIUrl":"https://doi.org/10.33180/infmidem2020.106","url":null,"abstract":"In this paper a three-axis capacitor accelerator has been designed, analyzed and optimized using micro-electromechanical systems technology. The accelerometers are generally divided into three categories of single axis, two axes, and three axes in terms of their ability to measure acceleration. In the suggested structure, acceleration measurements are carried out on all three axes simultaneously using a mass and spring system, which makes it possible to achieve a high sensitivity at a low occupancy level without losing other accelerator factors. By taking difference in this structure, it is shown that each axis acceleration has a very low impact on the measured acceleration of the other two axes. If any external factor changes the value of a single capacitor, the original output of the capacitor does not change for detecting acceleration. In other words, the acceleration of any of these three axes, due to its designing features, does not influence the other two axes and the system performance cannot be disrupted by external factors. The other important characteristics of the accelerometers are dynamic range, operating frequency and sensitivity. This study covers a dynamic range up to 1000g and an operating frequency up to 20 kHz. The accelerometer sensitivity is 4fF/g in the z axis direction while it is 9fF/g in the x and y axes directions. In this paper, the simulation of the structure is performed using Intellisuite software. Moreover, a multi-objective genetic optimization algorithm has been used to determine the dimensions of the constituents of the spring and the weight.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"5 1","pages":"55-66"},"PeriodicalIF":1.2,"publicationDate":"2020-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78609076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-01-30DOI: 10.33180/infmidem2019.402
David Neels Ponkumar Devadhas
Network on Chip (NoC) is an advanced integration design for communication networks and used as modules in System on Chip (SoC) designs. It provides the solution to the problem of traditional bus based SoC. A router is a key component which is considered as backbone of communication in NoC .The objective is to design a priority based reconfigurable router. Initially a 4x4 VLSI router is designed and synthesised, then the channels inside the router are modified to achieve reconfiguration in order to improve the efficiency of the router. In 4x4 Reconfigurable Router the slots are well utilized but prioritization was not considered. Since routers are associatedwith switches to take data transfer decisions and results in high power consumption. In order to overcome this problem, new priority based reconfigurable router is designed. The design entry for router is done using Verilog HDL, The design is synthesized and simulated using Xilinx ISE Design Suite 14.3 & ModelSim -Altera 6.5b software respectively and the corresponding results in terms of power and delay are analysed.
片上网络(NoC)是一种先进的通信网络集成设计，在片上系统(SoC)设计中用作模块。它解决了传统基于总线的SoC存在的问题。路由器是NoC中通信骨干的关键部件，其目的是设计一种基于优先级的可重构路由器。首先设计并合成了一个4x4 VLSI路由器，然后对路由器内部的通道进行修改以实现重新配置，以提高路由器的效率。在4x4可重构路由器中，插槽得到了很好的利用，但没有考虑优先级。由于路由器与交换机相关联，以采取数据传输决策，并导致高功耗。为了克服这一问题，设计了一种新的基于优先级的可重构路由器。采用Verilog HDL语言完成了路由器的设计输入，并分别使用Xilinx ISE design Suite 14.3和ModelSim -Altera 6.5b软件对设计进行了综合仿真，并对相应的功耗和时延结果进行了分析。
{"title":"Design of Priority Based Reconfigurable Router in Network on Chip","authors":"David Neels Ponkumar Devadhas","doi":"10.33180/infmidem2019.402","DOIUrl":"https://doi.org/10.33180/infmidem2019.402","url":null,"abstract":"Network on Chip (NoC) is an advanced integration design for communication networks and used as modules in System on Chip (SoC) designs. It provides the solution to the problem of traditional bus based SoC. A router is a key component which is considered as backbone of communication in NoC .The objective is to design a priority based reconfigurable router. Initially a 4x4 VLSI router is designed and synthesised, then the channels inside the router are modified to achieve reconfiguration in order to improve the efficiency of the router. In 4x4 Reconfigurable Router the slots are well utilized but prioritization was not considered. Since routers are associatedwith switches to take data transfer decisions and results in high power consumption. In order to overcome this problem, new priority based reconfigurable router is designed. The design entry for router is done using Verilog HDL, The design is synthesized and simulated using Xilinx ISE Design Suite 14.3 & ModelSim -Altera 6.5b software respectively and the corresponding results in terms of power and delay are analysed.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"5 1","pages":"203-210"},"PeriodicalIF":1.2,"publicationDate":"2020-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87111411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-01-30DOI: 10.33180/infmidem2019.403
Jirapun Pimpol
In this work, we propose a resistorless realization of the simple capacitance multiplier circuit with electronically controllable using a single voltage differencing gain amplifier (VDGA) as an active building block. The circuit utilizes one VDGA and only one capacitor in a simple circuit configuration. The proposed capacitance multiplier circuit can be tuned electronically with the adjustment of the transconductance gains of the VDGA. To emphasis the workability of the proposed circuit, the second-order RC low-pass filter is constructed as an application example. PSPICE simulations are performed to verify the theory.
{"title":"Electronically Adjustable Capacitance Multiplier Circuit with a Single Voltage Differencing Gain Amplifier (VDGA)","authors":"Jirapun Pimpol","doi":"10.33180/infmidem2019.403","DOIUrl":"https://doi.org/10.33180/infmidem2019.403","url":null,"abstract":"In this work, we propose a resistorless realization of the simple capacitance multiplier circuit with electronically controllable using a single voltage differencing gain amplifier (VDGA) as an active building block. The circuit utilizes one VDGA and only one capacitor in a simple circuit configuration. The proposed capacitance multiplier circuit can be tuned electronically with the adjustment of the transconductance gains of the VDGA. To emphasis the workability of the proposed circuit, the second-order RC low-pass filter is constructed as an application example. PSPICE simulations are performed to verify the theory.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"68 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2020-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84187141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-01-30DOI: 10.33180/infmidem2019.406
S. Padmapriya
Reconfigurability, low complexity and low power are the key requirements of FIR filters employed in multi-standard wireless communication systems. Digital Filters are used to filter the audio data stream and increase the reliability of speech signal. Therefore, it is imperative to design an area optimized and low power based reconfigurable FIR filter architectures. The reconfigurable architecture designed in this research is capable of achieving lower adaptation-delay and area-delay-power efficient implementation of a Delayed Least Mean Square (DLMS) adaptive filter with reversible logic gates. The Optimized Adaptive Reconfigurable Adaptive Reconfigurable (OAR) FIR filter architectures are proposed. The optimized architectures are implemented across the combinational blocks by reducing the pipeline delays, sampling period, energy consumption and area, to increase the Power-Delay Product (PDP) and Energy Per Sample (EPS).The noisy speech signals are used for verifying the efficiency of the proposed architectures. The efficiency of the architecture is verified by implementing the proposed scheme in signal corrupted by various real-time noises at different Signal to Noise Ratios (SNRs).
{"title":"Design of an Optimized Twin Mode Reconfigurable Adaptive FIR Filter Architecture for Speech Signal Processing","authors":"S. Padmapriya","doi":"10.33180/infmidem2019.406","DOIUrl":"https://doi.org/10.33180/infmidem2019.406","url":null,"abstract":"Reconfigurability, low complexity and low power are the key requirements of FIR filters employed in multi-standard wireless communication systems. Digital Filters are used to filter the audio data stream and increase the reliability of speech signal. Therefore, it is imperative to design an area optimized and low power based reconfigurable FIR filter architectures. The reconfigurable architecture designed in this research is capable of achieving lower adaptation-delay and area-delay-power efficient implementation of a Delayed Least Mean Square (DLMS) adaptive filter with reversible logic gates. The Optimized Adaptive Reconfigurable Adaptive Reconfigurable (OAR) FIR filter architectures are proposed. The optimized architectures are implemented across the combinational blocks by reducing the pipeline delays, sampling period, energy consumption and area, to increase the Power-Delay Product (PDP) and Energy Per Sample (EPS).The noisy speech signals are used for verifying the efficiency of the proposed architectures. The efficiency of the architecture is verified by implementing the proposed scheme in signal corrupted by various real-time noises at different Signal to Noise Ratios (SNRs).","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"20 1","pages":"241-254"},"PeriodicalIF":1.2,"publicationDate":"2020-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74057110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-01-30DOI: 10.33180/infmidem2019.405
M. Kunaver
Computer aided circuit design is becoming one of the mainstream methods for helping circuit designers. Multiple new methods have been developed in this field including Evolutionary Electronics. A lot of work has been done in this field but there is still a room for improvement since some of the solutions lack the flexibility (diversity of components, limited topology etc.) in circuit design or lack complex fitness functions that would enable the synthesis of more complex circuits. The research presented in this article aims to improve this by introducing Grammatical Evolution-based approach for circuit synthesis. Grammatical Evolution offers great flexibility since it is rule based – adding a new element is as simple as writing one additional line of initialization code. In addition, the use of a complex multi-criteria function allows us to create circuits that can be as complex as required thus further increasing the flexibility of the approach. To achieve this, we use a combination of Python and SPICE to create a series of netlists, evaluate them in the PyOpus environment, and select the best possible circuit for the task. We demonstrate the efficiency of our approach in three different case studies where we automatically generate oscillators and high/low-pass filters of second and third order.
{"title":"Grammatical Evolution-based Analog Circuit Synthesis","authors":"M. Kunaver","doi":"10.33180/infmidem2019.405","DOIUrl":"https://doi.org/10.33180/infmidem2019.405","url":null,"abstract":"Computer aided circuit design is becoming one of the mainstream methods for helping circuit designers. Multiple new methods have been developed in this field including Evolutionary Electronics. A lot of work has been done in this field but there is still a room for improvement since some of the solutions lack the flexibility (diversity of components, limited topology etc.) in circuit design or lack complex fitness functions that would enable the synthesis of more complex circuits. The research presented in this article aims to improve this by introducing Grammatical Evolution-based approach for circuit synthesis. Grammatical Evolution offers great flexibility since it is rule based – adding a new element is as simple as writing one additional line of initialization code. In addition, the use of a complex multi-criteria function allows us to create circuits that can be as complex as required thus further increasing the flexibility of the approach. To achieve this, we use a combination of Python and SPICE to create a series of netlists, evaluate them in the PyOpus environment, and select the best possible circuit for the task. We demonstrate the efficiency of our approach in three different case studies where we automatically generate oscillators and high/low-pass filters of second and third order.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"33 1","pages":"229-240"},"PeriodicalIF":1.2,"publicationDate":"2020-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74302883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-01-30DOI: 10.33180/infmidem2019.407
R. Razman, A. Sešek, J. Tasic, J. Trontelj
Blood glycemic level, also known as blood sugar level or blood glucose level, especially that reaching high values (hyper glycaemia) and persisting in time, is strongly linked to the development of type 2 diabetes and consequently serious medical conditions such as neuropathy, cardiovascular diseases, sensitivity to infections etc. Nowadays the only effective and reliable way of monitoring blood sugar level is to directly analyze the blood (capillary or venous), interstitial or other body fluids. The former method is the most used. Its main disadvantage is puncturing of patient skin (finger pricking for example) which frequently causes pain and the risk of viruses and bacteria entering the body. The development of an effective and accurate noninvasive method for blood glucose monitoring has been recognized as a crucial goal for future studies of blood sugar and implementations of such methods into wearable devices. In this paper, we propose monitoring of blood glucose level employing skin impedance measurement. A measurement system featuring an Application-Specific Integrated Circuit (ASIC) is presented and analyzed. The fabricated ASIC in 350 nm CMOS technology with dimensions 1223 μm x 1388 μm, typically consumes 450 μA at 3.3 V supply voltage and operates in frequency region from 5 kHz to 16 MHz. The system exhibits a good linear response for loads up to a few kΩ, making it suitable for skin impedance measurements.
{"title":"Blood Sugar Level Monitoring","authors":"R. Razman, A. Sešek, J. Tasic, J. Trontelj","doi":"10.33180/infmidem2019.407","DOIUrl":"https://doi.org/10.33180/infmidem2019.407","url":null,"abstract":"Blood glycemic level, also known as blood sugar level or blood glucose level, especially that reaching high values (hyper glycaemia) and persisting in time, is strongly linked to the development of type 2 diabetes and consequently serious medical conditions such as neuropathy, cardiovascular diseases, sensitivity to infections etc. Nowadays the only effective and reliable way of monitoring blood sugar level is to directly analyze the blood (capillary or venous), interstitial or other body fluids. The former method is the most used. Its main disadvantage is puncturing of patient skin (finger pricking for example) which frequently causes pain and the risk of viruses and bacteria entering the body. The development of an effective and accurate noninvasive method for blood glucose monitoring has been recognized as a crucial goal for future studies of blood sugar and implementations of such methods into wearable devices. In this paper, we propose monitoring of blood glucose level employing skin impedance measurement. A measurement system featuring an Application-Specific Integrated Circuit (ASIC) is presented and analyzed. The fabricated ASIC in 350 nm CMOS technology with dimensions 1223 μm x 1388 μm, typically consumes 450 μA at 3.3 V supply voltage and operates in frequency region from 5 kHz to 16 MHz. The system exhibits a good linear response for loads up to a few kΩ, making it suitable for skin impedance measurements.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"61 1","pages":"255-260"},"PeriodicalIF":1.2,"publicationDate":"2020-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89280202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-01-01DOI: 10.33180/infmidem2020.105
Peng Si, Kai Zhang, Tianyu Yu, Zhifeng Zhao, Wei-feng Lü
The negative capacitance field-effect transistor can break the limitation of the Boltzmann tyranny. In this study, the analog and radio-frequency (RF) performance of a nanometer negative-capacitance fully depleted silicon-on-insulator (NC-FDSOI) transistor is investigated. The analog/RF parameters of the NC-FDSOI device are compared with the conventional FDSOI counterparts for transconductance, output conductance, gate capacitance, cutoff frequency, and maximum oscillation frequency. In addition, the effect of ferroelectric thickness on the analog/RF performance of NC-FDSOI device is analyzed and discussed. The results show that even when operated at low voltages, NC-FDSOI transistors enable analog/RF performance improvement in traditional FDSOI counterparts at low power in the case of a suitable ferroelectric thickness.
{"title":"Analog / Radio-Frequency Performance Analysis of Nanometer Negative Capacitance Fully Depleted Silicon-On-Insulator Transistors","authors":"Peng Si, Kai Zhang, Tianyu Yu, Zhifeng Zhao, Wei-feng Lü","doi":"10.33180/infmidem2020.105","DOIUrl":"https://doi.org/10.33180/infmidem2020.105","url":null,"abstract":"The negative capacitance field-effect transistor can break the limitation of the Boltzmann tyranny. In this study, the analog and radio-frequency (RF) performance of a nanometer negative-capacitance fully depleted silicon-on-insulator (NC-FDSOI) transistor is investigated. The analog/RF parameters of the NC-FDSOI device are compared with the conventional FDSOI counterparts for transconductance, output conductance, gate capacitance, cutoff frequency, and maximum oscillation frequency. In addition, the effect of ferroelectric thickness on the analog/RF performance of NC-FDSOI device is analyzed and discussed. The results show that even when operated at low voltages, NC-FDSOI transistors enable analog/RF performance improvement in traditional FDSOI counterparts at low power in the case of a suitable ferroelectric thickness.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"30 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72509311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-18DOI: 10.33180/infmidem2019.307
M. Kovačič, J. Krč, B. Lipovšek, Wei‐Chao Chen, M. Edoff, P. Bolt, J. Deelen, M. Zhukova, J. Lontchi, D. Flandre, P. Salomé, M. Topič
Chalcopyrite solar cells exhibit one of the highest conversion efficiencies among thin-film solar cell technologies (> 23.3%), however a considerably thick absorber ≥1.8 μm is required for an efficient absorption of the long-wavelength light and collection of charge carriers. In order to minimize the material consumption and to accelerate the fabrication process, further thinning down of the absorber layer is important. Using a thin absorber layer results in a highly reduced photocurrent density and to compensate for it an effective light management needs to be introduced. Experimentally supported, advanced optical simulations in a PV module configuration, i.e. solar cell structure including the encapsulation and front glass are employed to design solutions to increase the short current density of devices with ultra-thin (500 nm) absorbers. In particular (i) highly reflective metal back reflector (BR), (ii) internal nano-textures and (iii) external textures by applying a light management (LM) foil are investigated by simulations. Experimental verification of simulation results is presented for the external texture case. In the scope of this contribution we show that any individual aforementioned approach is not sufficient to compensate for the short circuit current drop of the thin CIGS, but only a combination of highly reflective back contact and introduction of textures (internal or external) is able to compensate and also to exceed (by more than 5 % for internal texture) photocurrent density of a thick (1800 nm) CIGS absorber.
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