Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607128
Zhao Zhendong, L. Zhigang, Zhang Yu, Shu Xuefeng
The purpose of this paper is to study the combined effect of moisture absorption and void growing on the reliability of electronic packaging. Finite element simulation on a plastic PBGA package was carried out for moisture history from the moisture preconditioning (85 degC / 85 % RH for 168 h) to subsequent exposure to a lead-free soldering process, and the rule of moisture diffusion and the change of stress was found. Then, with the implementation of interface properties into the model study, the critical stress that results in the unstable void growth and the delamination at interface is significantly reduced and comparable to the magnitude of vapor pressure. Finite element results give a good guideline on the underfill material selection, and also give an insight of the failure mechanism associated with moisture absorption.
{"title":"Moisture absorption and void growing effects on failure of electronic packaging","authors":"Zhao Zhendong, L. Zhigang, Zhang Yu, Shu Xuefeng","doi":"10.1109/ICEPT.2008.4607128","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607128","url":null,"abstract":"The purpose of this paper is to study the combined effect of moisture absorption and void growing on the reliability of electronic packaging. Finite element simulation on a plastic PBGA package was carried out for moisture history from the moisture preconditioning (85 degC / 85 % RH for 168 h) to subsequent exposure to a lead-free soldering process, and the rule of moisture diffusion and the change of stress was found. Then, with the implementation of interface properties into the model study, the critical stress that results in the unstable void growth and the delamination at interface is significantly reduced and comparable to the magnitude of vapor pressure. Finite element results give a good guideline on the underfill material selection, and also give an insight of the failure mechanism associated with moisture absorption.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88494618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607021
Li Jiao, Zhang Jinyi, Shi Hui, L. Wei
Test time optimization is necessary for modular testing of hierarchical system-on-chip (SOC) that contain embedded IP core. In this paper, we consider the case of non-interactive design transfer between IP core vendor and IC integrator. We proposes a method based on genetic algorithm which can efficiently optimize the test time of hierarchical SOC. Utilizing international reference circuit provided by International Test conference 2002(ITCpsila02), we execute the experiment and results suggest that this method is superior than recently proposes methods for hierarchical SOC test time.
{"title":"Optimization of hierarchical SOC test time based on genetic algorithm","authors":"Li Jiao, Zhang Jinyi, Shi Hui, L. Wei","doi":"10.1109/ICEPT.2008.4607021","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607021","url":null,"abstract":"Test time optimization is necessary for modular testing of hierarchical system-on-chip (SOC) that contain embedded IP core. In this paper, we consider the case of non-interactive design transfer between IP core vendor and IC integrator. We proposes a method based on genetic algorithm which can efficiently optimize the test time of hierarchical SOC. Utilizing international reference circuit provided by International Test conference 2002(ITCpsila02), we execute the experiment and results suggest that this method is superior than recently proposes methods for hierarchical SOC test time.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91288581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607038
Rong Zhang, S. Lee
A novel encapsulation process for wafer level LED arrays is presented. In this process, 4 inch P-type single crystal silicon wafers served as the substrates for flip-chip mountable LED chips. The wafer substrates were fabricated by wafer level lithography and plating process. An UV curable epoxy was applied as the encapsulant. The encapsulation process takes advantage of square trenches fabricated by deep reaction ion etching (DRIE) process as barriers to limit the spread of the epoxy encapsulant, and can adjust the geometry of the encapsulation via controlling the volume of the epoxy and the dimension of the trenches. The packaging and encapsulation process of LED arrays were completed on wafer level. LED packages can be directly obtained after wafer dicing.
提出了一种新的晶圆级LED阵列封装工艺。在该工艺中，4英寸p型单晶硅片作为倒装LED芯片的衬底。采用晶圆级光刻和电镀工艺制备晶圆基板。采用紫外光固化环氧树脂作为包封剂。该封装工艺利用深反应离子蚀刻(deep reaction ion etching, DRIE)工艺制备的方形沟槽作为屏障，限制环氧封装剂的扩散，并通过控制环氧树脂的体积和沟槽的尺寸来调整封装的几何形状。LED阵列的封装和封装工艺在晶圆级完成。晶圆切割后可直接获得LED封装。
{"title":"Wafer level LED packaging with integrated DRIE trenches for encapsulation","authors":"Rong Zhang, S. Lee","doi":"10.1109/ICEPT.2008.4607038","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607038","url":null,"abstract":"A novel encapsulation process for wafer level LED arrays is presented. In this process, 4 inch P-type single crystal silicon wafers served as the substrates for flip-chip mountable LED chips. The wafer substrates were fabricated by wafer level lithography and plating process. An UV curable epoxy was applied as the encapsulant. The encapsulation process takes advantage of square trenches fabricated by deep reaction ion etching (DRIE) process as barriers to limit the spread of the epoxy encapsulant, and can adjust the geometry of the encapsulation via controlling the volume of the epoxy and the dimension of the trenches. The packaging and encapsulation process of LED arrays were completed on wafer level. LED packages can be directly obtained after wafer dicing.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76859073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607042
Yi Fan, Yifeng Fu, Yan Zhang, Teng Wang, Xiaojing Wang, Z. Cheng, J. Liu
In this work, silicon microchannel coolers were made using the deep ion reactive etching (DIRE) technique. Stable and homogeneous carbon nanotube (CNT) suspension was also prepared. Meanwhile, a closed-loop cooling test system was developed to investigate the heat removal of the silicon microchannel cooler with different coolants. The experimental setup included a test module, a minipump for providing controllable flow, and a fan system for cooling the circular fluid. Beside the inlet and outlet of the test module, two thermocouples and pressure gauges were set up to measure the temperature and pressure of the fluids. The heat removal of the silicon microchannel cooler using different CNT volume fraction of suspension coolant was studied. The results show that the microchannel cooler with CNT suspension as coolant could strengthen the heat removal capability of microchannel cooler. In addition to heat transfer enhancement, the microchannel cooler with CNT suspension coolant did not produce extra pressure drop in the present study.
{"title":"A study of fluid coolant with carbon nanotube suspension for microchannel coolers","authors":"Yi Fan, Yifeng Fu, Yan Zhang, Teng Wang, Xiaojing Wang, Z. Cheng, J. Liu","doi":"10.1109/ICEPT.2008.4607042","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607042","url":null,"abstract":"In this work, silicon microchannel coolers were made using the deep ion reactive etching (DIRE) technique. Stable and homogeneous carbon nanotube (CNT) suspension was also prepared. Meanwhile, a closed-loop cooling test system was developed to investigate the heat removal of the silicon microchannel cooler with different coolants. The experimental setup included a test module, a minipump for providing controllable flow, and a fan system for cooling the circular fluid. Beside the inlet and outlet of the test module, two thermocouples and pressure gauges were set up to measure the temperature and pressure of the fluids. The heat removal of the silicon microchannel cooler using different CNT volume fraction of suspension coolant was studied. The results show that the microchannel cooler with CNT suspension as coolant could strengthen the heat removal capability of microchannel cooler. In addition to heat transfer enhancement, the microchannel cooler with CNT suspension coolant did not produce extra pressure drop in the present study.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78498910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606963
Wenming Liu, Mingxiang Chen, Yanyan Xi, Changyong Lin, Sheng Liu
In this paper, a non-linear and one-directional coupled finite element framework has been implemented to simulate induction heating process of wafer-level packaging. Based on numerical results of induction heating, thermally-caused warpages and stresses of the single-sided ceramic wafer have been evaluated. Some primary experiments have also been conducted to verify the numerical method. Using three-dimensional models, the temperature distribution, thermally-caused warpages and stress in the single-sided ceramic wafer subjected to induction heating can be clearly defined. In addition, the temperature-dependent material properties are considered in the modeling. From the finite element analysis, it is found that the induction heating is selective, that is, the temperature in the wafer is lower than that of Cu-loops during the induction heating process; the temperature variation on the Cu-loops, as well as the difference of the temperature between the Cu-loops and the wafer is related with the wafer material properties; the maximum thermal-stresses caused by the induced Joule heating occur on the middle-edge areas of the single-sided ceramic wafer. On the other hand, in order to prove the soundness of the framework established in this paper, the test results obtained by infrared radiometer are compared to that achieved from the proposed numerical analysis method. It is shown that the temperature variation and locations of initial cracks caused by thermal-stresses during the induction heating are in a good agreement with those obtained from the test.
{"title":"Thermo-mechanical analysis of a wafer level packaging by induction heating","authors":"Wenming Liu, Mingxiang Chen, Yanyan Xi, Changyong Lin, Sheng Liu","doi":"10.1109/ICEPT.2008.4606963","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606963","url":null,"abstract":"In this paper, a non-linear and one-directional coupled finite element framework has been implemented to simulate induction heating process of wafer-level packaging. Based on numerical results of induction heating, thermally-caused warpages and stresses of the single-sided ceramic wafer have been evaluated. Some primary experiments have also been conducted to verify the numerical method. Using three-dimensional models, the temperature distribution, thermally-caused warpages and stress in the single-sided ceramic wafer subjected to induction heating can be clearly defined. In addition, the temperature-dependent material properties are considered in the modeling. From the finite element analysis, it is found that the induction heating is selective, that is, the temperature in the wafer is lower than that of Cu-loops during the induction heating process; the temperature variation on the Cu-loops, as well as the difference of the temperature between the Cu-loops and the wafer is related with the wafer material properties; the maximum thermal-stresses caused by the induced Joule heating occur on the middle-edge areas of the single-sided ceramic wafer. On the other hand, in order to prove the soundness of the framework established in this paper, the test results obtained by infrared radiometer are compared to that achieved from the proposed numerical analysis method. It is shown that the temperature variation and locations of initial cracks caused by thermal-stresses during the induction heating are in a good agreement with those obtained from the test.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74988434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607146
Ting-biao Jiang, Hong-mi Nong, C. Du
The interface crack caused by moisture absorption is a main reason for the failure of plastic packaging electronic devices. According to the failure of interface cracks in QFN plastic packaging devices caused by hygro-thermal environment, the paper combining with finite element method (FEM), carried on the research by moisture absorption experiment, lead-free reflow soldering experiment, high temperature tidal thermal experiment, and scanning electron microscope (SEM) experiment. The results of study show that: non-moisture absorption devices seldom produce cracks after the lead-free reflow soldering, and moisture absorption devices donpsilat produce any crack during absorbing moisture, but they easily produce cracks after lead-free reflow soldering; The cracks produced by the experiment mainly lay on the interface between die-attach material (DA) and the chip, and the cracks at the junction of chip, DA material and epoxy molding compound material (EMC) have the greatest damage; The position and the expansion direction of cracks are closely related to the characteristic and the interface intensity of the two connecting materials. These conclusions have important practical significance to the study and the evaluation criterion of crack.
{"title":"Study of interface reliability in QFN device under hygro-thermal environment","authors":"Ting-biao Jiang, Hong-mi Nong, C. Du","doi":"10.1109/ICEPT.2008.4607146","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607146","url":null,"abstract":"The interface crack caused by moisture absorption is a main reason for the failure of plastic packaging electronic devices. According to the failure of interface cracks in QFN plastic packaging devices caused by hygro-thermal environment, the paper combining with finite element method (FEM), carried on the research by moisture absorption experiment, lead-free reflow soldering experiment, high temperature tidal thermal experiment, and scanning electron microscope (SEM) experiment. The results of study show that: non-moisture absorption devices seldom produce cracks after the lead-free reflow soldering, and moisture absorption devices donpsilat produce any crack during absorbing moisture, but they easily produce cracks after lead-free reflow soldering; The cracks produced by the experiment mainly lay on the interface between die-attach material (DA) and the chip, and the cracks at the junction of chip, DA material and epoxy molding compound material (EMC) have the greatest damage; The position and the expansion direction of cracks are closely related to the characteristic and the interface intensity of the two connecting materials. These conclusions have important practical significance to the study and the evaluation criterion of crack.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75573380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607110
Xing Jin, M. Li
To conform to the ever-emerging market demand, stacked memory devices have been more widely utilized. The stacking method also reduces the cost of electronical components through the way that stacking could fully utilize currently on-hand equipment without any new investment. While, starting from late 2003, flash memory manufacturers begin experience capacity degradation, specifically with multiple loop-back workflows induced by stack CSP devices. By analyzing the process of stacking, the industrypsilas practice considers the control of assembly cost largely depends on the improvement of overall line productivity, specifically the critical bottle-neck area of die bonding. This presentation intends to critically describe the methodology and procedures used by Intelpsilas stack CSP assembly factory, which finally results innovative projects targeting above said productivity improvements. The authors use TRIZ, an inventive problem solving theory and application tool, to analyze and abstract the major contradictions and then sketch out possible solutions. As a result of the applications, the overall stack CSP assembly factorypsilas productivity increased to a record-high of 340%, far above the industry average, and supports Intelpsilas stack CSP assembly factory more efficient than benchmarking world-class companies ever since. The authors of this paper wishes the methodology on productivity and design flexibility at Intelpsilas stack CSP assembly factory could possibly be proliferated, so as to help achieve productivity and capability maximum output throughout the industry.
{"title":"Productivity improvement of stack package line through die bonding process & scheme optimization","authors":"Xing Jin, M. Li","doi":"10.1109/ICEPT.2008.4607110","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607110","url":null,"abstract":"To conform to the ever-emerging market demand, stacked memory devices have been more widely utilized. The stacking method also reduces the cost of electronical components through the way that stacking could fully utilize currently on-hand equipment without any new investment. While, starting from late 2003, flash memory manufacturers begin experience capacity degradation, specifically with multiple loop-back workflows induced by stack CSP devices. By analyzing the process of stacking, the industrypsilas practice considers the control of assembly cost largely depends on the improvement of overall line productivity, specifically the critical bottle-neck area of die bonding. This presentation intends to critically describe the methodology and procedures used by Intelpsilas stack CSP assembly factory, which finally results innovative projects targeting above said productivity improvements. The authors use TRIZ, an inventive problem solving theory and application tool, to analyze and abstract the major contradictions and then sketch out possible solutions. As a result of the applications, the overall stack CSP assembly factorypsilas productivity increased to a record-high of 340%, far above the industry average, and supports Intelpsilas stack CSP assembly factory more efficient than benchmarking world-class companies ever since. The authors of this paper wishes the methodology on productivity and design flexibility at Intelpsilas stack CSP assembly factory could possibly be proliferated, so as to help achieve productivity and capability maximum output throughout the industry.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74739928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607156
Chen Lei
Interconnect test technology has become a bottleneck in the application of multi-chip module (MCM), so study on new methods of test generation to acquire better test set is significant. This paper presents a novel optimization approach of adaptive genetic algorithm (AGA) for the MCM interconnect test generation problem. By combing the characteristics of MCM interconnect test, an accurate fitness function is designed to compute the fitness of each candidate vector. AGA is composed of populations of chromosomes and three evolutionary operators: selection, crossover and mutation. The international standard MCM benchmark circuit was used to verify the approach. Comparing with not only the evolutionary algorithms, but also the deterministic algorithms, experimental results demonstrate that the hybrid approach can achieve high fault coverage, short CPU time and compact test set, which shows that it is a novel optimized method deserving research.
{"title":"MCM interconnect test scheme based on adaptive genetic algorithm","authors":"Chen Lei","doi":"10.1109/ICEPT.2008.4607156","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607156","url":null,"abstract":"Interconnect test technology has become a bottleneck in the application of multi-chip module (MCM), so study on new methods of test generation to acquire better test set is significant. This paper presents a novel optimization approach of adaptive genetic algorithm (AGA) for the MCM interconnect test generation problem. By combing the characteristics of MCM interconnect test, an accurate fitness function is designed to compute the fitness of each candidate vector. AGA is composed of populations of chromosomes and three evolutionary operators: selection, crossover and mutation. The international standard MCM benchmark circuit was used to verify the approach. Comparing with not only the evolutionary algorithms, but also the deterministic algorithms, experimental results demonstrate that the hybrid approach can achieve high fault coverage, short CPU time and compact test set, which shows that it is a novel optimized method deserving research.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74808239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607085
Li Xu, Cong Yue, J. Liu, Yan Zhang, Xiuzhen Lu, Z. Cheng
Heat dissipation of electronic packages has become one of the limiting factors to miniaturization. The removal of the heat generated is a critical issue in electronic packaging. With the development of thermal management, thermal interface material (TIM) plays a more and more important role in electronics packaging. A new nano-TIM with nanofibers prepared by using electrospinning has been suggested in recent years. In this experiment study, the carbon nanotube (CNT) nano-particles were added into the polymer solution before the electrospinning to improve the thermal conductivity of nano-TIM. The polymer solution of polyurethane was used for present electrospinning. The effects of a number of process parameters in the electrospinning were studied in this work. Different variables such as the distance between needle tip and collector, the voltage applied, and CNT nano-particles content were studied. The scanning electron microscopy (SEM) was used to characterize nano-TIMs with CNT nano-particles.
{"title":"Nano-thermal interface material with CNT nano-particles for heat dissipation application","authors":"Li Xu, Cong Yue, J. Liu, Yan Zhang, Xiuzhen Lu, Z. Cheng","doi":"10.1109/ICEPT.2008.4607085","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607085","url":null,"abstract":"Heat dissipation of electronic packages has become one of the limiting factors to miniaturization. The removal of the heat generated is a critical issue in electronic packaging. With the development of thermal management, thermal interface material (TIM) plays a more and more important role in electronics packaging. A new nano-TIM with nanofibers prepared by using electrospinning has been suggested in recent years. In this experiment study, the carbon nanotube (CNT) nano-particles were added into the polymer solution before the electrospinning to improve the thermal conductivity of nano-TIM. The polymer solution of polyurethane was used for present electrospinning. The effects of a number of process parameters in the electrospinning were studied in this work. Different variables such as the distance between needle tip and collector, the voltage applied, and CNT nano-particles content were studied. The scanning electron microscopy (SEM) was used to characterize nano-TIMs with CNT nano-particles.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73248712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607147
Y.H. Xia, W. Jillek, E. Schmitt
Electrochemical migration (ECM) of lead-free solder joints were investigated by water drop test method. Nine types solder pastes were employed to compare the ECM susceptible. The effects of applied voltage, electrodes spacing and flux residue on the ECM were in-situ observed. The microstructure and composition of the growing dendrites during ECM were detected. The results revealed that higher voltage and narrower spacing weakened the ECM reliability of solder joints. The flux residua inhibited the occurrence of ECM. The main migration element was Pb in Pb-bearing solder joints. For Sn-Ag-Cu solder joints, it was Sn and Cu to migrate during the ECM process. Zn was the only migration element in the SnZnBi solder joint. Sn-Zn-Bi solder exhibited the best ECM reliability.
采用水滴法研究了无铅焊点的电化学迁移。采用9种焊锡膏对ECM的敏感性进行比较。现场观察了外加电压、电极间距和焊剂残留量对电解加工的影响。检测了ECM过程中生长枝晶的微观结构和组成。结果表明，较高的电压和较窄的间距降低了焊点的ECM可靠性。残流抑制了ECM的发生。含铅焊点的主要迁移元素是Pb。对于Sn- ag -Cu焊点，在ECM过程中主要是Sn和Cu的迁移。Zn是SnZnBi焊点中唯一的迁移元素。Sn-Zn-Bi焊料表现出最好的ECM可靠性。
{"title":"In-situ observation on electrochemical migration of lead-free solder joints under water drop test","authors":"Y.H. Xia, W. Jillek, E. Schmitt","doi":"10.1109/ICEPT.2008.4607147","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607147","url":null,"abstract":"Electrochemical migration (ECM) of lead-free solder joints were investigated by water drop test method. Nine types solder pastes were employed to compare the ECM susceptible. The effects of applied voltage, electrodes spacing and flux residue on the ECM were in-situ observed. The microstructure and composition of the growing dendrites during ECM were detected. The results revealed that higher voltage and narrower spacing weakened the ECM reliability of solder joints. The flux residua inhibited the occurrence of ECM. The main migration element was Pb in Pb-bearing solder joints. For Sn-Ag-Cu solder joints, it was Sn and Cu to migrate during the ECM process. Zn was the only migration element in the SnZnBi solder joint. Sn-Zn-Bi solder exhibited the best ECM reliability.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74440295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：