Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606956
Po Xu, A. Hu, Zhuo Chen, Ming Li, D. Mao
In this paper, a novel low-temperature micro-insert bonding technology for 3D package has been reported. Nickel microcone arrays (MCA) fabricated on the bonding pad was used as the under bump metallization (UBM). The bonding temperature is below the melting point of the solder. At certain temperature and pressure, the MCA inserted into the lead-free Sn-Ag-Cu solder bumps to achieve a good adhesion. The bonding of the joint is realized by the mechanical interlocking and the diffusion between the MCA and the solder. The nickel microcone arrays were prepared by directional electrodeposition (DEP) method on the Cu substrates in the solution with inorganic additives. And then hundreds of bumps were bonded on the substrates at different temperatures (150deg-210degC) and different bonding pressure (450, 560, 750 gf/p). Subsequently, ball shear testings were performed to evaluate the mechanical reliability and failure mode of the solder joints. After the shear testings, the microstructures of the fracture interfaces were investigated by SEM.
{"title":"Novel low-temperature micro-insert bonding technology for 3D package","authors":"Po Xu, A. Hu, Zhuo Chen, Ming Li, D. Mao","doi":"10.1109/ICEPT.2008.4606956","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606956","url":null,"abstract":"In this paper, a novel low-temperature micro-insert bonding technology for 3D package has been reported. Nickel microcone arrays (MCA) fabricated on the bonding pad was used as the under bump metallization (UBM). The bonding temperature is below the melting point of the solder. At certain temperature and pressure, the MCA inserted into the lead-free Sn-Ag-Cu solder bumps to achieve a good adhesion. The bonding of the joint is realized by the mechanical interlocking and the diffusion between the MCA and the solder. The nickel microcone arrays were prepared by directional electrodeposition (DEP) method on the Cu substrates in the solution with inorganic additives. And then hundreds of bumps were bonded on the substrates at different temperatures (150deg-210degC) and different bonding pressure (450, 560, 750 gf/p). Subsequently, ball shear testings were performed to evaluate the mechanical reliability and failure mode of the solder joints. After the shear testings, the microstructures of the fracture interfaces were investigated by SEM.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"45 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91285981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607161
Q. Chen, Leon Xu, A. Salo, Gustavo Neto, Germano Freitas
Flexible display module reliability were investigated herein with experiments, such as bending, twisting and ball drop. The pretests of all the three experiments were carried out firstly to primarily understand the flexibility and mechanical behavior of the display. Based on the pretest results, the corresponding fatigue test setup method and process were put forward. Then, the fatigue tests were executed. At last, through the failure analysis, the flexibility and reliability of the flexible display in different use cases were evaluated. Suggestions about how to use the display and improve the reliability through change the design were given also.
{"title":"Reliability study of flexible display module by experiments","authors":"Q. Chen, Leon Xu, A. Salo, Gustavo Neto, Germano Freitas","doi":"10.1109/ICEPT.2008.4607161","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607161","url":null,"abstract":"Flexible display module reliability were investigated herein with experiments, such as bending, twisting and ball drop. The pretests of all the three experiments were carried out firstly to primarily understand the flexibility and mechanical behavior of the display. Based on the pretest results, the corresponding fatigue test setup method and process were put forward. Then, the fatigue tests were executed. At last, through the failure analysis, the flexibility and reliability of the flexible display in different use cases were evaluated. Suggestions about how to use the display and improve the reliability through change the design were given also.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"87 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73616625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607140
Chang-Lin Yeh, Y. Lai, Ching-Chun Wang
We derive in this paper equations of motion of board-level IC packages subjected to swept sine vibration loads following the support excitation scheme. Harmonic analysis is performed based on the argument such that at each loading state over the swept sine process, hysteresis responses of solder joints following the isotropic hardening rule vanish fairly quickly so that plasticity is fully developed. Computed and measured acceleration response spectra of a board-level test vehicle are benchmarked. Stress-based failure indices as well as elastoplastic responses and strain rates of solder joints are examined for the test vehicle subjected to swept sine vibration tests of different acceleration levels with vibration frequencies up to 2 kHz.
{"title":"Parametric study on board-level electronic test device subjected to JEDEC vibration loads","authors":"Chang-Lin Yeh, Y. Lai, Ching-Chun Wang","doi":"10.1109/ICEPT.2008.4607140","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607140","url":null,"abstract":"We derive in this paper equations of motion of board-level IC packages subjected to swept sine vibration loads following the support excitation scheme. Harmonic analysis is performed based on the argument such that at each loading state over the swept sine process, hysteresis responses of solder joints following the isotropic hardening rule vanish fairly quickly so that plasticity is fully developed. Computed and measured acceleration response spectra of a board-level test vehicle are benchmarked. Stress-based failure indices as well as elastoplastic responses and strain rates of solder joints are examined for the test vehicle subjected to swept sine vibration tests of different acceleration levels with vibration frequencies up to 2 kHz.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"6 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73153228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607159
Dongfang Cheng, Jue Zhang, Xiaohui Li, Jiongming Wang
Illustrated by the case of a lithium-ion battery protection IC, the paper focuses on the design of internal immunity to RFI. With analysis of the chippsilas three major elements of electromagnetic compatibility (EMC), the qualitative and quasi-quantitative analysis results of RFI influence to the chip are given out. By using a simple filter circuit and available material physical construction which can isolate, absorb and consume the RFI energy, the protection ICpsilas electromagnetic susceptibility has been reduced effectively. The simulation of the devised structure in the time domain is gained by Winspice, and tool IC_EMC makes it possible of the conversion from time domain to frequency domain in which the spectrum analysis is completed. The design has passed the simulation verification and the layout implement of the devised construction designed is also available.
{"title":"A design for increasing the immunity to RFI of protection IC of lithium-ion battery","authors":"Dongfang Cheng, Jue Zhang, Xiaohui Li, Jiongming Wang","doi":"10.1109/ICEPT.2008.4607159","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607159","url":null,"abstract":"Illustrated by the case of a lithium-ion battery protection IC, the paper focuses on the design of internal immunity to RFI. With analysis of the chippsilas three major elements of electromagnetic compatibility (EMC), the qualitative and quasi-quantitative analysis results of RFI influence to the chip are given out. By using a simple filter circuit and available material physical construction which can isolate, absorb and consume the RFI energy, the protection ICpsilas electromagnetic susceptibility has been reduced effectively. The simulation of the devised structure in the time domain is gained by Winspice, and tool IC_EMC makes it possible of the conversion from time domain to frequency domain in which the spectrum analysis is completed. The design has passed the simulation verification and the layout implement of the devised construction designed is also available.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"29 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74792269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607052
D. Shih, B. Dang, P. Gruber, M. Lu, S. Kang, S. Buchwalter, J. Knickerbocker, E. Perfecto, J. Garant, S. Knickerbocker, K. Semkow, B. Sundlof, J. Busby, R. Weisman, K. Ruhmer, E. Hughlett
Controlled collapse chip connection - new process (C4NP) technology is a novel solder bumping technology developed by IBM to address the limitations of existing bumping technologies. Through continuous improvements in processes, materials and defect control, C4NP technology has been successfully implemented at IBM in the manufacturing of all 300 mm Pb-free solder bumped wafers. Both 200 mum and 150 mum pitch products have been qualified and are currently ramping up volume production. Extendibility of C4NP to 50 mum ultra-fine pitch microbump application has been successfully demonstrated with the existing C4NP manufacturing tools. Targeted applications for microbumps are three-dimensional (3D) chip integration and the conversion of memory wafers from wirebonding (WB) to C4 bumping. The metrology data on solder volume, bump height, defect and yield have been characterized by RVSI inspection. This paper reviews the C4NP processes from mold manufacturing, solder fill and solder transfer onto 300 mm wafers, along with defect and yield analysis. Reliability challenges as well as solutions in the development and qualification of flip chip Pb-free solder joint are also reviewed. In addition to a suitable under bump metallurgy (UBM), a robust lead-free solder alloy with precisely controlled composition and special alloy doping is needed to enhance performance and reliability.
{"title":"C4NP for Pb-free solder wafer bumping and 3D fine-pitch applications","authors":"D. Shih, B. Dang, P. Gruber, M. Lu, S. Kang, S. Buchwalter, J. Knickerbocker, E. Perfecto, J. Garant, S. Knickerbocker, K. Semkow, B. Sundlof, J. Busby, R. Weisman, K. Ruhmer, E. Hughlett","doi":"10.1109/ICEPT.2008.4607052","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607052","url":null,"abstract":"Controlled collapse chip connection - new process (C4NP) technology is a novel solder bumping technology developed by IBM to address the limitations of existing bumping technologies. Through continuous improvements in processes, materials and defect control, C4NP technology has been successfully implemented at IBM in the manufacturing of all 300 mm Pb-free solder bumped wafers. Both 200 mum and 150 mum pitch products have been qualified and are currently ramping up volume production. Extendibility of C4NP to 50 mum ultra-fine pitch microbump application has been successfully demonstrated with the existing C4NP manufacturing tools. Targeted applications for microbumps are three-dimensional (3D) chip integration and the conversion of memory wafers from wirebonding (WB) to C4 bumping. The metrology data on solder volume, bump height, defect and yield have been characterized by RVSI inspection. This paper reviews the C4NP processes from mold manufacturing, solder fill and solder transfer onto 300 mm wafers, along with defect and yield analysis. Reliability challenges as well as solutions in the development and qualification of flip chip Pb-free solder joint are also reviewed. In addition to a suitable under bump metallurgy (UBM), a robust lead-free solder alloy with precisely controlled composition and special alloy doping is needed to enhance performance and reliability.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"39 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77096089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606950
B. Xie, P. Sun, D. Shi
The needs to integrate devices into portable products with smaller form factor and more functionality have fueled enormous growth of 3D packaging technology. The package-on-package (PoP) is one of the 3D packaging solutions, by which the packaging and assembly houses can achieve a lower cost, faster turn benefits and testing prior to assembly. PoP is a complicated system with multi-layered structure, which induces more manufacturability issues, such as stand-off height issue and top & bottom packages having different types of warpage. In order to reduce R&D cost, achieve fast time-to-market and address most of the manufacturability issues during the development of a new PoP, a design advisor for PoP manufacturing has been developed based on the design for manufacturability (DFM) methodology. The key components of this design advisor are the validated numerical models, comprehensive materials library, design guidelines of PoP packaging and novel finite element analysis (FEA) techniques. With the developed novel FEA techniques for curing process simulation and seamless packaging process simulation, complete numerical models for PoP manufacturing were developed and validated, which can simulate the whole PoP manufacturing processes. The design advisor is easy to use by selecting package geometries, material properties and process parameters. By running the envelope-based design advisor for normal package design or the FEA-based design advisor for special package design, the detailed analysis reports can be generated, including simulation results, design evaluations and recommendations to ensure the first-time success of package design. Therefore, the design advisor can help improve the yield of complex PoP manufacturing processes leading to higher quality and confidence of manufacturing processes, faster time-to-market and lower overall manufacturing cost.
{"title":"Design advisor for package-on-package (PoP) manufacturing","authors":"B. Xie, P. Sun, D. Shi","doi":"10.1109/ICEPT.2008.4606950","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606950","url":null,"abstract":"The needs to integrate devices into portable products with smaller form factor and more functionality have fueled enormous growth of 3D packaging technology. The package-on-package (PoP) is one of the 3D packaging solutions, by which the packaging and assembly houses can achieve a lower cost, faster turn benefits and testing prior to assembly. PoP is a complicated system with multi-layered structure, which induces more manufacturability issues, such as stand-off height issue and top & bottom packages having different types of warpage. In order to reduce R&D cost, achieve fast time-to-market and address most of the manufacturability issues during the development of a new PoP, a design advisor for PoP manufacturing has been developed based on the design for manufacturability (DFM) methodology. The key components of this design advisor are the validated numerical models, comprehensive materials library, design guidelines of PoP packaging and novel finite element analysis (FEA) techniques. With the developed novel FEA techniques for curing process simulation and seamless packaging process simulation, complete numerical models for PoP manufacturing were developed and validated, which can simulate the whole PoP manufacturing processes. The design advisor is easy to use by selecting package geometries, material properties and process parameters. By running the envelope-based design advisor for normal package design or the FEA-based design advisor for special package design, the detailed analysis reports can be generated, including simulation results, design evaluations and recommendations to ensure the first-time success of package design. Therefore, the design advisor can help improve the yield of complex PoP manufacturing processes leading to higher quality and confidence of manufacturing processes, faster time-to-market and lower overall manufacturing cost.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"30 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76828155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606993
Jun Tang, Hong Wang, Rui Liu, Shengping Mao, Xiaolin Zhao, G. Ding
Through-mask electroplating has been widely used in the fabrication of chips, BGA substrates and PCBs etc. The uniformity of plating thin-film is the major factor contributed to the reliability of the products. Currently, it is usually by setting optimum plating parameters and adopting electrochemical method to achieve the uniformity of plating. However, the problem of non-uniform distribution of electric field, which is the major cause of the non-uniformity of the plating thin-film, has not been solved. In this paper, finite element method (FEM) was developed to analyze the non-uniform distribution of electric field under different conditions in the process of electroplating. The results show that different thickness of photo-resist and size of electroplating cell are two major factors contribute to the uniformity of plating thin-film. The uniform of electroplating cell can be improved by adding in-chip auxiliary electrode. Also better uniformity of the plating film in radial direction can achieved by setting a shield in the proper position of the plating solution and annular out-chip auxiliary electrode (Cu) around the wafer. The simulation results were consistent with experimental results, which proved that finite element method is an effect way to simulate the electroplating process.
{"title":"Study on non-uniformity of Through-Mask electroplated Ni thin-film","authors":"Jun Tang, Hong Wang, Rui Liu, Shengping Mao, Xiaolin Zhao, G. Ding","doi":"10.1109/ICEPT.2008.4606993","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606993","url":null,"abstract":"Through-mask electroplating has been widely used in the fabrication of chips, BGA substrates and PCBs etc. The uniformity of plating thin-film is the major factor contributed to the reliability of the products. Currently, it is usually by setting optimum plating parameters and adopting electrochemical method to achieve the uniformity of plating. However, the problem of non-uniform distribution of electric field, which is the major cause of the non-uniformity of the plating thin-film, has not been solved. In this paper, finite element method (FEM) was developed to analyze the non-uniform distribution of electric field under different conditions in the process of electroplating. The results show that different thickness of photo-resist and size of electroplating cell are two major factors contribute to the uniformity of plating thin-film. The uniform of electroplating cell can be improved by adding in-chip auxiliary electrode. Also better uniformity of the plating film in radial direction can achieved by setting a shield in the proper position of the plating solution and annular out-chip auxiliary electrode (Cu) around the wafer. The simulation results were consistent with experimental results, which proved that finite element method is an effect way to simulate the electroplating process.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"162 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78071201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607048
Yanping He, D. Ding, Xiang Gao, Z. Chen, Ming Li, D. Mao
Co-Ni alloys have the properties of high hardness, good wear and corrosion resistance. A transition layer of Co-Ni coating will help enhance the hydrogen sensing stability of Pd films. In this work, Pd films were electrodeposited on Co-Ni coated copper substrate and silicon wafers. The influence of deposition parameters on the microstructure of Co-Ni coatings and Pd films were investigated. Experimental results indicated that scallop shell-like Co-Ni alloys could be fabricated on copper wafers. The tendency to form the shell-like deposits increased with increase of deposition time. While on silicon wafers, scallop shell-like Co-Ni alloys could not be fabricated. SEM and AFM analyses indicated that both composite films have a large surface area. Results showed that Pd films could be shaped by the prime films and thus maintain a large surface area.
{"title":"Electrodeposition of palladium films on Ni-Co coatings","authors":"Yanping He, D. Ding, Xiang Gao, Z. Chen, Ming Li, D. Mao","doi":"10.1109/ICEPT.2008.4607048","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607048","url":null,"abstract":"Co-Ni alloys have the properties of high hardness, good wear and corrosion resistance. A transition layer of Co-Ni coating will help enhance the hydrogen sensing stability of Pd films. In this work, Pd films were electrodeposited on Co-Ni coated copper substrate and silicon wafers. The influence of deposition parameters on the microstructure of Co-Ni coatings and Pd films were investigated. Experimental results indicated that scallop shell-like Co-Ni alloys could be fabricated on copper wafers. The tendency to form the shell-like deposits increased with increase of deposition time. While on silicon wafers, scallop shell-like Co-Ni alloys could not be fabricated. SEM and AFM analyses indicated that both composite films have a large surface area. Results showed that Pd films could be shaped by the prime films and thus maintain a large surface area.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"47 4 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76518262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606938
A. Lee, Louie Huang, M. Hung
The package on package (POP) stacking is getting more and more popular for system in package (SIP) applications. But during the assembly process, the POP had encountered the challenge of packages stacking yield loss, especially when top package and bottom package stacking. The key factors are the mount height of top package, the mold cap of bottom package, and the metallized ball land on the top surface of bottom package. JEDEC JC-11 has defined the rules of two packages stacking. However, the fine pitch package stacking application will meet the process capability limitation, including thinner mold cap, wafer thinning and the lowest wire bond loop height challenges. The POP used the top gate mold chase for the bottom package to expose the metallized ball land on the top side of package which is a dedicated molding tooling. Also, some process are used for solving yield loss issues such as a POP with interposer between top package and bottom package, or a bottom package with pre-mounted the solder ball on chip side ready for top package to attach. Those are customized tooling and not a prevailing tooling that increases the developing cost and timing. To resolve the stacking process yield loss issue, a MAPPOP solution had been revealed for eliminating the limitation between the top and bottom package stacking. The assembly process of mold array package (MAP) for fine pitch BGA has been implemented for MAPPOP applications. In the paper, the package design rules, and assembly process of exposed metallized ball land on the top surface of bottom package had been discussed. Finally the warpage performance and the packaging level reliability had also been discussed and analyzed.
{"title":"Mold array package for POP applications","authors":"A. Lee, Louie Huang, M. Hung","doi":"10.1109/ICEPT.2008.4606938","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606938","url":null,"abstract":"The package on package (POP) stacking is getting more and more popular for system in package (SIP) applications. But during the assembly process, the POP had encountered the challenge of packages stacking yield loss, especially when top package and bottom package stacking. The key factors are the mount height of top package, the mold cap of bottom package, and the metallized ball land on the top surface of bottom package. JEDEC JC-11 has defined the rules of two packages stacking. However, the fine pitch package stacking application will meet the process capability limitation, including thinner mold cap, wafer thinning and the lowest wire bond loop height challenges. The POP used the top gate mold chase for the bottom package to expose the metallized ball land on the top side of package which is a dedicated molding tooling. Also, some process are used for solving yield loss issues such as a POP with interposer between top package and bottom package, or a bottom package with pre-mounted the solder ball on chip side ready for top package to attach. Those are customized tooling and not a prevailing tooling that increases the developing cost and timing. To resolve the stacking process yield loss issue, a MAPPOP solution had been revealed for eliminating the limitation between the top and bottom package stacking. The assembly process of mold array package (MAP) for fine pitch BGA has been implemented for MAPPOP applications. In the paper, the package design rules, and assembly process of exposed metallized ball land on the top surface of bottom package had been discussed. Finally the warpage performance and the packaging level reliability had also been discussed and analyzed.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"50 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75741070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606957
Tao Feng, Jian Cai, Hye-Kyong Kwon, Qian Wang, Xinyu Dou
Wafer level packaging (WLP) technology has been used to integrate high-Q inductor on Si substrate. These inductors consist of a thick Cu electroplated rerouting to reduce series resistance and a thick dielectric layer to separate the inductors from Si substrate. The measured results show that the peak O-factor is 30 at 4 GHz for a 0.77 nH inductor, which is good agreement with the simulated performance by HFSS. Therefore, this technology realizes embedded high-Q inductors in WLP and can improve the performance of RF system.
{"title":"High-Q on-chip inductors embedded in wafer-level package for RFIC applications","authors":"Tao Feng, Jian Cai, Hye-Kyong Kwon, Qian Wang, Xinyu Dou","doi":"10.1109/ICEPT.2008.4606957","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606957","url":null,"abstract":"Wafer level packaging (WLP) technology has been used to integrate high-Q inductor on Si substrate. These inductors consist of a thick Cu electroplated rerouting to reduce series resistance and a thick dielectric layer to separate the inductors from Si substrate. The measured results show that the peak O-factor is 30 at 4 GHz for a 0.77 nH inductor, which is good agreement with the simulated performance by HFSS. Therefore, this technology realizes embedded high-Q inductors in WLP and can improve the performance of RF system.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"16 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88267408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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