Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606956
Po Xu, A. Hu, Zhuo Chen, Ming Li, D. Mao
In this paper, a novel low-temperature micro-insert bonding technology for 3D package has been reported. Nickel microcone arrays (MCA) fabricated on the bonding pad was used as the under bump metallization (UBM). The bonding temperature is below the melting point of the solder. At certain temperature and pressure, the MCA inserted into the lead-free Sn-Ag-Cu solder bumps to achieve a good adhesion. The bonding of the joint is realized by the mechanical interlocking and the diffusion between the MCA and the solder. The nickel microcone arrays were prepared by directional electrodeposition (DEP) method on the Cu substrates in the solution with inorganic additives. And then hundreds of bumps were bonded on the substrates at different temperatures (150deg-210degC) and different bonding pressure (450, 560, 750 gf/p). Subsequently, ball shear testings were performed to evaluate the mechanical reliability and failure mode of the solder joints. After the shear testings, the microstructures of the fracture interfaces were investigated by SEM.
{"title":"Novel low-temperature micro-insert bonding technology for 3D package","authors":"Po Xu, A. Hu, Zhuo Chen, Ming Li, D. Mao","doi":"10.1109/ICEPT.2008.4606956","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606956","url":null,"abstract":"In this paper, a novel low-temperature micro-insert bonding technology for 3D package has been reported. Nickel microcone arrays (MCA) fabricated on the bonding pad was used as the under bump metallization (UBM). The bonding temperature is below the melting point of the solder. At certain temperature and pressure, the MCA inserted into the lead-free Sn-Ag-Cu solder bumps to achieve a good adhesion. The bonding of the joint is realized by the mechanical interlocking and the diffusion between the MCA and the solder. The nickel microcone arrays were prepared by directional electrodeposition (DEP) method on the Cu substrates in the solution with inorganic additives. And then hundreds of bumps were bonded on the substrates at different temperatures (150deg-210degC) and different bonding pressure (450, 560, 750 gf/p). Subsequently, ball shear testings were performed to evaluate the mechanical reliability and failure mode of the solder joints. After the shear testings, the microstructures of the fracture interfaces were investigated by SEM.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91285981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607076
Yanhong Tian, Chunqing Wang, Shihua Yang, P. Lin, Le Liang
To meet the urgent demands of future electronic packages, the solder joints have to become increasingly miniaturized. Compared to the large solder joints, mechanics behavior for the samll solder joints is very different, resulting in a series of reliability issues. Therefore, it is very important to understand the mechanics behavior of the small solder joints. In this paper, the shear test of the as-reflowed and aged Sn-3.0Ag-0.5Cu solder joints on Cu pads with the diameters of 200 mum to 600 mum were conducted, and fracture behavior was observed using SEM. The results show that shear strength of the solder joint increases with the decreasing of the solder joints volumes. For the large volume solder joints, the fracture occurs close to the interface, and the solder joint shows strong brittleness. Whereas, for the small solder joints, the fracture occurs within the bulk solder, and the solder joint shows ductile property. The Ag3Sn and Cu6Sn5 intermetallic compounds (IMCs) at the interface region have a prominent effect on the shear property and the propagation of the fracture.
{"title":"Shear fracture behavior of Sn3.0Ag0.5Cu solder joints on Cu pads with different solder volumes","authors":"Yanhong Tian, Chunqing Wang, Shihua Yang, P. Lin, Le Liang","doi":"10.1109/ICEPT.2008.4607076","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607076","url":null,"abstract":"To meet the urgent demands of future electronic packages, the solder joints have to become increasingly miniaturized. Compared to the large solder joints, mechanics behavior for the samll solder joints is very different, resulting in a series of reliability issues. Therefore, it is very important to understand the mechanics behavior of the small solder joints. In this paper, the shear test of the as-reflowed and aged Sn-3.0Ag-0.5Cu solder joints on Cu pads with the diameters of 200 mum to 600 mum were conducted, and fracture behavior was observed using SEM. The results show that shear strength of the solder joint increases with the decreasing of the solder joints volumes. For the large volume solder joints, the fracture occurs close to the interface, and the solder joint shows strong brittleness. Whereas, for the small solder joints, the fracture occurs within the bulk solder, and the solder joint shows ductile property. The Ag3Sn and Cu6Sn5 intermetallic compounds (IMCs) at the interface region have a prominent effect on the shear property and the propagation of the fracture.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90801915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607003
Jia Yuxi, Li Jiao, Ran Feng, Dian Yang
In this paper, a lot of CMOS devices with different device dimensions, spacings, and clearances have been drawn and fabricated to find the optimized layout rules for electrostatic discharge (ESD) protection in 0.13 um Silicide CMOS Technology. The dependences of layout parameters on ESD protection ability of GGNMOS are investigated by using the TLP (transmission line pulsing) measurement technique. A DC model for modeling ESD NMOS snapback characteristics is also presented in this paper.
{"title":"Layout optimization and modeling of an ESD-protection n-MOSFET in 0.13um silicide CMOS technology","authors":"Jia Yuxi, Li Jiao, Ran Feng, Dian Yang","doi":"10.1109/ICEPT.2008.4607003","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607003","url":null,"abstract":"In this paper, a lot of CMOS devices with different device dimensions, spacings, and clearances have been drawn and fabricated to find the optimized layout rules for electrostatic discharge (ESD) protection in 0.13 um Silicide CMOS Technology. The dependences of layout parameters on ESD protection ability of GGNMOS are investigated by using the TLP (transmission line pulsing) measurement technique. A DC model for modeling ESD NMOS snapback characteristics is also presented in this paper.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87272517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606957
Tao Feng, Jian Cai, Hye-Kyong Kwon, Qian Wang, Xinyu Dou
Wafer level packaging (WLP) technology has been used to integrate high-Q inductor on Si substrate. These inductors consist of a thick Cu electroplated rerouting to reduce series resistance and a thick dielectric layer to separate the inductors from Si substrate. The measured results show that the peak O-factor is 30 at 4 GHz for a 0.77 nH inductor, which is good agreement with the simulated performance by HFSS. Therefore, this technology realizes embedded high-Q inductors in WLP and can improve the performance of RF system.
{"title":"High-Q on-chip inductors embedded in wafer-level package for RFIC applications","authors":"Tao Feng, Jian Cai, Hye-Kyong Kwon, Qian Wang, Xinyu Dou","doi":"10.1109/ICEPT.2008.4606957","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606957","url":null,"abstract":"Wafer level packaging (WLP) technology has been used to integrate high-Q inductor on Si substrate. These inductors consist of a thick Cu electroplated rerouting to reduce series resistance and a thick dielectric layer to separate the inductors from Si substrate. The measured results show that the peak O-factor is 30 at 4 GHz for a 0.77 nH inductor, which is good agreement with the simulated performance by HFSS. Therefore, this technology realizes embedded high-Q inductors in WLP and can improve the performance of RF system.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88267408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607139
Chang-Lin Yeh, Y. Lai
In this paper, numerical studies are carried out on high-speed cold ball pull test by using explicit transient finite element simulations to predict transient response of package-level solder ball subjected to pull loads. The material constitutions of solder alloys are obtained from quasi-static tensile test and Hopkinsonpsilas bar test. Erosion technique is adopted for simulations of bulk solder fracturing, and interfacial element for intermetalic compound (IMC) fracturing. Parameter studies on pull velocity effect as well as strain-rate effect are also carried out. Transition points of pull velocity between bulk solder fracturing mode and IMC fracturing mode are identified therefore. From simulation results, transform relationship between pull forces to joint adhesion strengths of solder joints can be set up.
{"title":"Strain-rate and impact velocity effects on joint adhesion strength","authors":"Chang-Lin Yeh, Y. Lai","doi":"10.1109/ICEPT.2008.4607139","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607139","url":null,"abstract":"In this paper, numerical studies are carried out on high-speed cold ball pull test by using explicit transient finite element simulations to predict transient response of package-level solder ball subjected to pull loads. The material constitutions of solder alloys are obtained from quasi-static tensile test and Hopkinsonpsilas bar test. Erosion technique is adopted for simulations of bulk solder fracturing, and interfacial element for intermetalic compound (IMC) fracturing. Parameter studies on pull velocity effect as well as strain-rate effect are also carried out. Transition points of pull velocity between bulk solder fracturing mode and IMC fracturing mode are identified therefore. From simulation results, transform relationship between pull forces to joint adhesion strengths of solder joints can be set up.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85510147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607050
Zhenqing Zhao, Lei Wang, Xiaoqiang Xie, Qian Wang, Jaisung Lee
In this paper, the behavior of BGA solder joints microstructures was studied as a function of Ni doping in SAC solder. Three kinds of solder compositions were selected including Sn3.0Ag0.5Cu, Sn1.0Ag0.5Cu and Sn1.0Ag0.5Cu0.02Ni to value the influence the effect of Ni doping, OSP and Au/Ni pad was employed on the PCB side. Emphasis was placed on studying the effect of low level doping with Ni on the joint microstructure and subsequent reliability. Both solder composition and PCB surface finish had a notable effect on the interfacial microstructure, the Ni addition can give rise to needle like NiCuSn IMC formation and reduce the grain size locally at solder/NiAu pad interface after one time reflow according to top-view interface analysis, and had no obvious effect on the IMC evolution of solder/OSP pad, the phenomena was investigated from the perspective of metallurgy. Bending and drop tests were conducted to evaluate the effect of solder composition and pad finish on the joint reliability. It was found that the decrease of Ag concentration and Ni addition in SAC solder could significantly improve the drop test performance when NiAu pad was used. In bending test, OSP pad show better performance than Au/Ni pad. The correlation between joint microstructure and joint reliability was discussed in detail. The work can give some directions on the solder alloy design and choice of pad finish in electronic packaging.
{"title":"The influence of low level doping of Ni on the microstructure and reliability of SAC solder joint","authors":"Zhenqing Zhao, Lei Wang, Xiaoqiang Xie, Qian Wang, Jaisung Lee","doi":"10.1109/ICEPT.2008.4607050","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607050","url":null,"abstract":"In this paper, the behavior of BGA solder joints microstructures was studied as a function of Ni doping in SAC solder. Three kinds of solder compositions were selected including Sn3.0Ag0.5Cu, Sn1.0Ag0.5Cu and Sn1.0Ag0.5Cu0.02Ni to value the influence the effect of Ni doping, OSP and Au/Ni pad was employed on the PCB side. Emphasis was placed on studying the effect of low level doping with Ni on the joint microstructure and subsequent reliability. Both solder composition and PCB surface finish had a notable effect on the interfacial microstructure, the Ni addition can give rise to needle like NiCuSn IMC formation and reduce the grain size locally at solder/NiAu pad interface after one time reflow according to top-view interface analysis, and had no obvious effect on the IMC evolution of solder/OSP pad, the phenomena was investigated from the perspective of metallurgy. Bending and drop tests were conducted to evaluate the effect of solder composition and pad finish on the joint reliability. It was found that the decrease of Ag concentration and Ni addition in SAC solder could significantly improve the drop test performance when NiAu pad was used. In bending test, OSP pad show better performance than Au/Ni pad. The correlation between joint microstructure and joint reliability was discussed in detail. The work can give some directions on the solder alloy design and choice of pad finish in electronic packaging.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84773175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607048
Yanping He, D. Ding, Xiang Gao, Z. Chen, Ming Li, D. Mao
Co-Ni alloys have the properties of high hardness, good wear and corrosion resistance. A transition layer of Co-Ni coating will help enhance the hydrogen sensing stability of Pd films. In this work, Pd films were electrodeposited on Co-Ni coated copper substrate and silicon wafers. The influence of deposition parameters on the microstructure of Co-Ni coatings and Pd films were investigated. Experimental results indicated that scallop shell-like Co-Ni alloys could be fabricated on copper wafers. The tendency to form the shell-like deposits increased with increase of deposition time. While on silicon wafers, scallop shell-like Co-Ni alloys could not be fabricated. SEM and AFM analyses indicated that both composite films have a large surface area. Results showed that Pd films could be shaped by the prime films and thus maintain a large surface area.
{"title":"Electrodeposition of palladium films on Ni-Co coatings","authors":"Yanping He, D. Ding, Xiang Gao, Z. Chen, Ming Li, D. Mao","doi":"10.1109/ICEPT.2008.4607048","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607048","url":null,"abstract":"Co-Ni alloys have the properties of high hardness, good wear and corrosion resistance. A transition layer of Co-Ni coating will help enhance the hydrogen sensing stability of Pd films. In this work, Pd films were electrodeposited on Co-Ni coated copper substrate and silicon wafers. The influence of deposition parameters on the microstructure of Co-Ni coatings and Pd films were investigated. Experimental results indicated that scallop shell-like Co-Ni alloys could be fabricated on copper wafers. The tendency to form the shell-like deposits increased with increase of deposition time. While on silicon wafers, scallop shell-like Co-Ni alloys could not be fabricated. SEM and AFM analyses indicated that both composite films have a large surface area. Results showed that Pd films could be shaped by the prime films and thus maintain a large surface area.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76518262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607009
Hu Yue-li, Yan Ke
More and more analog and mixed-signal (AMS) blocks are integrated into SoC (system-on-chip) platform due to intense market competition. A mixed signal /mixed power SoC design, using Synopsys Libraries, based on Chartered 0.35 um Salicide 2P4M CMOS mixed signal process is introduced in this paper. The method of supply the core with different powers, isolated the digital part and the analog part and splitting the padring is also proposed. The physical layout design and its verification are implemented using Astro and Calibre.
随着市场竞争的加剧，越来越多的模拟和混合信号(AMS)模块被集成到片上系统(SoC)平台中。介绍了一种基于Chartered 0.35 um Salicide 2P4M CMOS混合信号工艺，利用Synopsys库实现的混合信号/混合功率SoC设计。提出了用不同功率供电、数字部分和模拟部分隔离以及分割衬垫的方法。利用Astro和Calibre实现了物理布局设计及其验证。
{"title":"A mixed- signal physical design and its verification","authors":"Hu Yue-li, Yan Ke","doi":"10.1109/ICEPT.2008.4607009","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607009","url":null,"abstract":"More and more analog and mixed-signal (AMS) blocks are integrated into SoC (system-on-chip) platform due to intense market competition. A mixed signal /mixed power SoC design, using Synopsys Libraries, based on Chartered 0.35 um Salicide 2P4M CMOS mixed signal process is introduced in this paper. The method of supply the core with different powers, isolated the digital part and the analog part and splitting the padring is also proposed. The physical layout design and its verification are implemented using Astro and Calibre.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79501275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606997
R. Guan, Dalei Tian, Xing Wang
LEDs have becoming the most suitable candidate replacing traditional fluorescent lamps because of its energy-efficient, the introduction of high brightness LEDs with white light and monochromatic colors have led to a movement towards general illumination. This revolutionizes the optoelectronics market, enabling engineers to use LEDs for general lighting applications as well as medical, indoor lighting and automotive solutions. So variable LED array modules were developed, they are making great strides in terms of lumen performance and reliability, however the barrier to widespread use in general illumination still remains the cost or luminous efficiency, special requirements concerning optical properties and optomechanical layout have to be met. In order to meet the requirements of indoor illumination, a LED daylight lamp model was designed, it can replace traditional fluorescent lamp without insteading additional power supply establishment. The optical properties of the model were simulated using optical analysis software, its luminous efficiency is about 41 lm/W, the illuminance is about 50 lux when the distance is 1.5 m between the center of the model and measured spot, With the theoretically-optimized design of the LED model, experiments based on the results of the optimal simulation in the laboratory were conducted to verify the performance of the proposed LED model, it reaches a power factor of about 0.8 at 11 W. Results of the simulation are very similar with the measured values, it was testified that simulative method is one of the effective tools for LED lighting optical design.
{"title":"Design and implementation of LED daylight lamp lighting system","authors":"R. Guan, Dalei Tian, Xing Wang","doi":"10.1109/ICEPT.2008.4606997","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606997","url":null,"abstract":"LEDs have becoming the most suitable candidate replacing traditional fluorescent lamps because of its energy-efficient, the introduction of high brightness LEDs with white light and monochromatic colors have led to a movement towards general illumination. This revolutionizes the optoelectronics market, enabling engineers to use LEDs for general lighting applications as well as medical, indoor lighting and automotive solutions. So variable LED array modules were developed, they are making great strides in terms of lumen performance and reliability, however the barrier to widespread use in general illumination still remains the cost or luminous efficiency, special requirements concerning optical properties and optomechanical layout have to be met. In order to meet the requirements of indoor illumination, a LED daylight lamp model was designed, it can replace traditional fluorescent lamp without insteading additional power supply establishment. The optical properties of the model were simulated using optical analysis software, its luminous efficiency is about 41 lm/W, the illuminance is about 50 lux when the distance is 1.5 m between the center of the model and measured spot, With the theoretically-optimized design of the LED model, experiments based on the results of the optimal simulation in the laboratory were conducted to verify the performance of the proposed LED model, it reaches a power factor of about 0.8 at 11 W. Results of the simulation are very similar with the measured values, it was testified that simulative method is one of the effective tools for LED lighting optical design.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78595664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606993
Jun Tang, Hong Wang, Rui Liu, Shengping Mao, Xiaolin Zhao, G. Ding
Through-mask electroplating has been widely used in the fabrication of chips, BGA substrates and PCBs etc. The uniformity of plating thin-film is the major factor contributed to the reliability of the products. Currently, it is usually by setting optimum plating parameters and adopting electrochemical method to achieve the uniformity of plating. However, the problem of non-uniform distribution of electric field, which is the major cause of the non-uniformity of the plating thin-film, has not been solved. In this paper, finite element method (FEM) was developed to analyze the non-uniform distribution of electric field under different conditions in the process of electroplating. The results show that different thickness of photo-resist and size of electroplating cell are two major factors contribute to the uniformity of plating thin-film. The uniform of electroplating cell can be improved by adding in-chip auxiliary electrode. Also better uniformity of the plating film in radial direction can achieved by setting a shield in the proper position of the plating solution and annular out-chip auxiliary electrode (Cu) around the wafer. The simulation results were consistent with experimental results, which proved that finite element method is an effect way to simulate the electroplating process.
{"title":"Study on non-uniformity of Through-Mask electroplated Ni thin-film","authors":"Jun Tang, Hong Wang, Rui Liu, Shengping Mao, Xiaolin Zhao, G. Ding","doi":"10.1109/ICEPT.2008.4606993","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606993","url":null,"abstract":"Through-mask electroplating has been widely used in the fabrication of chips, BGA substrates and PCBs etc. The uniformity of plating thin-film is the major factor contributed to the reliability of the products. Currently, it is usually by setting optimum plating parameters and adopting electrochemical method to achieve the uniformity of plating. However, the problem of non-uniform distribution of electric field, which is the major cause of the non-uniformity of the plating thin-film, has not been solved. In this paper, finite element method (FEM) was developed to analyze the non-uniform distribution of electric field under different conditions in the process of electroplating. The results show that different thickness of photo-resist and size of electroplating cell are two major factors contribute to the uniformity of plating thin-film. The uniform of electroplating cell can be improved by adding in-chip auxiliary electrode. Also better uniformity of the plating film in radial direction can achieved by setting a shield in the proper position of the plating solution and annular out-chip auxiliary electrode (Cu) around the wafer. The simulation results were consistent with experimental results, which proved that finite element method is an effect way to simulate the electroplating process.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78071201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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