Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606961
K. Pan, Daoguo Yang, Qiao Kai, Kouchi Zhang, L. Yang
In order to promote the professional education and meet the requirements for the well-qualified technicians of the microelectronics industry , the higher education division of the education ministry and Intel (China) jointly initiated and setup a new mode of higher professional education faculty training:ldquo2008 Microelectronics Manufacturing Engineering Faculty Training Camprdquo, of which the ldquoIntel-GUET Microelectronics Packaging & Assembly Technology Faculty Training Camprdquo was organized and implemented by Guilin University of Electronic Technology (GUET). The program includes three parts: basic theories and experiments, one weekpsilas industry visit & investigation, and one weekpsilas education reform discussion & forum. In this paper, the initiatives, curriculum structure, and hands-on training, etc. were presented. The activities and the achievements of this joint faculty training are summarized.
{"title":"Introduction of Microelectronics Manufacturing Engineering into professional education: a joint effort among industry, government and universities","authors":"K. Pan, Daoguo Yang, Qiao Kai, Kouchi Zhang, L. Yang","doi":"10.1109/ICEPT.2008.4606961","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606961","url":null,"abstract":"In order to promote the professional education and meet the requirements for the well-qualified technicians of the microelectronics industry , the higher education division of the education ministry and Intel (China) jointly initiated and setup a new mode of higher professional education faculty training:ldquo2008 Microelectronics Manufacturing Engineering Faculty Training Camprdquo, of which the ldquoIntel-GUET Microelectronics Packaging & Assembly Technology Faculty Training Camprdquo was organized and implemented by Guilin University of Electronic Technology (GUET). The program includes three parts: basic theories and experiments, one weekpsilas industry visit & investigation, and one weekpsilas education reform discussion & forum. In this paper, the initiatives, curriculum structure, and hands-on training, etc. were presented. The activities and the achievements of this joint faculty training are summarized.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"23 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91537533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607062
Xiao-Wei Tian, Zhenguo Yang, Jiang-yan Sun, Zheng Ji
O-cresol novolac epoxy resins are used widely as electronic encapsulating materials. When the pitch wires in electronic systems are more slender, there are pressing demands for high purity o-cresol novolac epoxy resin which are with little content of hydrolyzable chloride. In this paper, o-cresol novolac resin was synthesized from para-formaldehyde and o-cresol in the presence of a mixed catalyst (oxalic acid and another co-catalyst). Then, the resultant resin was further reacted with epichlorohydrin to prepare o-cresol novolac epoxy resin. The performances and structure of o-cresol novolac resin and o-cresol novolac epoxy resin were characterized by epoxy equivalent weight, softening point, the content of hydrolyzable chloride and inorganic chlorine, FTIR, 13CNMR. And the relationships between the performances and the reaction conditions were also studied. The results indicate that, o-cresol novolac epoxy resins were synthesized with certain performances through the adjustment of the reaction conditions, which were suited for the pressing demands for high purity applications.
{"title":"Synthesis of high purity o-cresol novolac epoxy resins","authors":"Xiao-Wei Tian, Zhenguo Yang, Jiang-yan Sun, Zheng Ji","doi":"10.1109/ICEPT.2008.4607062","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607062","url":null,"abstract":"O-cresol novolac epoxy resins are used widely as electronic encapsulating materials. When the pitch wires in electronic systems are more slender, there are pressing demands for high purity o-cresol novolac epoxy resin which are with little content of hydrolyzable chloride. In this paper, o-cresol novolac resin was synthesized from para-formaldehyde and o-cresol in the presence of a mixed catalyst (oxalic acid and another co-catalyst). Then, the resultant resin was further reacted with epichlorohydrin to prepare o-cresol novolac epoxy resin. The performances and structure of o-cresol novolac resin and o-cresol novolac epoxy resin were characterized by epoxy equivalent weight, softening point, the content of hydrolyzable chloride and inorganic chlorine, FTIR, 13CNMR. And the relationships between the performances and the reaction conditions were also studied. The results indicate that, o-cresol novolac epoxy resins were synthesized with certain performances through the adjustment of the reaction conditions, which were suited for the pressing demands for high purity applications.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"122 ","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91462628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607092
Li Liu, Yinggang Shi, Qinghua Jiao, Yanan Wu, Zhikun Zhang, J. Liu
In this paper, we select electrospinning technique to fabricate polysulfonamide nanofibers. Polysulfonamide with relatively high inherent viscosity was prepared based on 4,4'-diaminodiphenylsulfone and terephthaloyl chloride in the common solvent N,N-Dimethylacetamide (DMAc) by the method of low-temperature solution condensation polymerization. Our research work focused on studying the effect of concentration of solution, processing parameters including voltage and distance from tip to collector on the spinnability of the solution and morphology electrospun polysulfonamid fibers. The microstructures of the electrospun polysulfonamid fibers were quantitively investigated by scanning electron microscope (SEM) as a function of processing variables.
{"title":"Preparation of polysulfoneamide electrospinning nanofibers","authors":"Li Liu, Yinggang Shi, Qinghua Jiao, Yanan Wu, Zhikun Zhang, J. Liu","doi":"10.1109/ICEPT.2008.4607092","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607092","url":null,"abstract":"In this paper, we select electrospinning technique to fabricate polysulfonamide nanofibers. Polysulfonamide with relatively high inherent viscosity was prepared based on 4,4'-diaminodiphenylsulfone and terephthaloyl chloride in the common solvent N,N-Dimethylacetamide (DMAc) by the method of low-temperature solution condensation polymerization. Our research work focused on studying the effect of concentration of solution, processing parameters including voltage and distance from tip to collector on the spinnability of the solution and morphology electrospun polysulfonamid fibers. The microstructures of the electrospun polysulfonamid fibers were quantitively investigated by scanning electron microscope (SEM) as a function of processing variables.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"7 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91113716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607059
Yanhua Fan, Shuhui Yu, R. Sun, Lei Li, Mian Huang, Yan-sheng Yin, L. Wan
Ba0.7Sr0.3TiO3 thin films have been deposited on copper foils via sol-gel method. The films have been processed in almost inert atmosphere so that the substrate oxidation is avoided while allowing the perovskite phase to crystallize. Polyethylene glycol (PEG) with the molecular weight of 200 was employed to modify the BST precursor solutions. The effect of PEG on the microstructure and dielectric properties of BST thin films has been investigated. Leakage current for BST thin film made from the sol with PEG modification is reported.
{"title":"Microstructure and properties of barium strontium titanate thin films prepared on copper foils via addition of PEG to the sol precursor","authors":"Yanhua Fan, Shuhui Yu, R. Sun, Lei Li, Mian Huang, Yan-sheng Yin, L. Wan","doi":"10.1109/ICEPT.2008.4607059","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607059","url":null,"abstract":"Ba0.7Sr0.3TiO3 thin films have been deposited on copper foils via sol-gel method. The films have been processed in almost inert atmosphere so that the substrate oxidation is avoided while allowing the perovskite phase to crystallize. Polyethylene glycol (PEG) with the molecular weight of 200 was employed to modify the BST precursor solutions. The effect of PEG on the microstructure and dielectric properties of BST thin films has been investigated. Leakage current for BST thin film made from the sol with PEG modification is reported.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"19 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82371795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606959
Xiong-hui Cai, B. An, Yi-Ping Wu, Feng-shun Wu, Xiao-wei Lai
In this work, ACA was prepared by mixing micro-sized spherical Ag particles and latent curing agent into thermo-set epoxy resin, and RFID flip chips were assembled on the Al/PET, printed Ag/PET and printed Ag/paper antennae through hot-press bonding process. The contact resistance and shear bonding strength before and after the reliability tests (hot humidity test, 85degC, RH 85%), and degradation mechanism of ACA interconnection for flip-chip-on-flex (FCOF) assembly were studied using modified RFIC and the three kinds of antennae mentioned above. It was found that the contact resistance changed after the reliability test, it was caused by the total results of oxidation of Al/PET antennae and conductive particles, mismatch of coefficient of thermal expansion (CTE) between the ACA adhesive, antennae and flip-chips and post curing of resin. And the bonding strength also affect by the further curing of paste, strain release accumulated in resin and the microstructure change caused by moisture absorption during the reliability test. It was concluded that it was benefit to improve the reliability of FCOF assembly packaged by ACA by introducing the post curing process. And it was suggested that selecting the anti-oxidation conductor and the anti-heat substrate of antennae could decrease the shift of contact resistance, which was especially favored for ultra-high frequency RFID tag. Therefore, the printed Ag/paper antenna was preferred to large scale, cheap and rapid manufacturing RFID tags.
{"title":"Research on the contact resistance and reliability of flexible RFID tag inlays packaged by anisotropic conductive paste","authors":"Xiong-hui Cai, B. An, Yi-Ping Wu, Feng-shun Wu, Xiao-wei Lai","doi":"10.1109/ICEPT.2008.4606959","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606959","url":null,"abstract":"In this work, ACA was prepared by mixing micro-sized spherical Ag particles and latent curing agent into thermo-set epoxy resin, and RFID flip chips were assembled on the Al/PET, printed Ag/PET and printed Ag/paper antennae through hot-press bonding process. The contact resistance and shear bonding strength before and after the reliability tests (hot humidity test, 85degC, RH 85%), and degradation mechanism of ACA interconnection for flip-chip-on-flex (FCOF) assembly were studied using modified RFIC and the three kinds of antennae mentioned above. It was found that the contact resistance changed after the reliability test, it was caused by the total results of oxidation of Al/PET antennae and conductive particles, mismatch of coefficient of thermal expansion (CTE) between the ACA adhesive, antennae and flip-chips and post curing of resin. And the bonding strength also affect by the further curing of paste, strain release accumulated in resin and the microstructure change caused by moisture absorption during the reliability test. It was concluded that it was benefit to improve the reliability of FCOF assembly packaged by ACA by introducing the post curing process. And it was suggested that selecting the anti-oxidation conductor and the anti-heat substrate of antennae could decrease the shift of contact resistance, which was especially favored for ultra-high frequency RFID tag. Therefore, the printed Ag/paper antenna was preferred to large scale, cheap and rapid manufacturing RFID tags.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"97 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81324849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606977
Jun Li, L. Wan, Wei Gao, C. Liao
With the voltage decreasing in power distribution network (PDN) in system-on-packages (SOPs), power integrity will be a critical issue. The cavity resonance modes between power and ground planes can be excited by simultaneous switching noise (SSN) or ground bounce noise (GBN) [1], [2]. To cut down the noise from susceptible devices, isolation techniques are necessary. In this paper, two novel structures combine segmented method and embedded capacitor provided isolation performances from 0.7 GHz to 10 GHz below -40 dB. The novel structures with a bridge for suppressing noise in high frequency and a thin high K dielectric substrate for decreasing the SSN in the entire frequency band. And they were better in performance and simpler in configuration than Electromagnetic Band Gap (EBG) and other isolation structures. Moreover, the analytical process could be a guidance to find better structures for improving the noise isolation.
{"title":"Improvement of power integrity with novel segmented power bus structures in RF/digital SOP","authors":"Jun Li, L. Wan, Wei Gao, C. Liao","doi":"10.1109/ICEPT.2008.4606977","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606977","url":null,"abstract":"With the voltage decreasing in power distribution network (PDN) in system-on-packages (SOPs), power integrity will be a critical issue. The cavity resonance modes between power and ground planes can be excited by simultaneous switching noise (SSN) or ground bounce noise (GBN) [1], [2]. To cut down the noise from susceptible devices, isolation techniques are necessary. In this paper, two novel structures combine segmented method and embedded capacitor provided isolation performances from 0.7 GHz to 10 GHz below -40 dB. The novel structures with a bridge for suppressing noise in high frequency and a thin high K dielectric substrate for decreasing the SSN in the entire frequency band. And they were better in performance and simpler in configuration than Electromagnetic Band Gap (EBG) and other isolation structures. Moreover, the analytical process could be a guidance to find better structures for improving the noise isolation.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81339534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607015
Shi Hui, Ran Feng, Zhang Jinyi
This paper presents a combinational test generation method for transition faults in acyclic sequential circuits. In this method, to generate test sequences for transition faults in a given acyclic sequential circuit is performed on its extend time-expansion model. The model is composed of two copies of time-expansion model of the given circuit and extends in the close two sequences to generate 2 vectors for the transition faults with some restrictions. Experimental results show the method can achieve the higher fault efficiency with the lower test generation times than conventional method.
{"title":"Combinational test generation for transition faults in acyclic sequential circuits","authors":"Shi Hui, Ran Feng, Zhang Jinyi","doi":"10.1109/ICEPT.2008.4607015","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607015","url":null,"abstract":"This paper presents a combinational test generation method for transition faults in acyclic sequential circuits. In this method, to generate test sequences for transition faults in a given acyclic sequential circuit is performed on its extend time-expansion model. The model is composed of two copies of time-expansion model of the given circuit and extends in the close two sequences to generate 2 vectors for the transition faults with some restrictions. Experimental results show the method can achieve the higher fault efficiency with the lower test generation times than conventional method.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"103 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87147647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606962
R. Dudek, E. Kaulfersch, S. Rzepka, M. Rollig, B. Michel
Recent studies revealed that there is no simple ldquodrop inrdquo solution for the lead-free replacement of SnPb joints, instead different Sn-based solders are advantageous for different use conditions, which can be dominated either by drop loading or by thermal cyclic loading in harsh use conditions. By way of high-speed shear testing reliability assessments of components during drop and shock events can be studied in a simplified manner. Dynamic 3-D finite element simulations have been performed applying explicit FEA to replicate the shear tests virtually. It was shown in this way that SAC 1305 solder outperformed SAC 387 solder. The low cycle fatigue behavior of different SAC alloys is additionally of interest. Fatigue life predictions require both the constitutive description of the lead-free solders and a fatigue hypothesis linked to the material selected. Based on recently measured creep properties the solder joint creep strain and creep dissipation responses were analyzed for several components and thermal cycling conditions. The results based upon non-linear finite element calculations indicate different trends for creep strain and energy dissipation: while the first is clearly increasing with lowered alloying Ag-content, the latter is almost stable and does only slightly vary. Furthermore, these trends are different for different test- and field cycling conditions as well as the different components studied.
{"title":"FEA based reliability prediction for different Sn-based solders subjected to fast shear and fatigue loadings","authors":"R. Dudek, E. Kaulfersch, S. Rzepka, M. Rollig, B. Michel","doi":"10.1109/ICEPT.2008.4606962","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606962","url":null,"abstract":"Recent studies revealed that there is no simple ldquodrop inrdquo solution for the lead-free replacement of SnPb joints, instead different Sn-based solders are advantageous for different use conditions, which can be dominated either by drop loading or by thermal cyclic loading in harsh use conditions. By way of high-speed shear testing reliability assessments of components during drop and shock events can be studied in a simplified manner. Dynamic 3-D finite element simulations have been performed applying explicit FEA to replicate the shear tests virtually. It was shown in this way that SAC 1305 solder outperformed SAC 387 solder. The low cycle fatigue behavior of different SAC alloys is additionally of interest. Fatigue life predictions require both the constitutive description of the lead-free solders and a fatigue hypothesis linked to the material selected. Based on recently measured creep properties the solder joint creep strain and creep dissipation responses were analyzed for several components and thermal cycling conditions. The results based upon non-linear finite element calculations indicate different trends for creep strain and energy dissipation: while the first is clearly increasing with lowered alloying Ag-content, the latter is almost stable and does only slightly vary. Furthermore, these trends are different for different test- and field cycling conditions as well as the different components studied.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"2 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87187614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606935
M. Yew, Chun-Fai Yu, M. Tsai, D. Hu, Wen-Kung Yang, K. Chiang
A new panel base package (PBP) technology that was developed based on the concepts of the wafer level package (WLP) has been proposed in order to obtain the signal fan-out capability for the fine-pitched integrated circuit (IC). In the PBP, the chip is attached to a selected chip carrier, and the volume of IC devices is extended for the redistribution of the original die pads. In this study, the thermal performance of the PBP technology was investigated and discussed through three-dimensional finite element (FE) analysis. In order to compare the thermal performance between conventional WLP and the proposed PBP, the junction temperature of WLP was also recorded through the modified FE model. The results showed that due to the larger packaging size of the PBP structure, the added solder bumps can be used as thermal balls. Moreover, they can effectively reduce the packaging thermal resistance (from 55degC/W to 41degC/W). It is expected that thermal performance could be further improved by applying solder paste between the chip and chip carrier. The study likewise discussed the condition of forced convection and developed the PBP technology for high-density IC devices. In light of the results obtained from this study, we believe in our new PBB technologypsilas great potential for future applications.
{"title":"A study of thermal performance for the panel base package (PBP™) technology","authors":"M. Yew, Chun-Fai Yu, M. Tsai, D. Hu, Wen-Kung Yang, K. Chiang","doi":"10.1109/ICEPT.2008.4606935","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606935","url":null,"abstract":"A new panel base package (PBP) technology that was developed based on the concepts of the wafer level package (WLP) has been proposed in order to obtain the signal fan-out capability for the fine-pitched integrated circuit (IC). In the PBP, the chip is attached to a selected chip carrier, and the volume of IC devices is extended for the redistribution of the original die pads. In this study, the thermal performance of the PBP technology was investigated and discussed through three-dimensional finite element (FE) analysis. In order to compare the thermal performance between conventional WLP and the proposed PBP, the junction temperature of WLP was also recorded through the modified FE model. The results showed that due to the larger packaging size of the PBP structure, the added solder bumps can be used as thermal balls. Moreover, they can effectively reduce the packaging thermal resistance (from 55degC/W to 41degC/W). It is expected that thermal performance could be further improved by applying solder paste between the chip and chip carrier. The study likewise discussed the condition of forced convection and developed the PBP technology for high-density IC devices. In light of the results obtained from this study, we believe in our new PBB technologypsilas great potential for future applications.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"51 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87591303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606953
Jin Ling, H. Jun, Han Li
The reliability of multi-dice in package was studied in this paper; DPA tests were operated on qualified devices to distribute early failure from overstress failure. Then factorial experiments manipulated on early failure samples for failure analysis. Comparing the C-SAM images before and after a series reliability tests, the reliability of SiP devices was confirmed.
{"title":"DPA tests on SiP device","authors":"Jin Ling, H. Jun, Han Li","doi":"10.1109/ICEPT.2008.4606953","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606953","url":null,"abstract":"The reliability of multi-dice in package was studied in this paper; DPA tests were operated on qualified devices to distribute early failure from overstress failure. Then factorial experiments manipulated on early failure samples for failure analysis. Comparing the C-SAM images before and after a series reliability tests, the reliability of SiP devices was confirmed.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"22 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80511118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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