Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607137
C. Regard, C. Gautier, H. Frémont, P. Poirier
To increase miniaturization, CSWLP (chip size wafer level packaging) has been developed. However, the difficulty to get good solder joint reliability leads to manufacture only small CSWLP modules. Different underfill methods are evaluated here, by measurements and simulations: results prove that underfill is necessary, but a bad choice can also decrease the reliability. An original method called ldquore-enforcementrdquo improves the life time.
{"title":"Influence of underfill methods on the solder joint fatigue of wafer level packaging","authors":"C. Regard, C. Gautier, H. Frémont, P. Poirier","doi":"10.1109/ICEPT.2008.4607137","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607137","url":null,"abstract":"To increase miniaturization, CSWLP (chip size wafer level packaging) has been developed. However, the difficulty to get good solder joint reliability leads to manufacture only small CSWLP modules. Different underfill methods are evaluated here, by measurements and simulations: results prove that underfill is necessary, but a bad choice can also decrease the reliability. An original method called ldquore-enforcementrdquo improves the life time.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72796419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606941
Baoxia Li, L. Wan, Chengyue Yang, Wei Gao, Y. Lv, Zhihua Li, Xu Zhang
A compact 4times2-channel parallel optical MCM transceiver with data rates up to 3.125 Gb/s per channel was studied for very short reach (VSR) interconnection. The transceiver was based on 1times4 VCSEL and PD arrays of 850 nm wavelength, and a 12-fiber-ribbon as the transmission medium. Greatly relaxed alignment tolerance and high coupling efficiency between optoelectronic (OE) device arrays and fiber arrays were achieved. The eye-diagram at 2.5 Gb/s was measured under 231-1 pseudorandom bit stream (PRBS).
{"title":"Low-cost high-efficiency 4 channel pluggable parallel optical transceiver using optoelectronic MCM packaging technologies","authors":"Baoxia Li, L. Wan, Chengyue Yang, Wei Gao, Y. Lv, Zhihua Li, Xu Zhang","doi":"10.1109/ICEPT.2008.4606941","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606941","url":null,"abstract":"A compact 4times2-channel parallel optical MCM transceiver with data rates up to 3.125 Gb/s per channel was studied for very short reach (VSR) interconnection. The transceiver was based on 1times4 VCSEL and PD arrays of 850 nm wavelength, and a 12-fiber-ribbon as the transmission medium. Greatly relaxed alignment tolerance and high coupling efficiency between optoelectronic (OE) device arrays and fiber arrays were achieved. The eye-diagram at 2.5 Gb/s was measured under 231-1 pseudorandom bit stream (PRBS).","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74595485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607157
Na Liu, Xiaoyan Li, Yongchang Yan
It is well known, reliability and workability are the more important issues in the field of chip size package (CSP). Creep and fatigue behaviors are the main loads of the solder joints, the reliability of which should take account of those two main loads. Based on the theory of continuum damage mechanics (CDM), this paper focuses on damage evolution of interaction between the fatigue and creep. A new damage model of fatigue-creep interaction has been developed. And the new fatigue-creep interaction damage model in this paper does not require the simple fatigue model and simple creep model.
{"title":"Investigation on fatigue-creep interaction damage model for solder","authors":"Na Liu, Xiaoyan Li, Yongchang Yan","doi":"10.1109/ICEPT.2008.4607157","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607157","url":null,"abstract":"It is well known, reliability and workability are the more important issues in the field of chip size package (CSP). Creep and fatigue behaviors are the main loads of the solder joints, the reliability of which should take account of those two main loads. Based on the theory of continuum damage mechanics (CDM), this paper focuses on damage evolution of interaction between the fatigue and creep. A new damage model of fatigue-creep interaction has been developed. And the new fatigue-creep interaction damage model in this paper does not require the simple fatigue model and simple creep model.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74152300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607079
Rui Liu, Hong Wang, Xueping Li, Jun Tang, Shengping Mao, G. Ding
Uniaxial tensile test is the most reliable way to measure mechanical properties of thin films. The difficulties of uniaxial tensile test are how to fabricate small and stress-free specimen, align and trip the specimen, generate small forces and measure strain. A novel tensile testing chip to measure thin film specimens with large elongation was proposed in this paper, and it was fabricated by UV-LIGA (Ultraviolet Lithographie GalVanoformung Abformung) technology. This novel testing chip has good alignment and can endure large deformation.
{"title":"Design of testing chip for measuring mechanical properties of thin films","authors":"Rui Liu, Hong Wang, Xueping Li, Jun Tang, Shengping Mao, G. Ding","doi":"10.1109/ICEPT.2008.4607079","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607079","url":null,"abstract":"Uniaxial tensile test is the most reliable way to measure mechanical properties of thin films. The difficulties of uniaxial tensile test are how to fabricate small and stress-free specimen, align and trip the specimen, generate small forces and measure strain. A novel tensile testing chip to measure thin film specimens with large elongation was proposed in this paper, and it was fabricated by UV-LIGA (Ultraviolet Lithographie GalVanoformung Abformung) technology. This novel testing chip has good alignment and can endure large deformation.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79340110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606968
An Tong, Q. Fei
A beam model of board level electronic package was used to investigate effects of the moment, axial force and shear force induced during drop/impact on the peeling stress of the soldered joints. The peeling stresses in soldered joints were evaluated under static and dynamic bending of the PCB. It shows that the peeling stress is dominated by the bending stress and the maximum occurs at the PCB end. In the soldered joint array, only a few soldered joints closed to the far end of the packaging are stressed and the most joints inside the array are almost stress free. Based on this observation, an approach was proposed to reduce the computation scale. By the approach, only 3 or 4 soldered joints are necessary to be included in the computational model.
{"title":"A scale reduced computation scheme for peeling stress of solder joints under drop impact","authors":"An Tong, Q. Fei","doi":"10.1109/ICEPT.2008.4606968","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606968","url":null,"abstract":"A beam model of board level electronic package was used to investigate effects of the moment, axial force and shear force induced during drop/impact on the peeling stress of the soldered joints. The peeling stresses in soldered joints were evaluated under static and dynamic bending of the PCB. It shows that the peeling stress is dominated by the bending stress and the maximum occurs at the PCB end. In the soldered joint array, only a few soldered joints closed to the far end of the packaging are stressed and the most joints inside the array are almost stress free. Based on this observation, an approach was proposed to reduce the computation scale. By the approach, only 3 or 4 soldered joints are necessary to be included in the computational model.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84310324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606945
Q. Qi
For devices with challenging power management requirement, thermally enhanced ball grid array package (TEBGA) offers a good solution, where the device is attached to a heat spreader, usually made of copper, with a thermally conductive epoxy to ensure a good conductive path for heat to escape from the die. The top die surface and bonding wires are covered with an overmolding compound for environmental protection such that heat dissipation is typically limited in that direction. However, TEBGA is not without its unique challenges. In this paper, we present a study on the challenges of meeting the thermal performance and reliability requirements for a ASIC packaged with TEBGA. A localized deformation or ldquodimplerdquo of the TEBGA package is discovered during the package assembly process, where the heat-spreader is noted to have deformed under the die shadow, which results in a circular shaped indentation. This raises concerns about the impact on the thermal performance of the subsequent package to heat sink interface when it is integrated into the system. Solution to this potential problem rests on balancing thermal performance, reducing package stress level & understanding potential long term package reliability. Deformation of the package with each process step will be first described and particular attention will be given to the change of package profile after the die attach process; then a finite element analysis of the stress and deformation of the die attach process is discussed and important parameters affecting the deformation and stress are shown; moreover, a thermal resistance model assessing the thermal budget for this package in a system environment is reviewed and confirmation with numerical analysis & validation by experimental analysis are highlighted; furthermore, an interactive analysis is subsequently performed based on the FEA model for package stress/deformation and thermal resistance model to optimize the packaging solution; finally, balanced solution through this interactive optimization process is summarized and demonstrated in the manufacturing process.
{"title":"Meeting thermal performance and reliability challenges for a thermally enhanced ball grid array package (TEBGA)","authors":"Q. Qi","doi":"10.1109/ICEPT.2008.4606945","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606945","url":null,"abstract":"For devices with challenging power management requirement, thermally enhanced ball grid array package (TEBGA) offers a good solution, where the device is attached to a heat spreader, usually made of copper, with a thermally conductive epoxy to ensure a good conductive path for heat to escape from the die. The top die surface and bonding wires are covered with an overmolding compound for environmental protection such that heat dissipation is typically limited in that direction. However, TEBGA is not without its unique challenges. In this paper, we present a study on the challenges of meeting the thermal performance and reliability requirements for a ASIC packaged with TEBGA. A localized deformation or ldquodimplerdquo of the TEBGA package is discovered during the package assembly process, where the heat-spreader is noted to have deformed under the die shadow, which results in a circular shaped indentation. This raises concerns about the impact on the thermal performance of the subsequent package to heat sink interface when it is integrated into the system. Solution to this potential problem rests on balancing thermal performance, reducing package stress level & understanding potential long term package reliability. Deformation of the package with each process step will be first described and particular attention will be given to the change of package profile after the die attach process; then a finite element analysis of the stress and deformation of the die attach process is discussed and important parameters affecting the deformation and stress are shown; moreover, a thermal resistance model assessing the thermal budget for this package in a system environment is reviewed and confirmation with numerical analysis & validation by experimental analysis are highlighted; furthermore, an interactive analysis is subsequently performed based on the FEA model for package stress/deformation and thermal resistance model to optimize the packaging solution; finally, balanced solution through this interactive optimization process is summarized and demonstrated in the manufacturing process.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84883343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606989
H. Fan, C. Wong, M. Yuen
Interfacial delamination, due to the presence of dissimilar material systems, is one of the primary concerns in electronic package design. The mismatch in coefficient of thermal expansion between the different layers in the packages can generate high interfacial stresses due to thermal loading during fabrication and assembly. More and more functional materials at the nano scale are, such as self-assembly monolayer (SAM) and CNT, used in electronic packaging for the improvement of the interfacial performance, traditional continuum model without considering these nano materials are obviously not suitable to study performance of electronic packages. In this study, a multi-scale model was built to investigate interfacial failure between EMC and SAM coated copper substrate. The interfacial material behavior was derived from the molecular dynamics simulation. The constitutive relation for the EMC-SAM-Cu interface under tensile load was derived from MD simulation. Tapered double cantilever beam tests (TDCB) were conducted on the laminated specimens to quantify the load during delamination propagation along the EMC-Cu interface with SAM and without SAM. Finite element models of the DCB test were built using ANSYS with interfacial element at the Cu-EMC interface. The constitutive relations from MD simulations in the form of a traction-displacement plot were introduced into the cohesive zone model to study the constitutive response of the EMC-Cu interface under the tensile loading, which is traversed across the length scale from nanoscale to macroscale. and assigned to the continuum model. The critical loading forces for the EMC/Cu interface with SAM and without SAM were obtained from the multi-scale model. It was found that interfacial strength between EMC and Cu substrate could be improved by SAM. Based on the proposed method, the predicted results were found to be comparable with those from experimental measurement.
{"title":"A multi-scale interfacial delamination model of Cu-SAM-epoxy systems","authors":"H. Fan, C. Wong, M. Yuen","doi":"10.1109/ICEPT.2008.4606989","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606989","url":null,"abstract":"Interfacial delamination, due to the presence of dissimilar material systems, is one of the primary concerns in electronic package design. The mismatch in coefficient of thermal expansion between the different layers in the packages can generate high interfacial stresses due to thermal loading during fabrication and assembly. More and more functional materials at the nano scale are, such as self-assembly monolayer (SAM) and CNT, used in electronic packaging for the improvement of the interfacial performance, traditional continuum model without considering these nano materials are obviously not suitable to study performance of electronic packages. In this study, a multi-scale model was built to investigate interfacial failure between EMC and SAM coated copper substrate. The interfacial material behavior was derived from the molecular dynamics simulation. The constitutive relation for the EMC-SAM-Cu interface under tensile load was derived from MD simulation. Tapered double cantilever beam tests (TDCB) were conducted on the laminated specimens to quantify the load during delamination propagation along the EMC-Cu interface with SAM and without SAM. Finite element models of the DCB test were built using ANSYS with interfacial element at the Cu-EMC interface. The constitutive relations from MD simulations in the form of a traction-displacement plot were introduced into the cohesive zone model to study the constitutive response of the EMC-Cu interface under the tensile loading, which is traversed across the length scale from nanoscale to macroscale. and assigned to the continuum model. The critical loading forces for the EMC/Cu interface with SAM and without SAM were obtained from the multi-scale model. It was found that interfacial strength between EMC and Cu substrate could be improved by SAM. Based on the proposed method, the predicted results were found to be comparable with those from experimental measurement.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84080729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607056
Shihua Yang, Chunqing Wang, Yanhong Tian, P. Lin, Le Liang
As-reflowed Sn-Ag-Cu solder joints in various diameters were found to contain only several beta-Sn crystal grains. With the solder joints increasingly miniaturized, there is no obvious change in the grain number in a solder joint. The aged Sn-Ag-Cu solder joints are composed of very limited number of beta-Sn crystal grains as well. It appears that the solder joint size and thermal aging have less influence on the growth of beta-Sn grains.
{"title":"Limited β-Sn grain number of miniaturized Sn-Ag-Cu solder joints","authors":"Shihua Yang, Chunqing Wang, Yanhong Tian, P. Lin, Le Liang","doi":"10.1109/ICEPT.2008.4607056","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607056","url":null,"abstract":"As-reflowed Sn-Ag-Cu solder joints in various diameters were found to contain only several beta-Sn crystal grains. With the solder joints increasingly miniaturized, there is no obvious change in the grain number in a solder joint. The aged Sn-Ag-Cu solder joints are composed of very limited number of beta-Sn crystal grains as well. It appears that the solder joint size and thermal aging have less influence on the growth of beta-Sn grains.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80269651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606994
Ning Ye-xiang, Pan Kai-lin, L. Ni
In this paper, the backward compatibility solder joints were chosen in simulation of perimeter PBGA272 assembly. A double-symmetric plane FE model of a PBGA272 was established using the software ANSYS. Based on the maximum von Mises stress and von Mises strain, the position of the most danger solder joints were obtained under thermal cycle with the temperature condition from -40degC to 125degC (JESD22-A104-B Condition G) , Viz. the inner (1#) solder joint and the outside (6#) solder joint are the two key solder joints which are the easiest to failure. On the basis of above analysis, the geometry parameters of the chosen assembly are optimized by design of experiment (DOE). The factors included PCB size, PCB thickness, chip size, chip thickness, substrate size, substrate thickness, solder height and solder radius. The simulating results have shown that substrate thickness (factor F), solder radius (factor H) and solder height (factor G) performed the main factors. The optimal scheme is F3H2G1C2D1E2B3A2 (substrate thickness 0.7 mm, solder radius 0.38 mm, solder height 0.4 mm, chip size 2.54 mm, chip thickness 0.4 mm, substrate size 13.5 mm, PCB thickness 1.8 mm and PCB size 15 mm) by comprehensively considered with every factorpsilas effect.
本文选择后向兼容焊点进行了周长PBGA272组装仿真。利用ANSYS软件建立了PBGA272的双对称平面有限元模型。根据最大von Mises应力和von Mises应变，在温度为-40℃~ 125℃(JESD22-A104-B条件G)的热循环条件下，得到了最危险焊点的位置，即内(1#)焊点和外(6#)焊点是最容易失效的两个关键焊点。在此基础上，通过实验设计对所选组件的几何参数进行了优化。影响因素包括PCB尺寸、PCB厚度、芯片尺寸、芯片厚度、衬底尺寸、衬底厚度、焊点高度和焊点半径。仿真结果表明，衬底厚度(F因子)、焊料半径(H因子)和焊料高度(G因子)是影响焊接性能的主要因素。综合考虑各因素的影响，最佳方案为F3H2G1C2D1E2B3A2(衬底厚度0.7 mm，焊料半径0.38 mm，焊料高度0.4 mm，芯片尺寸2.54 mm，芯片厚度0.4 mm，衬底尺寸13.5 mm, PCB板厚度1.8 mm, PCB板尺寸15 mm)。
{"title":"Simulation and analysis for backward compatibility of solder joints under thermal cycle","authors":"Ning Ye-xiang, Pan Kai-lin, L. Ni","doi":"10.1109/ICEPT.2008.4606994","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606994","url":null,"abstract":"In this paper, the backward compatibility solder joints were chosen in simulation of perimeter PBGA272 assembly. A double-symmetric plane FE model of a PBGA272 was established using the software ANSYS. Based on the maximum von Mises stress and von Mises strain, the position of the most danger solder joints were obtained under thermal cycle with the temperature condition from -40degC to 125degC (JESD22-A104-B Condition G) , Viz. the inner (1#) solder joint and the outside (6#) solder joint are the two key solder joints which are the easiest to failure. On the basis of above analysis, the geometry parameters of the chosen assembly are optimized by design of experiment (DOE). The factors included PCB size, PCB thickness, chip size, chip thickness, substrate size, substrate thickness, solder height and solder radius. The simulating results have shown that substrate thickness (factor F), solder radius (factor H) and solder height (factor G) performed the main factors. The optimal scheme is F3H2G1C2D1E2B3A2 (substrate thickness 0.7 mm, solder radius 0.38 mm, solder height 0.4 mm, chip size 2.54 mm, chip thickness 0.4 mm, substrate size 13.5 mm, PCB thickness 1.8 mm and PCB size 15 mm) by comprehensively considered with every factorpsilas effect.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80428207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607068
J. McElroy, R. Pfahl
In 2006 when the European Unionpsilas RoHS Regulation went into effect, a number of global firms who produce high-reliability products such as servers and telecommunication equipment had decided to take the exemption allowed for Pb containing solders in these applications. As a result they had not completed the tests necessary to prove the reliability of Tin Silver Copper (SAC) alloys in these applications. In 2007 it became apparent to many of these firms that they could no longer procure components with traditional SnPb surface finishes, and thus they faced an unknown reliability risk. In 2006 iNEMI had begun a study to evaluate the reliability of ldquoPb-Free BGAs in SnPb Assemblies.rdquo This paper will report on the results of this initial study and will then report on several studies currently under way to evaluate the reliability of new green-materials in high-reliability applications.
{"title":"Environmentally friendly electronics for high reliability","authors":"J. McElroy, R. Pfahl","doi":"10.1109/ICEPT.2008.4607068","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607068","url":null,"abstract":"In 2006 when the European Unionpsilas RoHS Regulation went into effect, a number of global firms who produce high-reliability products such as servers and telecommunication equipment had decided to take the exemption allowed for Pb containing solders in these applications. As a result they had not completed the tests necessary to prove the reliability of Tin Silver Copper (SAC) alloys in these applications. In 2007 it became apparent to many of these firms that they could no longer procure components with traditional SnPb surface finishes, and thus they faced an unknown reliability risk. In 2006 iNEMI had begun a study to evaluate the reliability of ldquoPb-Free BGAs in SnPb Assemblies.rdquo This paper will report on the results of this initial study and will then report on several studies currently under way to evaluate the reliability of new green-materials in high-reliability applications.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83051202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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