Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607051
A. Tseng, B. Lin, L. Huang, M. Hung
The object of this study is to develop a set of optimized assembly process parameters for BGA package using 45 nm ELK (extreme Low-K) and CUP (circuit under pad) wafer which is driven by high speed and high I/O requested. Due to chip size shrinkage with electrical performance improvement, most of 0.13 mum and 90 nm wafer process technology are moving toward 65 nm and even 45 nm now. The ELK dielectric material for Inter-Level Dielectric (ILD) with the CUP has been designed to get more space for active circuit layout. But the poor mechanical properties of the low-k dielectric and the CUP structure circuit pad design make packaging assembly more challenges. The impacts of IC packaging assembly processes are including the wafer sawing, wire bonding, and molding process. For mass production purpose, the most effective parameters for 45 nm ELK CUP wafer have been studied such as sawing blade type, sawing speed and sawing feeding rate for different wafer thickness, the wire bond time, bond power and bond force. To solve bond wire sweep and mold void issues, the properties of different molding compounds have been studied and assembly process parameters have been optimized. In the end, a real functional die of 45 nm ELK with CUP design has been assembled into package level for reliability test using optimized process parameters.
{"title":"BGA assembly process development for 45nm ELK CUP devices","authors":"A. Tseng, B. Lin, L. Huang, M. Hung","doi":"10.1109/ICEPT.2008.4607051","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607051","url":null,"abstract":"The object of this study is to develop a set of optimized assembly process parameters for BGA package using 45 nm ELK (extreme Low-K) and CUP (circuit under pad) wafer which is driven by high speed and high I/O requested. Due to chip size shrinkage with electrical performance improvement, most of 0.13 mum and 90 nm wafer process technology are moving toward 65 nm and even 45 nm now. The ELK dielectric material for Inter-Level Dielectric (ILD) with the CUP has been designed to get more space for active circuit layout. But the poor mechanical properties of the low-k dielectric and the CUP structure circuit pad design make packaging assembly more challenges. The impacts of IC packaging assembly processes are including the wafer sawing, wire bonding, and molding process. For mass production purpose, the most effective parameters for 45 nm ELK CUP wafer have been studied such as sawing blade type, sawing speed and sawing feeding rate for different wafer thickness, the wire bond time, bond power and bond force. To solve bond wire sweep and mold void issues, the properties of different molding compounds have been studied and assembly process parameters have been optimized. In the end, a real functional die of 45 nm ELK with CUP design has been assembled into package level for reliability test using optimized process parameters.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"1 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75827277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607032
D. Tian, Chunqing Wang, Yanhong Tian
A VOF model is developed to simulate the solder spreading and solidification during solder jet bumping process. This model is based on fixed mesh method, and accounts for the surface tension, wetting effects, and heat transfer with solidification. The visualizations of the transient impact processes are employed in order to compare and validate the numerical model presented. Results show the spreading and recoiling process coupled with the solidification leads to a final cone-shaped solder bump. The variation of gravitational potential energy in the impingement is too small to be neglected. The simulated results are in excellent agreement with the photographic images.
{"title":"Numerical simulation of solder spreading and solidification during solder jet bumping process","authors":"D. Tian, Chunqing Wang, Yanhong Tian","doi":"10.1109/ICEPT.2008.4607032","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607032","url":null,"abstract":"A VOF model is developed to simulate the solder spreading and solidification during solder jet bumping process. This model is based on fixed mesh method, and accounts for the surface tension, wetting effects, and heat transfer with solidification. The visualizations of the transient impact processes are employed in order to compare and validate the numerical model presented. Results show the spreading and recoiling process coupled with the solidification leads to a final cone-shaped solder bump. The variation of gravitational potential energy in the impingement is too small to be neglected. The simulated results are in excellent agreement with the photographic images.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"12 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91076341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606972
Yangjian Xia, Yuanxiang Zhang, L. Liang, Y. Liu, S. Irving, T. Luk
Moisture sensitivity of packages is an area of great concern for the electronics industry. The differential swelling of materials in a non-hermetic package during manufacture, handling, storage, assembly, and then also during its lifetime can cause stresses large enough to damage the package. A moisture automation analysis system is developed based on ANSYS Workbench and Excel platform in this paper. The goal of this paper is to develop an analysis system for moisture diffusion, hygro-mechanical stress and vapor pressure analysis automatically for different package family The application of moisture automation analysis system for moisture diffusion, vapor pressure diffusion, thermal-mechanical stress; hygro-mechanical stress; vapor equivalent thermal mismatch stress are performed. The comparisons of some results based on moisture automation analysis system with those from ANSYS are given. The results from this paper agree with those from pure ANSYS.
{"title":"Development of moisture automation analysis system for microelectronic packaging structures","authors":"Yangjian Xia, Yuanxiang Zhang, L. Liang, Y. Liu, S. Irving, T. Luk","doi":"10.1109/ICEPT.2008.4606972","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606972","url":null,"abstract":"Moisture sensitivity of packages is an area of great concern for the electronics industry. The differential swelling of materials in a non-hermetic package during manufacture, handling, storage, assembly, and then also during its lifetime can cause stresses large enough to damage the package. A moisture automation analysis system is developed based on ANSYS Workbench and Excel platform in this paper. The goal of this paper is to develop an analysis system for moisture diffusion, hygro-mechanical stress and vapor pressure analysis automatically for different package family The application of moisture automation analysis system for moisture diffusion, vapor pressure diffusion, thermal-mechanical stress; hygro-mechanical stress; vapor equivalent thermal mismatch stress are performed. The comparisons of some results based on moisture automation analysis system with those from ANSYS are given. The results from this paper agree with those from pure ANSYS.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"18 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89793175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606960
K. Pun, C. Q. Cui, T. Chung
In the trend of miniaturization, low cost, and the performance of electronics, high density interconnect has been required for interfacing with very fine pitch BGA, CSP and SIP. This raises a great challenge to the substrate technology and related interconnect technology in electronic packaging for high density, small feature size and high performance. Miniaturization in electronics means finer lines and smaller vias in substrate technology. Very fine lines on the substrate are difficult to produce by thicker copper layer in conventional CO2 laser blind via. In this paper, ultra-fine blind via with solid Cu filled at an entry diameter of 20 mum, over the current blind via size of 50-200 mum by CO2 laser drilling, is demonstrated on polyimide (PI) based flexible substrate. A via pitch at 30 mum for the blind via has been developed for next generation of stack die packaging accompanying with dimpless design, which ameliorates the void entrapment failure caused by soldering and direct flip-chip (FC) bonding, and strengthens interfacial bond strength. In the meantime, thinner Cu conductor at top and bottom side could be achieved for high circuit density. The reliability of the ultra-fine blind vias has been assessed in daisy chain modules at substrate level, subjected to JEDEC air-to-air thermal cycle and thermal shock, and low/high temperature storage tests. Applications in direct FC bonding and their virtues including high electrical and thermal performances, and feasible of various metals surface finishing, will be discussed. In the end, the ultra-fine Cu filled blind via technology has introduced to the production in Compass for SIP, stack die CSP, 2-metal layer chip-on-flex (COF) and multi-layer buildup flex, etc.
{"title":"Ultra-fine via pitch on flexible substrate for high density interconnect (HDI)","authors":"K. Pun, C. Q. Cui, T. Chung","doi":"10.1109/ICEPT.2008.4606960","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606960","url":null,"abstract":"In the trend of miniaturization, low cost, and the performance of electronics, high density interconnect has been required for interfacing with very fine pitch BGA, CSP and SIP. This raises a great challenge to the substrate technology and related interconnect technology in electronic packaging for high density, small feature size and high performance. Miniaturization in electronics means finer lines and smaller vias in substrate technology. Very fine lines on the substrate are difficult to produce by thicker copper layer in conventional CO2 laser blind via. In this paper, ultra-fine blind via with solid Cu filled at an entry diameter of 20 mum, over the current blind via size of 50-200 mum by CO2 laser drilling, is demonstrated on polyimide (PI) based flexible substrate. A via pitch at 30 mum for the blind via has been developed for next generation of stack die packaging accompanying with dimpless design, which ameliorates the void entrapment failure caused by soldering and direct flip-chip (FC) bonding, and strengthens interfacial bond strength. In the meantime, thinner Cu conductor at top and bottom side could be achieved for high circuit density. The reliability of the ultra-fine blind vias has been assessed in daisy chain modules at substrate level, subjected to JEDEC air-to-air thermal cycle and thermal shock, and low/high temperature storage tests. Applications in direct FC bonding and their virtues including high electrical and thermal performances, and feasible of various metals surface finishing, will be discussed. In the end, the ultra-fine Cu filled blind via technology has introduced to the production in Compass for SIP, stack die CSP, 2-metal layer chip-on-flex (COF) and multi-layer buildup flex, etc.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"1 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89189514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606975
Wei Gao, L. Wan, Jun Li
This paper presents a novel lowpass filter with an embedded capacitor which can substitute conventional filter network and suppress switching noise with a large bandwidth in Multi-GHz PCBs. A new design methodology of the low pass filter network is proposed. A new SPICE model of embedded capacitor based on transmission line theory is built and a comparison between H-spice and GTLE is used to illuminate its validity. With the model and finite elements method, the feature of the embedded capacitor, in which different frequency modes were excited by special exciting positions, was studied and the design procedure of an ECF was developed. As an application example, a typical power supply filter network and its replacement, an embedded capacitor with a 100 uF SMD capacitor, were studied.
{"title":"A lowpass filter with an embedded capacitor for wideband noise suppression in Multi-GHz PCBs","authors":"Wei Gao, L. Wan, Jun Li","doi":"10.1109/ICEPT.2008.4606975","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606975","url":null,"abstract":"This paper presents a novel lowpass filter with an embedded capacitor which can substitute conventional filter network and suppress switching noise with a large bandwidth in Multi-GHz PCBs. A new design methodology of the low pass filter network is proposed. A new SPICE model of embedded capacitor based on transmission line theory is built and a comparison between H-spice and GTLE is used to illuminate its validity. With the model and finite elements method, the feature of the embedded capacitor, in which different frequency modes were excited by special exciting positions, was studied and the design procedure of an ECF was developed. As an application example, a typical power supply filter network and its replacement, an embedded capacitor with a 100 uF SMD capacitor, were studied.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"24 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86518934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607115
X.F. Zhang, J.D. Guo, J. Shang
Electromigration in the Ni/SnZn/Cu solder interconnect was studied with an average current density of 4.1times104A/cm2 for 168.5h at 150degC. When the electrons flowed from the Ni side to the Cu side, uniform layers of Ni5Zn21 and Cu5Zn8 were formed at the Ni/SnZn and Cu/SnZn interfaces. The results are similar to those without passage of an electric current. However, upon reversing the current direction where electron flow was from the Cu side to the Ni side, thicker Cu6Sn5 phase replaced Ni5Zn21 phase at the Ni/SnZn interface, whereas at the Cu/SnZn interface, thicker beta-CuZn phase replaced Cu5Zn8 phase. Meanwhile, Cu-Sn phases also appeared at the Cu/SnZn interface. A kinetic model, based on the Zn and Cu mass transport in the sample, was presented to explain the growth of the intermetallic compound at the anode and cathode.
{"title":"Electromigration behavior of the Ni/SnZn/Cu solder interconnect","authors":"X.F. Zhang, J.D. Guo, J. Shang","doi":"10.1109/ICEPT.2008.4607115","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607115","url":null,"abstract":"Electromigration in the Ni/SnZn/Cu solder interconnect was studied with an average current density of 4.1times10<sup>4</sup>A/cm<sup>2</sup> for 168.5h at 150degC. When the electrons flowed from the Ni side to the Cu side, uniform layers of Ni<sub>5</sub>Zn<sub>21</sub> and Cu<sub>5</sub>Zn<sub>8</sub> were formed at the Ni/SnZn and Cu/SnZn interfaces. The results are similar to those without passage of an electric current. However, upon reversing the current direction where electron flow was from the Cu side to the Ni side, thicker Cu<sub>6</sub>Sn<sub>5</sub> phase replaced Ni<sub>5</sub>Zn<sub>21</sub> phase at the Ni/SnZn interface, whereas at the Cu/SnZn interface, thicker beta-CuZn phase replaced Cu<sub>5</sub>Zn<sub>8</sub> phase. Meanwhile, Cu-Sn phases also appeared at the Cu/SnZn interface. A kinetic model, based on the Zn and Cu mass transport in the sample, was presented to explain the growth of the intermetallic compound at the anode and cathode.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"06 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85852419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606991
S. Wu, Chi-Chang Lai, Hung-Hsiang Cheng, Yu-Che Tai, Chen-Chao Wang
Organic material using for packaging substrate is selected and multi-length microstrip lines in same trace width are designed and performed on it. Novel formulas deliver to extract dielectric constant and loss tangent varying with frequency for selected organic materials will be shown in this paper. Performances of microstrip lines are measured by Agilent vector network analyzer up to 20 GHz and SOLT calibration used to get two-port S-parameters. Then, novel formulas are used to extract material parameters in ADS software by measurement date.
{"title":"Frequency dielectric constant and loss tangent extracting of organic material using multi-length microstrip","authors":"S. Wu, Chi-Chang Lai, Hung-Hsiang Cheng, Yu-Che Tai, Chen-Chao Wang","doi":"10.1109/ICEPT.2008.4606991","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606991","url":null,"abstract":"Organic material using for packaging substrate is selected and multi-length microstrip lines in same trace width are designed and performed on it. Novel formulas deliver to extract dielectric constant and loss tangent varying with frequency for selected organic materials will be shown in this paper. Performances of microstrip lines are measured by Agilent vector network analyzer up to 20 GHz and SOLT calibration used to get two-port S-parameters. Then, novel formulas are used to extract material parameters in ADS software by measurement date.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"51 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88866470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607119
Jin Peng
The statistical process control (SPC) of destructive pull test on 1 Au gold wire is studied on two high-rel devices, namely #1 and #2. It was found that the Cpk of both parts are around 1.2, which have not meet our goal of 1.33 and the ultimately six sigma (Cpk= 2). However, this study shows that the traditional method of calculating Cpk has underestimated the capability of process control if considering the tolerance as asymmetric, such as the case for 1 mil gold wire bond.
{"title":"Capability study on the destructive pull test of 1 mil gold wire bond and its asymmetric distribution","authors":"Jin Peng","doi":"10.1109/ICEPT.2008.4607119","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607119","url":null,"abstract":"The statistical process control (SPC) of destructive pull test on 1 Au gold wire is studied on two high-rel devices, namely #1 and #2. It was found that the Cpk of both parts are around 1.2, which have not meet our goal of 1.33 and the ultimately six sigma (Cpk= 2). However, this study shows that the traditional method of calculating Cpk has underestimated the capability of process control if considering the tolerance as asymmetric, such as the case for 1 mil gold wire bond.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"17 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83618565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607020
Zhang Jinyi, Wang Jia, Lin Feng, Jia Yanhui, Zhou Kai
The paper presents a reverse SoC TAM design based dual-balanced strategy, which is on the basis of IEEE1500. Firstly test scheduling is executed according to the conceptual TAM architecture that is physically realizable, and then the real TAM architecture can be reversely established according to the test scheduling result. Since the test scheduling is not limited by TAM architecture, the test scheduling optimization can involve both top level and IP level and obtain the cross-level combined optimization between these two levels. The experimental results on the ITCpsila02 show the better availability and reliability and the performance improvement on test time of the proposed method, compared with several other representative approaches. Particularly, the method of this paper is based on the practical test cost, thus is of greatly practical value.
{"title":"Research on the characteristics theory of reverse SoC TAM design based on dual-balanced strategy","authors":"Zhang Jinyi, Wang Jia, Lin Feng, Jia Yanhui, Zhou Kai","doi":"10.1109/ICEPT.2008.4607020","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607020","url":null,"abstract":"The paper presents a reverse SoC TAM design based dual-balanced strategy, which is on the basis of IEEE1500. Firstly test scheduling is executed according to the conceptual TAM architecture that is physically realizable, and then the real TAM architecture can be reversely established according to the test scheduling result. Since the test scheduling is not limited by TAM architecture, the test scheduling optimization can involve both top level and IP level and obtain the cross-level combined optimization between these two levels. The experimental results on the ITCpsila02 show the better availability and reliability and the performance improvement on test time of the proposed method, compared with several other representative approaches. Particularly, the method of this paper is based on the practical test cost, thus is of greatly practical value.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"43 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86125451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606976
Xiaobing Luo, Weizhi Xiong, Sheng Liu
Light emitting diode (LED) street lamp heavily relies on successful thermal management, which strongly affects the optical extraction and the reliability/durability of the LED lamp. In this study, a thermal resistance network model was presented to estimate the maximum heat sink temperature of the street lamp, which could be utilized to further evaluate the thermal performance of the street lamp. Two high power LED street lamps, an 114 watts and an 80 watts LED street lamp were used to evaluate the present model. Their heat sink temperatures were calculated by the model, the results showed that the maximum heat sink temperature was about 61degC at the environment temperature of 25degC for the 114 watts LED street lamp. For the 80 watts LED street lamp, the maximum heat sink temperature was about 42.5degC at the environment temperature of 11degC. To prove the model feasibility, experimental investigations on the 114 watts and 80 watts LED street lamp were conducted. The results demonstrated that the heat sink temperature of the 114 watts LED street lamp remained to be stable at about 60degC after several hourspsila lighting at the room temperature of 25degC. The heat sink temperature of the 80 watts LED street lamp remained to be stable at about 42degC at the room temperature of 11degC. Comparing the results achieved by the thermal resistance model with the experimental results, it was found that the proposed thermal resistance model could be used for temperature estimation and thermal evaluation for the high power street lamp.
{"title":"A simplified thermal resistance network model for high power LED street lamp","authors":"Xiaobing Luo, Weizhi Xiong, Sheng Liu","doi":"10.1109/ICEPT.2008.4606976","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606976","url":null,"abstract":"Light emitting diode (LED) street lamp heavily relies on successful thermal management, which strongly affects the optical extraction and the reliability/durability of the LED lamp. In this study, a thermal resistance network model was presented to estimate the maximum heat sink temperature of the street lamp, which could be utilized to further evaluate the thermal performance of the street lamp. Two high power LED street lamps, an 114 watts and an 80 watts LED street lamp were used to evaluate the present model. Their heat sink temperatures were calculated by the model, the results showed that the maximum heat sink temperature was about 61degC at the environment temperature of 25degC for the 114 watts LED street lamp. For the 80 watts LED street lamp, the maximum heat sink temperature was about 42.5degC at the environment temperature of 11degC. To prove the model feasibility, experimental investigations on the 114 watts and 80 watts LED street lamp were conducted. The results demonstrated that the heat sink temperature of the 114 watts LED street lamp remained to be stable at about 60degC after several hourspsila lighting at the room temperature of 25degC. The heat sink temperature of the 80 watts LED street lamp remained to be stable at about 42degC at the room temperature of 11degC. Comparing the results achieved by the thermal resistance model with the experimental results, it was found that the proposed thermal resistance model could be used for temperature estimation and thermal evaluation for the high power street lamp.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"21 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91518817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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