Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606950
B. Xie, P. Sun, D. Shi
The needs to integrate devices into portable products with smaller form factor and more functionality have fueled enormous growth of 3D packaging technology. The package-on-package (PoP) is one of the 3D packaging solutions, by which the packaging and assembly houses can achieve a lower cost, faster turn benefits and testing prior to assembly. PoP is a complicated system with multi-layered structure, which induces more manufacturability issues, such as stand-off height issue and top & bottom packages having different types of warpage. In order to reduce R&D cost, achieve fast time-to-market and address most of the manufacturability issues during the development of a new PoP, a design advisor for PoP manufacturing has been developed based on the design for manufacturability (DFM) methodology. The key components of this design advisor are the validated numerical models, comprehensive materials library, design guidelines of PoP packaging and novel finite element analysis (FEA) techniques. With the developed novel FEA techniques for curing process simulation and seamless packaging process simulation, complete numerical models for PoP manufacturing were developed and validated, which can simulate the whole PoP manufacturing processes. The design advisor is easy to use by selecting package geometries, material properties and process parameters. By running the envelope-based design advisor for normal package design or the FEA-based design advisor for special package design, the detailed analysis reports can be generated, including simulation results, design evaluations and recommendations to ensure the first-time success of package design. Therefore, the design advisor can help improve the yield of complex PoP manufacturing processes leading to higher quality and confidence of manufacturing processes, faster time-to-market and lower overall manufacturing cost.
{"title":"Design advisor for package-on-package (PoP) manufacturing","authors":"B. Xie, P. Sun, D. Shi","doi":"10.1109/ICEPT.2008.4606950","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606950","url":null,"abstract":"The needs to integrate devices into portable products with smaller form factor and more functionality have fueled enormous growth of 3D packaging technology. The package-on-package (PoP) is one of the 3D packaging solutions, by which the packaging and assembly houses can achieve a lower cost, faster turn benefits and testing prior to assembly. PoP is a complicated system with multi-layered structure, which induces more manufacturability issues, such as stand-off height issue and top & bottom packages having different types of warpage. In order to reduce R&D cost, achieve fast time-to-market and address most of the manufacturability issues during the development of a new PoP, a design advisor for PoP manufacturing has been developed based on the design for manufacturability (DFM) methodology. The key components of this design advisor are the validated numerical models, comprehensive materials library, design guidelines of PoP packaging and novel finite element analysis (FEA) techniques. With the developed novel FEA techniques for curing process simulation and seamless packaging process simulation, complete numerical models for PoP manufacturing were developed and validated, which can simulate the whole PoP manufacturing processes. The design advisor is easy to use by selecting package geometries, material properties and process parameters. By running the envelope-based design advisor for normal package design or the FEA-based design advisor for special package design, the detailed analysis reports can be generated, including simulation results, design evaluations and recommendations to ensure the first-time success of package design. Therefore, the design advisor can help improve the yield of complex PoP manufacturing processes leading to higher quality and confidence of manufacturing processes, faster time-to-market and lower overall manufacturing cost.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"30 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76828155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607052
D. Shih, B. Dang, P. Gruber, M. Lu, S. Kang, S. Buchwalter, J. Knickerbocker, E. Perfecto, J. Garant, S. Knickerbocker, K. Semkow, B. Sundlof, J. Busby, R. Weisman, K. Ruhmer, E. Hughlett
Controlled collapse chip connection - new process (C4NP) technology is a novel solder bumping technology developed by IBM to address the limitations of existing bumping technologies. Through continuous improvements in processes, materials and defect control, C4NP technology has been successfully implemented at IBM in the manufacturing of all 300 mm Pb-free solder bumped wafers. Both 200 mum and 150 mum pitch products have been qualified and are currently ramping up volume production. Extendibility of C4NP to 50 mum ultra-fine pitch microbump application has been successfully demonstrated with the existing C4NP manufacturing tools. Targeted applications for microbumps are three-dimensional (3D) chip integration and the conversion of memory wafers from wirebonding (WB) to C4 bumping. The metrology data on solder volume, bump height, defect and yield have been characterized by RVSI inspection. This paper reviews the C4NP processes from mold manufacturing, solder fill and solder transfer onto 300 mm wafers, along with defect and yield analysis. Reliability challenges as well as solutions in the development and qualification of flip chip Pb-free solder joint are also reviewed. In addition to a suitable under bump metallurgy (UBM), a robust lead-free solder alloy with precisely controlled composition and special alloy doping is needed to enhance performance and reliability.
{"title":"C4NP for Pb-free solder wafer bumping and 3D fine-pitch applications","authors":"D. Shih, B. Dang, P. Gruber, M. Lu, S. Kang, S. Buchwalter, J. Knickerbocker, E. Perfecto, J. Garant, S. Knickerbocker, K. Semkow, B. Sundlof, J. Busby, R. Weisman, K. Ruhmer, E. Hughlett","doi":"10.1109/ICEPT.2008.4607052","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607052","url":null,"abstract":"Controlled collapse chip connection - new process (C4NP) technology is a novel solder bumping technology developed by IBM to address the limitations of existing bumping technologies. Through continuous improvements in processes, materials and defect control, C4NP technology has been successfully implemented at IBM in the manufacturing of all 300 mm Pb-free solder bumped wafers. Both 200 mum and 150 mum pitch products have been qualified and are currently ramping up volume production. Extendibility of C4NP to 50 mum ultra-fine pitch microbump application has been successfully demonstrated with the existing C4NP manufacturing tools. Targeted applications for microbumps are three-dimensional (3D) chip integration and the conversion of memory wafers from wirebonding (WB) to C4 bumping. The metrology data on solder volume, bump height, defect and yield have been characterized by RVSI inspection. This paper reviews the C4NP processes from mold manufacturing, solder fill and solder transfer onto 300 mm wafers, along with defect and yield analysis. Reliability challenges as well as solutions in the development and qualification of flip chip Pb-free solder joint are also reviewed. In addition to a suitable under bump metallurgy (UBM), a robust lead-free solder alloy with precisely controlled composition and special alloy doping is needed to enhance performance and reliability.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"39 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77096089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607140
Chang-Lin Yeh, Y. Lai, Ching-Chun Wang
We derive in this paper equations of motion of board-level IC packages subjected to swept sine vibration loads following the support excitation scheme. Harmonic analysis is performed based on the argument such that at each loading state over the swept sine process, hysteresis responses of solder joints following the isotropic hardening rule vanish fairly quickly so that plasticity is fully developed. Computed and measured acceleration response spectra of a board-level test vehicle are benchmarked. Stress-based failure indices as well as elastoplastic responses and strain rates of solder joints are examined for the test vehicle subjected to swept sine vibration tests of different acceleration levels with vibration frequencies up to 2 kHz.
{"title":"Parametric study on board-level electronic test device subjected to JEDEC vibration loads","authors":"Chang-Lin Yeh, Y. Lai, Ching-Chun Wang","doi":"10.1109/ICEPT.2008.4607140","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607140","url":null,"abstract":"We derive in this paper equations of motion of board-level IC packages subjected to swept sine vibration loads following the support excitation scheme. Harmonic analysis is performed based on the argument such that at each loading state over the swept sine process, hysteresis responses of solder joints following the isotropic hardening rule vanish fairly quickly so that plasticity is fully developed. Computed and measured acceleration response spectra of a board-level test vehicle are benchmarked. Stress-based failure indices as well as elastoplastic responses and strain rates of solder joints are examined for the test vehicle subjected to swept sine vibration tests of different acceleration levels with vibration frequencies up to 2 kHz.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"6 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73153228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607161
Q. Chen, Leon Xu, A. Salo, Gustavo Neto, Germano Freitas
Flexible display module reliability were investigated herein with experiments, such as bending, twisting and ball drop. The pretests of all the three experiments were carried out firstly to primarily understand the flexibility and mechanical behavior of the display. Based on the pretest results, the corresponding fatigue test setup method and process were put forward. Then, the fatigue tests were executed. At last, through the failure analysis, the flexibility and reliability of the flexible display in different use cases were evaluated. Suggestions about how to use the display and improve the reliability through change the design were given also.
{"title":"Reliability study of flexible display module by experiments","authors":"Q. Chen, Leon Xu, A. Salo, Gustavo Neto, Germano Freitas","doi":"10.1109/ICEPT.2008.4607161","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607161","url":null,"abstract":"Flexible display module reliability were investigated herein with experiments, such as bending, twisting and ball drop. The pretests of all the three experiments were carried out firstly to primarily understand the flexibility and mechanical behavior of the display. Based on the pretest results, the corresponding fatigue test setup method and process were put forward. Then, the fatigue tests were executed. At last, through the failure analysis, the flexibility and reliability of the flexible display in different use cases were evaluated. Suggestions about how to use the display and improve the reliability through change the design were given also.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"87 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73616625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606938
A. Lee, Louie Huang, M. Hung
The package on package (POP) stacking is getting more and more popular for system in package (SIP) applications. But during the assembly process, the POP had encountered the challenge of packages stacking yield loss, especially when top package and bottom package stacking. The key factors are the mount height of top package, the mold cap of bottom package, and the metallized ball land on the top surface of bottom package. JEDEC JC-11 has defined the rules of two packages stacking. However, the fine pitch package stacking application will meet the process capability limitation, including thinner mold cap, wafer thinning and the lowest wire bond loop height challenges. The POP used the top gate mold chase for the bottom package to expose the metallized ball land on the top side of package which is a dedicated molding tooling. Also, some process are used for solving yield loss issues such as a POP with interposer between top package and bottom package, or a bottom package with pre-mounted the solder ball on chip side ready for top package to attach. Those are customized tooling and not a prevailing tooling that increases the developing cost and timing. To resolve the stacking process yield loss issue, a MAPPOP solution had been revealed for eliminating the limitation between the top and bottom package stacking. The assembly process of mold array package (MAP) for fine pitch BGA has been implemented for MAPPOP applications. In the paper, the package design rules, and assembly process of exposed metallized ball land on the top surface of bottom package had been discussed. Finally the warpage performance and the packaging level reliability had also been discussed and analyzed.
{"title":"Mold array package for POP applications","authors":"A. Lee, Louie Huang, M. Hung","doi":"10.1109/ICEPT.2008.4606938","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606938","url":null,"abstract":"The package on package (POP) stacking is getting more and more popular for system in package (SIP) applications. But during the assembly process, the POP had encountered the challenge of packages stacking yield loss, especially when top package and bottom package stacking. The key factors are the mount height of top package, the mold cap of bottom package, and the metallized ball land on the top surface of bottom package. JEDEC JC-11 has defined the rules of two packages stacking. However, the fine pitch package stacking application will meet the process capability limitation, including thinner mold cap, wafer thinning and the lowest wire bond loop height challenges. The POP used the top gate mold chase for the bottom package to expose the metallized ball land on the top side of package which is a dedicated molding tooling. Also, some process are used for solving yield loss issues such as a POP with interposer between top package and bottom package, or a bottom package with pre-mounted the solder ball on chip side ready for top package to attach. Those are customized tooling and not a prevailing tooling that increases the developing cost and timing. To resolve the stacking process yield loss issue, a MAPPOP solution had been revealed for eliminating the limitation between the top and bottom package stacking. The assembly process of mold array package (MAP) for fine pitch BGA has been implemented for MAPPOP applications. In the paper, the package design rules, and assembly process of exposed metallized ball land on the top surface of bottom package had been discussed. Finally the warpage performance and the packaging level reliability had also been discussed and analyzed.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"50 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75741070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607159
Dongfang Cheng, Jue Zhang, Xiaohui Li, Jiongming Wang
Illustrated by the case of a lithium-ion battery protection IC, the paper focuses on the design of internal immunity to RFI. With analysis of the chippsilas three major elements of electromagnetic compatibility (EMC), the qualitative and quasi-quantitative analysis results of RFI influence to the chip are given out. By using a simple filter circuit and available material physical construction which can isolate, absorb and consume the RFI energy, the protection ICpsilas electromagnetic susceptibility has been reduced effectively. The simulation of the devised structure in the time domain is gained by Winspice, and tool IC_EMC makes it possible of the conversion from time domain to frequency domain in which the spectrum analysis is completed. The design has passed the simulation verification and the layout implement of the devised construction designed is also available.
{"title":"A design for increasing the immunity to RFI of protection IC of lithium-ion battery","authors":"Dongfang Cheng, Jue Zhang, Xiaohui Li, Jiongming Wang","doi":"10.1109/ICEPT.2008.4607159","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607159","url":null,"abstract":"Illustrated by the case of a lithium-ion battery protection IC, the paper focuses on the design of internal immunity to RFI. With analysis of the chippsilas three major elements of electromagnetic compatibility (EMC), the qualitative and quasi-quantitative analysis results of RFI influence to the chip are given out. By using a simple filter circuit and available material physical construction which can isolate, absorb and consume the RFI energy, the protection ICpsilas electromagnetic susceptibility has been reduced effectively. The simulation of the devised structure in the time domain is gained by Winspice, and tool IC_EMC makes it possible of the conversion from time domain to frequency domain in which the spectrum analysis is completed. The design has passed the simulation verification and the layout implement of the devised construction designed is also available.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"29 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74792269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607158
Xiaoyan Li, Yongchang Yan, Na Liu
A thermodynamics-based damage mechanics rate dependent constitutive model is used to simulate experiments conducted on thin layer eutectic SnAgCu(SAC) solder joints. The non-damage constitutive is measured by bulk tensile test. The relationship between true stress and strain is sigma=85.26epsiv0.3536. Damage evolution equation is proposed based Lemaitre ductile damage theory and the constant in the equation is measured by unloading elastic modulus method. The damage evolution equation is D=1.0689epsivP-0.0008. Simulation (using software Ansys 9.0) of shear test of solder joint between Cu sticks employing damage mechanics rate independent constitutive is uniform to practicable test.
{"title":"Study of plasticity damage mechanics constitutive model for SnAgCu solder joint","authors":"Xiaoyan Li, Yongchang Yan, Na Liu","doi":"10.1109/ICEPT.2008.4607158","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607158","url":null,"abstract":"A thermodynamics-based damage mechanics rate dependent constitutive model is used to simulate experiments conducted on thin layer eutectic SnAgCu(SAC) solder joints. The non-damage constitutive is measured by bulk tensile test. The relationship between true stress and strain is sigma=85.26epsiv0.3536. Damage evolution equation is proposed based Lemaitre ductile damage theory and the constant in the equation is measured by unloading elastic modulus method. The damage evolution equation is D=1.0689epsivP-0.0008. Simulation (using software Ansys 9.0) of shear test of solder joint between Cu sticks employing damage mechanics rate independent constitutive is uniform to practicable test.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"56 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90326648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606952
Junwen Liu, Qing‐An Huang, J. Shang, Jing Song, Jie-ying Tang
In the domain of manufacturing and packaging of micro-system, the Pyrex7740 glass is a widely-used material since its coefficient of thermal expansion is similar to that of silicon, and its good optical performance for biosensors and optical sensors. But the use of Pyrex7740 glass is limited for its isotropic etching characteristic of tradition micro-machining. In this paper, we present a new process to fabricate deep grooves in Pyrex7740 glass. The process is based on the anodic bonding, and it uses the Si substrate as the mold for forming the shape of the cavity. Finally the cavities were formed by the atmospheric pressure after the special heat treatment. The Pyrex7740 glass with cavities could be used for high density packaging of micro-system by anodic bonding or adhesive bonding. The approach of fabricating deep cavities in Pyrex7740 glass is a key technology, which has seldom studied before. We have experimentally verified the feasibility of this new process. First of all, we fabricated the array of desired shape of cavities on silicon substrate by wet etching or dry etching. It is much easier to get the precise shape on the silicon substrate by micro machining than in Pyrex7740 glass. In our experiment, we had chosen several different side length of the square as a pattern. Then we bonded the Pyrex7740 glass and the silicon substrate together under the vacuum environment by anodic bonding. After that twice heat treatments were taken to the bonding wafer. One was to form the Pyrex7740 glass into desired shape by the silicon mold with the temperature up to the softening point. Another was to release thermal stress of the anodic bonding and the first heat treatment. The placement of the wafer during the heat treatment must be taken attention to. Finally, the bonding wafer with cavities was finished for the high density packaging of micro-system.
{"title":"A new process to fabricate cavities in Pyrex7740 glass for high density packaging of micro-system","authors":"Junwen Liu, Qing‐An Huang, J. Shang, Jing Song, Jie-ying Tang","doi":"10.1109/ICEPT.2008.4606952","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606952","url":null,"abstract":"In the domain of manufacturing and packaging of micro-system, the Pyrex7740 glass is a widely-used material since its coefficient of thermal expansion is similar to that of silicon, and its good optical performance for biosensors and optical sensors. But the use of Pyrex7740 glass is limited for its isotropic etching characteristic of tradition micro-machining. In this paper, we present a new process to fabricate deep grooves in Pyrex7740 glass. The process is based on the anodic bonding, and it uses the Si substrate as the mold for forming the shape of the cavity. Finally the cavities were formed by the atmospheric pressure after the special heat treatment. The Pyrex7740 glass with cavities could be used for high density packaging of micro-system by anodic bonding or adhesive bonding. The approach of fabricating deep cavities in Pyrex7740 glass is a key technology, which has seldom studied before. We have experimentally verified the feasibility of this new process. First of all, we fabricated the array of desired shape of cavities on silicon substrate by wet etching or dry etching. It is much easier to get the precise shape on the silicon substrate by micro machining than in Pyrex7740 glass. In our experiment, we had chosen several different side length of the square as a pattern. Then we bonded the Pyrex7740 glass and the silicon substrate together under the vacuum environment by anodic bonding. After that twice heat treatments were taken to the bonding wafer. One was to form the Pyrex7740 glass into desired shape by the silicon mold with the temperature up to the softening point. Another was to release thermal stress of the anodic bonding and the first heat treatment. The placement of the wafer during the heat treatment must be taken attention to. Finally, the bonding wafer with cavities was finished for the high density packaging of micro-system.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83848650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4607046
Zhili Hu, X. Guo, J. Liu
An elastic string-elastic shell model is developed to study vibration behaviors of a carbon nanowire. The present model predicts that non-coaxial vibration between the C-chain and the innermost tube does not occur due to negligible bending rigidity of the C-chain. In addition, it is found that the C-chain has most significant effect on the lowest frequency associated with radial vibration mode for circumferential wave-number 2 (n=2). In particular, the effect of the C-chain on axisymmetric radial breathing frequencies (n=0) predicted by the present model is found to be in reasonable agreement with known experimental and modeling results available in the literature.
{"title":"Vibration and buckling of a carbon nanotube inserted with a carbon chain","authors":"Zhili Hu, X. Guo, J. Liu","doi":"10.1109/ICEPT.2008.4607046","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607046","url":null,"abstract":"An elastic string-elastic shell model is developed to study vibration behaviors of a carbon nanowire. The present model predicts that non-coaxial vibration between the C-chain and the innermost tube does not occur due to negligible bending rigidity of the C-chain. In addition, it is found that the C-chain has most significant effect on the lowest frequency associated with radial vibration mode for circumferential wave-number 2 (n=2). In particular, the effect of the C-chain on axisymmetric radial breathing frequencies (n=0) predicted by the present model is found to be in reasonable agreement with known experimental and modeling results available in the literature.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"102 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76770194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606970
Guohua Gao, Honghui Wang, Guoji Yang, Haiqing Zhu
Electronic package plays an important part in the development of IC industry. As we all known, strip warpage is a critical issue for the MAP-QFN manufacturing, results from the package structure, the thermal mismatch of materials and the manufacturing process. In this paper, a new finite element model was used to predict the warpage of one MAP-QFN block. And in this model, the temperature-dependent parameters of materials were characterized by DMA and DSC measurements, and the boundary condition was set up to be close to the real deforming situation. Furthermore, by the geometric triangle principle, the calculated warpage was also verified with the experiment measurement data. Finally we accomplished the optimization of related package parameters, and decreased the warpage of MAP-QFN by applying the dead weight on the strip block in the post mould curing process.
{"title":"A new method for the investigation of strip warpage of MAP-QFN","authors":"Guohua Gao, Honghui Wang, Guoji Yang, Haiqing Zhu","doi":"10.1109/ICEPT.2008.4606970","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606970","url":null,"abstract":"Electronic package plays an important part in the development of IC industry. As we all known, strip warpage is a critical issue for the MAP-QFN manufacturing, results from the package structure, the thermal mismatch of materials and the manufacturing process. In this paper, a new finite element model was used to predict the warpage of one MAP-QFN block. And in this model, the temperature-dependent parameters of materials were characterized by DMA and DSC measurements, and the boundary condition was set up to be close to the real deforming situation. Furthermore, by the geometric triangle principle, the calculated warpage was also verified with the experiment measurement data. Finally we accomplished the optimization of related package parameters, and decreased the warpage of MAP-QFN by applying the dead weight on the strip block in the post mould curing process.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"5 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85240034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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