Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479112
T. Egawa
Developments of heteroepitaxial growth and characteristics of an AlGaN/GaN HEMT on a Si substrate are reported. High-temperature-grown AlGaN/AlN intermediate layers and GaN/AlN strained layer superlattice are effective in improving the crystallinity of a following GaN layer and for growing thick device structure on Si, which resulted in obtaining high-breakdown voltage. The AlGaN/GaN HEMT on Si exhibited the breakdown voltage as high as 1402 V with a state-of-the-art figure-of-merit (FOM = BV2/Ron) of 2.6×108 V2Ω-1cm-2.
{"title":"Heteroepitaxial growth and power electronics using AlGaN/GaN HEMT on Si","authors":"T. Egawa","doi":"10.1109/IEDM.2012.6479112","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479112","url":null,"abstract":"Developments of heteroepitaxial growth and characteristics of an AlGaN/GaN HEMT on a Si substrate are reported. High-temperature-grown AlGaN/AlN intermediate layers and GaN/AlN strained layer superlattice are effective in improving the crystallinity of a following GaN layer and for growing thick device structure on Si, which resulted in obtaining high-breakdown voltage. The AlGaN/GaN HEMT on Si exhibited the breakdown voltage as high as 1402 V with a state-of-the-art figure-of-merit (FOM = BV<sup>2</sup>/R<sub>on</sub>) of 2.6×10<sup>8</sup> V<sup>2</sup>Ω<sup>-1</sup>cm<sup>-2</sup>.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"12 1","pages":"27.1.1-27.1.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84356270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6478992
M. Pala, D. Esseni, F. Conzatti
We present the first computational study employing a full quantum transport model to investigate the effect of interface traps in nanowire InAs Tunnel FETs and MOSFETs. To this purpose, we introduced a description of interface traps in a simulator based on the NEGF formalism and on a 8×8 k·p Hamiltonian and accounting for phonon scattering. Our results show that: (a) even a single trap can detereorate the inverse sub-threshold slope (SS) of a nanowire InAs Tunnel FET; (b) the inelastic phonon assisted tunneling (PAT) through interface traps results in a temperature dependence of the Tunnel FETs IV characteristics; (c) the impact of interface traps on Ioff is larger in Tunnel FETs than in MOSFETs; (d) interface traps represent a sizable source of device variability.
{"title":"Impact of interface traps on the IV curves of InAs Tunnel-FETs and MOSFETs: A full quantum study","authors":"M. Pala, D. Esseni, F. Conzatti","doi":"10.1109/IEDM.2012.6478992","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6478992","url":null,"abstract":"We present the first computational study employing a full quantum transport model to investigate the effect of interface traps in nanowire InAs Tunnel FETs and MOSFETs. To this purpose, we introduced a description of interface traps in a simulator based on the NEGF formalism and on a 8×8 k·p Hamiltonian and accounting for phonon scattering. Our results show that: (a) even a single trap can detereorate the inverse sub-threshold slope (SS) of a nanowire InAs Tunnel FET; (b) the inelastic phonon assisted tunneling (PAT) through interface traps results in a temperature dependence of the Tunnel FETs IV characteristics; (c) the impact of interface traps on Ioff is larger in Tunnel FETs than in MOSFETs; (d) interface traps represent a sizable source of device variability.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"1 1","pages":"6.6.1-6.6.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90278035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479069
L. Perniola, P. Noé, Q. Hubert, S. Souiki, G. Ghezzi, G. Navarro, A. Cabrini, A. Persico, V. Delaye, D. Blachier, J. Barnes, E. Henaff, M. Tessaire, E. Souchier, A. Roule, F. Fillot, J. Ferrand, A. Fargeix, F. Hippert, J. Raty, C. Jahan, V. Sousa, G. Torelli, S. Maitrejean, B. De Salvo, G. Reimbold
In this paper, we present a thorough physical-chemical analysis of an engineered PCM stack, where the integration of C-doping and the use of a Ti top layer allow obtaining an Amorphous As-Deposited (A-AD) phase stable against Back End-Of-Line (BEOL) thermal budget. This PCM stack is then integrated in devices, which are extensively tested in order to validate a novel pre-coding technique compliant to the Pb-free soldering reflow issue. Finally, an original design to optimize the distribution dispersion is presented.
{"title":"Ti impact in C-doped phase-change memories compliant to Pb-free soldering reflow","authors":"L. Perniola, P. Noé, Q. Hubert, S. Souiki, G. Ghezzi, G. Navarro, A. Cabrini, A. Persico, V. Delaye, D. Blachier, J. Barnes, E. Henaff, M. Tessaire, E. Souchier, A. Roule, F. Fillot, J. Ferrand, A. Fargeix, F. Hippert, J. Raty, C. Jahan, V. Sousa, G. Torelli, S. Maitrejean, B. De Salvo, G. Reimbold","doi":"10.1109/IEDM.2012.6479069","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479069","url":null,"abstract":"In this paper, we present a thorough physical-chemical analysis of an engineered PCM stack, where the integration of C-doping and the use of a Ti top layer allow obtaining an Amorphous As-Deposited (A-AD) phase stable against Back End-Of-Line (BEOL) thermal budget. This PCM stack is then integrated in devices, which are extensively tested in order to validate a novel pre-coding technique compliant to the Pb-free soldering reflow issue. Finally, an original design to optimize the distribution dispersion is presented.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"53 80 1","pages":"18.7.1-18.7.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90365887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479138
M. Bina, K. Rupp, S. Tyaginov, O. Triebl, T. Grasser
Recent studies have clearly demonstrated that the degradation of MOS transistors due to hot carriers is highly sensitive to the energy distribution of the carriers. These distributions can only be obtained in sufficient detail by the simultaneous solution of the Boltzmann transport equation (BTE) for both carrier types. For predictive simulations, the energy distributions have to be thoroughly resolved by including the fullband structure, impact ionization (II), electron electron scattering (EE), as well as the interaction of minority carriers with the majority carriers. We demonstrate that this challenging problem can be efficiently tackled using a deterministic approach based on the spherical harmonics expansion (SHE) of the BTE.
{"title":"Modeling of hot carrier degradation using a spherical harmonics expansion of the bipolar Boltzmann transport equation","authors":"M. Bina, K. Rupp, S. Tyaginov, O. Triebl, T. Grasser","doi":"10.1109/IEDM.2012.6479138","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479138","url":null,"abstract":"Recent studies have clearly demonstrated that the degradation of MOS transistors due to hot carriers is highly sensitive to the energy distribution of the carriers. These distributions can only be obtained in sufficient detail by the simultaneous solution of the Boltzmann transport equation (BTE) for both carrier types. For predictive simulations, the energy distributions have to be thoroughly resolved by including the fullband structure, impact ionization (II), electron electron scattering (EE), as well as the interaction of minority carriers with the majority carriers. We demonstrate that this challenging problem can be efficiently tackled using a deterministic approach based on the spherical harmonics expansion (SHE) of the BTE.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"1 1","pages":"30.5.1-30.5.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90591478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479031
O. Puscasu, S. Monfray, G. Savelli, C. Maitre, J. P. Pemeant, P. Coronel, K. Domanski, P. Grabiec, P. Ancey, P. Cottinet, D. Guyomar, V. Bottarel, G. Ricotti, I. Bimbaud, F. Boeuf, F. Gaillard, T. Skotnicki
An innovative approach to heat energy harvesting (HEATec) is proposed in this paper. It consists of a two-step conversion of heat into electricity. The first step is a thermo-mechanical conversion by a bimetal and the second is an electromechanical conversion by a piezoelectric. The first developed prototypes show natural thermal resistance matching between their body and the interface with ambient air, and therefore do not need a heat sink in order to work. The available mechanical power (2.7 mW/cm2 measured in practice for a single bimetal, and extendable to theoretical 27 mW/cm2 for 100 bimetals occupying the same surface) that can be converted into electricity may lead to a superior performance compared to the best commercial Seebeck devices. Analytical scaling laws for our technology have been established and show power density gain equal to the scaling factor, making it LSI integration favorable.
{"title":"An innovative heat harvesting technology (HEATec) for above-Seebeck performance","authors":"O. Puscasu, S. Monfray, G. Savelli, C. Maitre, J. P. Pemeant, P. Coronel, K. Domanski, P. Grabiec, P. Ancey, P. Cottinet, D. Guyomar, V. Bottarel, G. Ricotti, I. Bimbaud, F. Boeuf, F. Gaillard, T. Skotnicki","doi":"10.1109/IEDM.2012.6479031","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479031","url":null,"abstract":"An innovative approach to heat energy harvesting (HEATec) is proposed in this paper. It consists of a two-step conversion of heat into electricity. The first step is a thermo-mechanical conversion by a bimetal and the second is an electromechanical conversion by a piezoelectric. The first developed prototypes show natural thermal resistance matching between their body and the interface with ambient air, and therefore do not need a heat sink in order to work. The available mechanical power (2.7 mW/cm2 measured in practice for a single bimetal, and extendable to theoretical 27 mW/cm2 for 100 bimetals occupying the same surface) that can be converted into electricity may lead to a superior performance compared to the best commercial Seebeck devices. Analytical scaling laws for our technology have been established and show power density gain equal to the scaling factor, making it LSI integration favorable.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"63 1","pages":"12.5.1-12.5.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89071859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6478970
F. Arnaud, Nicolas Planes, O. Weber, V. Barral, S. Haendler, Philippe Flatresse, F. Nyer
This paper presents the superior performance of UTBB (Ultra-Thin Box and Body) technology for providing high speed at low voltage. We evidence the transistor capability to sustain full forward-body-biasing solution thanks to a planar back-side gate scheme. Silicon measurements on low complexity circuits show that the dynamic power consumption can be reduced by 90% without any speed degradation by simply selecting the appropriate power supply and body bias couple (Vdd; Vbb). A simple switching energy efficiency model is then proposed allowing the (Vdd; Vbb) couple prediction reaching the minimum energy point. Finally, we demonstrate on a full CPU Core implementation with UTBB a total power reduction of -30% and a +40% energy efficiency at identical speed with respect to bulk technology thanks to back side gate biasing efficiency.
本文介绍了超薄盒体(Ultra-Thin Box and Body, UTBB)技术在低电压下提供高速的优越性能。我们证明了由于平面背面栅极方案，晶体管能够维持完全的正向体偏置解决方案。在低复杂度电路上的硅测量表明，通过简单地选择合适的电源和体偏置耦合器(Vdd;Vbb)。然后提出了一个简单的开关能效模型，允许(Vdd;Vbb)耦合预测达到最小能量点。最后，我们展示了一个完整的CPU核心实现与UTBB，总功耗降低-30%和+40%的能源效率在相同的速度相对于散装技术，由于后门偏置效率。
{"title":"Switching energy efficiency optimization for advanced CPU thanks to UTBB technology","authors":"F. Arnaud, Nicolas Planes, O. Weber, V. Barral, S. Haendler, Philippe Flatresse, F. Nyer","doi":"10.1109/IEDM.2012.6478970","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6478970","url":null,"abstract":"This paper presents the superior performance of UTBB (Ultra-Thin Box and Body) technology for providing high speed at low voltage. We evidence the transistor capability to sustain full forward-body-biasing solution thanks to a planar back-side gate scheme. Silicon measurements on low complexity circuits show that the dynamic power consumption can be reduced by 90% without any speed degradation by simply selecting the appropriate power supply and body bias couple (Vdd; Vbb). A simple switching energy efficiency model is then proposed allowing the (Vdd; Vbb) couple prediction reaching the minimum energy point. Finally, we demonstrate on a full CPU Core implementation with UTBB a total power reduction of -30% and a +40% energy efficiency at identical speed with respect to bulk technology thanks to back side gate biasing efficiency.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":" 71","pages":"3.2.1-3.2.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91414785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479139
Zheng Xu, J. J. Lu
This paper reports on a novel partition and assembly approach that combines both the electromagnetic (EM) and analytical simulations to accurately model and analyze several through-silicon-via (TSV) based 3D power delivery networks, which are composed of various stacked-chips, interposer, and package substrate. With this method, we also analyzed RLC couplings between multiple voltage supply rails in 3D systems. The quantitatively examined power performance unveils 3D power delivery design implications, which is useful for 3D system design and fabrication.
{"title":"Hybrid modeling and analysis of different through-silicon-Via (TSV)-based 3D power distribution networks","authors":"Zheng Xu, J. J. Lu","doi":"10.1109/IEDM.2012.6479139","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479139","url":null,"abstract":"This paper reports on a novel partition and assembly approach that combines both the electromagnetic (EM) and analytical simulations to accurately model and analyze several through-silicon-via (TSV) based 3D power delivery networks, which are composed of various stacked-chips, interposer, and package substrate. With this method, we also analyzed RLC couplings between multiple voltage supply rails in 3D systems. The quantitatively examined power performance unveils 3D power delivery design implications, which is useful for 3D system design and fabrication.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"40 1","pages":"30.6.1-30.6.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90882458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6478974
L. Grenouillet, M. Vinet, J. Gimbert, B. Giraud, J. Noel, Q. Liu, P. Khare, M. Jaud, Y. Le Tiec, R. Wacquez, T. Levin, P. Rivallin, S. Holmes, S. Liu, K. Chen, O. Rozeau, P. Scheiblin, E. Mclellan, M. Malley, J. Guilford, A. Upham, R. Johnson, M. Hargrove, T. Hook, S. Schmitz, S. Mehta, J. Kuss, N. Loubet, S. Teehan, M. Terrizzi, S. Ponoth, K. Cheng, T. Nagumo, A. Khakifirooz, F. Monsieur, P. Kulkarni, R. Conte, J. Demarest, O. Faynot, W. Kleemeier, S. Luning, B. Doris
We introduce an innovative dual-depth shallow trench isolation (dual STI) scheme for Ultra Thin Body and BOX (UTBB) FDSOI architecture. Since in the dual STI configuration wells are isolated from one another by the deepest trenches, this architecture enables a full use of the back bias while staying compatible with both standard bulk design and conventional SOI substrates. We demonstrate in 20nm ground rules that we are able to tune Vt by more than 400mV, that transistor performance can be boosted by up to 30% and that Ioff can be controlled over 3 decades by allowing more than VDD/2 to be applied on the back gate.
{"title":"UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below","authors":"L. Grenouillet, M. Vinet, J. Gimbert, B. Giraud, J. Noel, Q. Liu, P. Khare, M. Jaud, Y. Le Tiec, R. Wacquez, T. Levin, P. Rivallin, S. Holmes, S. Liu, K. Chen, O. Rozeau, P. Scheiblin, E. Mclellan, M. Malley, J. Guilford, A. Upham, R. Johnson, M. Hargrove, T. Hook, S. Schmitz, S. Mehta, J. Kuss, N. Loubet, S. Teehan, M. Terrizzi, S. Ponoth, K. Cheng, T. Nagumo, A. Khakifirooz, F. Monsieur, P. Kulkarni, R. Conte, J. Demarest, O. Faynot, W. Kleemeier, S. Luning, B. Doris","doi":"10.1109/IEDM.2012.6478974","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6478974","url":null,"abstract":"We introduce an innovative dual-depth shallow trench isolation (dual STI) scheme for Ultra Thin Body and BOX (UTBB) FDSOI architecture. Since in the dual STI configuration wells are isolated from one another by the deepest trenches, this architecture enables a full use of the back bias while staying compatible with both standard bulk design and conventional SOI substrates. We demonstrate in 20nm ground rules that we are able to tune Vt by more than 400mV, that transistor performance can be boosted by up to 30% and that Ioff can be controlled over 3 decades by allowing more than VDD/2 to be applied on the back gate.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"109 1","pages":"3.6.1-3.6.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79265731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479027
D. Psaltis, W. Song, A. Vasdekis
Optofluidic devices are most commonly fabricated using microfluidic technology into which photonic capability is embedded. Lasers, microscopes, sensors, optical fibers, and lenses can be fabricated with this approach [1]. The application areas of optofluidics include tunable optical devices, biophotonics [2], and more recently solar energy harvesting [3].
{"title":"Optofluidic devices and applications","authors":"D. Psaltis, W. Song, A. Vasdekis","doi":"10.1109/IEDM.2012.6479027","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479027","url":null,"abstract":"Optofluidic devices are most commonly fabricated using microfluidic technology into which photonic capability is embedded. Lasers, microscopes, sensors, optical fibers, and lenses can be fabricated with this approach [1]. The application areas of optofluidics include tunable optical devices, biophotonics [2], and more recently solar energy harvesting [3].","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"37 1","pages":"12.1.1-12.1.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80107280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479113
K. Shinohara, D. Regan, A. Corrion, D. Brown, Y. Tang, J. Wong, G. Candia, A. Schmitz, H. Fung, S. Kim, M. Micovic
We report record DC and RF performance obtained in deeply-scaled self-aligned-gate GaN-HEMTs with heavily-doped n+-GaN ohmic contacts to two-dimensional electron-gas (2DEG). High density-of-states of three-dimensional (3D) n+-GaN source near the gate mitigates “source-starvation,” resulting in a dramatic increase in a maximum drain current (Idmax) and a transconductance (gm). 20-nm-gate D-mode HEMTs with a 40-nm gate-source (and gate-drain) distance exhibited a record-low Ron of 0.23 Ω·mm, a record-high Idmax of >4 A/mm, and a broad gm curve of >1 S/mm over a wide range of Ids from 0.5 to 3.5 A/mm. Furthermore, 20-nm-gate E-mode HEMTs with an increased Lsw of 70 nm demonstrated a simultaneous fT/fmax of 342/518 GHz with an off-state breakdown voltage of 14V.
我们报告了在深度尺度自校准栅极gan - hemt中获得的创纪录的直流和射频性能，这些gan - hemt具有重掺杂的n+-GaN欧姆接触到二维电子-气体(2DEG)。栅极附近的三维(3D) n+-GaN源的高密度状态减轻了“源饥饿”，导致最大漏极电流(Idmax)和跨导(gm)的急剧增加。当栅极-源极(和栅极-漏极)距离为40 nm时，20 nm栅极d模hemt的Ron值最低，为0.23 Ω·mm; Idmax值最高，为>4 a /mm;在0.5 ~ 3.5 a /mm的宽Ids范围内，gm曲线宽，>1 S/mm。此外，Lsw增加到70 nm的20 nm栅极e模hemt的同时fT/fmax为342/518 GHz，断态击穿电压为14V。
{"title":"Self-aligned-gate GaN-HEMTs with heavily-doped n+-GaN ohmic contacts to 2DEG","authors":"K. Shinohara, D. Regan, A. Corrion, D. Brown, Y. Tang, J. Wong, G. Candia, A. Schmitz, H. Fung, S. Kim, M. Micovic","doi":"10.1109/IEDM.2012.6479113","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479113","url":null,"abstract":"We report record DC and RF performance obtained in deeply-scaled self-aligned-gate GaN-HEMTs with heavily-doped n<sup>+</sup>-GaN ohmic contacts to two-dimensional electron-gas (2DEG). High density-of-states of three-dimensional (3D) n<sup>+</sup>-GaN source near the gate mitigates “source-starvation,” resulting in a dramatic increase in a maximum drain current (I<sub>dmax</sub>) and a transconductance (g<sub>m</sub>). 20-nm-gate D-mode HEMTs with a 40-nm gate-source (and gate-drain) distance exhibited a record-low R<sub>on</sub> of 0.23 Ω·mm, a record-high I<sub>dmax</sub> of >4 A/mm, and a broad g<sub>m</sub> curve of >1 S/mm over a wide range of I<sub>ds</sub> from 0.5 to 3.5 A/mm. Furthermore, 20-nm-gate E-mode HEMTs with an increased L<sub>sw</sub> of 70 nm demonstrated a simultaneous f<sub>T</sub>/f<sub>max</sub> of 342/518 GHz with an off-state breakdown voltage of 14V.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"94 1","pages":"27.2.1-27.2.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76683342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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