Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479090
Shu‐Han Hsu, Hung-Chih Chang, C. Chu, Yen‐Ting Chen, W. Tu, F. Hou, Chih-hung Lo, P. Sung, Bo-Yuan Chen, G. Huang, G. Luo, Cheewee Liu, C. Hu, Fu-Liang Yang
Due to the highest electron mobility (2200 cm2/Vs) on (111) Ge surface, the n-channel triangular Ge gate-all-around (GAA) FET with (111) sidewalls on Si and Lg=350 nm shows 2x enhanced Ion of 110 μA/μm at 1V with respect to the devices with near (110) sidewalls. A novel process to etch away the defective Ge near Ge/Si interface from epitaxial Ge grown on SOI achieves a nearly defect-free channel, good gate control triangular gate, and larger effective width. Electrostatic control of SS= 94 mV/dec (at 1V) can be further improved if superior gate stack than EOT= 5.5 nm and Dit= 1×1012 cm-2eV-1 is used. The Ion can be further enhanced if the line edge roughness (LER) can be reduced. The Ge GAA n-FET is reported for the first time with CMOS compatible process, which makes the circuits integration much easier.
{"title":"Triangular-channel Ge NFETs on Si with (111) sidewall-enhanced Ion and nearly defect-free channels","authors":"Shu‐Han Hsu, Hung-Chih Chang, C. Chu, Yen‐Ting Chen, W. Tu, F. Hou, Chih-hung Lo, P. Sung, Bo-Yuan Chen, G. Huang, G. Luo, Cheewee Liu, C. Hu, Fu-Liang Yang","doi":"10.1109/IEDM.2012.6479090","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479090","url":null,"abstract":"Due to the highest electron mobility (2200 cm<sup>2</sup>/Vs) on (111) Ge surface, the n-channel triangular Ge gate-all-around (GAA) FET with (111) sidewalls on Si and L<sub>g</sub>=350 nm shows 2x enhanced I<sub>on</sub> of 110 μA/μm at 1V with respect to the devices with near (110) sidewalls. A novel process to etch away the defective Ge near Ge/Si interface from epitaxial Ge grown on SOI achieves a nearly defect-free channel, good gate control triangular gate, and larger effective width. Electrostatic control of SS= 94 mV/dec (at 1V) can be further improved if superior gate stack than EOT= 5.5 nm and D<sub>it</sub>= 1×10<sup>12</sup> cm<sup>-2</sup>eV<sup>-1</sup> is used. The I<sub>on</sub> can be further enhanced if the line edge roughness (LER) can be reduced. The Ge GAA n-FET is reported for the first time with CMOS compatible process, which makes the circuits integration much easier.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"21 1","pages":"23.6.1-23.6.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77726614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6478980
H. Wang, L. Yu, Y. Lee, W. Fang, A. Hsu, P. Herring, M. Chin, M. Dubey, L. Li, J. Kong, T. Palacios
2D nanoelectronics based on single-layer MoS2 offers great advantages for both conventional and ubiquitous applications. This paper discusses the large-scale CVD growth of single-layer MoS2 and fabrication of integrated devices and circuits for the first time. Fundamental building blocks of digital electronics, such as inverters and NAND gates, are fabricated to demonstrate its capability for logic applications.
{"title":"Large-scale 2D electronics based on single-layer MoS2 grown by chemical vapor deposition","authors":"H. Wang, L. Yu, Y. Lee, W. Fang, A. Hsu, P. Herring, M. Chin, M. Dubey, L. Li, J. Kong, T. Palacios","doi":"10.1109/IEDM.2012.6478980","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6478980","url":null,"abstract":"2D nanoelectronics based on single-layer MoS2 offers great advantages for both conventional and ubiquitous applications. This paper discusses the large-scale CVD growth of single-layer MoS2 and fabrication of integrated devices and circuits for the first time. Fundamental building blocks of digital electronics, such as inverters and NAND gates, are fabricated to demonstrate its capability for logic applications.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"25 1","pages":"4.6.1-4.6.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82228598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6478998
T. Hosoi, Shuji Azumo, Yusaku Kashiwagi, S. Hosaka, R. Nakamura, Shuhei Mitani, Y. Nakano, H. Asahara, Takashi Nakamura, Tsunenobu Kimoto, T. Shimura, Heiji Watanabe
We have developed AlON high-k gate dielectric technology that can be easily implemented into both planar and trench SiC-based MOSFETs. On the basis of electrical characterization and numerical simulation, the thickness ratio of the AlON layer to the SiO2 interlayer and nitrogen content in AlON film were carefully optimized to enhance device performance and reliability.
{"title":"Performance and reliability improvement in SiC power MOSFETs by implementing AlON high-k gate dielectrics","authors":"T. Hosoi, Shuji Azumo, Yusaku Kashiwagi, S. Hosaka, R. Nakamura, Shuhei Mitani, Y. Nakano, H. Asahara, Takashi Nakamura, Tsunenobu Kimoto, T. Shimura, Heiji Watanabe","doi":"10.1109/IEDM.2012.6478998","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6478998","url":null,"abstract":"We have developed AlON high-k gate dielectric technology that can be easily implemented into both planar and trench SiC-based MOSFETs. On the basis of electrical characterization and numerical simulation, the thickness ratio of the AlON layer to the SiO2 interlayer and nitrogen content in AlON film were carefully optimized to enhance device performance and reliability.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"240 1","pages":"7.4.1-7.4.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80463782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479043
Yuchao Liu, Ru Huang, Runsheng Wang, Jiaojiao Ou, Yangyuan Wang
In this paper, a new design optimization method is put forward, which can significantly improve the analog/RF performance of MG devices with impacts of parasitics and process variations considered. The gate-all-around silicon nanowire transistors (SNWTs) are taken as example, the analog/RF performance, such as cutoff frequency (fT), transconductance efficiency (gm/Id), intrinsic gain (gm/gds) and comprehensive figure of merit (FOM) are optimized by utilizing the proposed method. Through design optimization, higher fT of SNWTs can be obtained compared with planar FETs, which can approach the ITRS projection, manifesting the promising potential of SNWTs for high frequency circuit applications. The optimal regions of independent variable vector (X) of SNWTs are given, which can provide useful guidelines for MG device-based circuit design.
{"title":"Improving analog/RF performance of multi-gate devices through multi-dimensional design optimization with awareness of variations and parasitics","authors":"Yuchao Liu, Ru Huang, Runsheng Wang, Jiaojiao Ou, Yangyuan Wang","doi":"10.1109/IEDM.2012.6479043","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479043","url":null,"abstract":"In this paper, a new design optimization method is put forward, which can significantly improve the analog/RF performance of MG devices with impacts of parasitics and process variations considered. The gate-all-around silicon nanowire transistors (SNWTs) are taken as example, the analog/RF performance, such as cutoff frequency (fT), transconductance efficiency (gm/Id), intrinsic gain (gm/gds) and comprehensive figure of merit (FOM) are optimized by utilizing the proposed method. Through design optimization, higher fT of SNWTs can be obtained compared with planar FETs, which can approach the ITRS projection, manifesting the promising potential of SNWTs for high frequency circuit applications. The optimal regions of independent variable vector (X) of SNWTs are given, which can provide useful guidelines for MG device-based circuit design.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"21 1","pages":"14.5.1-14.5.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90157161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479147
Dong-il Moon, Sung-Jin Choi, Jee-Yeon Kim, Seungwon Ko, Moon-Seok Kim, J. Oh, G. Lee, Min-Ho Kang, Young-Su Kim, J. Kim, Yang‐Kyu Choi
A BJT named `biristor', a term derived from `bi-stable resistor', is demonstrated for 4F2 high speed volatile memory applications. For a floating body cell, a gate-less vertical silicon pillar, which is an n-p-n BJT with an open-base, is employed, whereas for its control device, a MOSFET composed of a vertical silicon pillar surrounded by a gate is utilized. A 4F2 memory cell array is realized by the unidirectional operation of a vertical two-terminal biristor, which consists of a cross-bar array. Due to the nature of the gate-less structure, the biristor cell shows excellent endurance of up to 1016.
{"title":"Highly endurable floating body cell memory: Vertical biristor","authors":"Dong-il Moon, Sung-Jin Choi, Jee-Yeon Kim, Seungwon Ko, Moon-Seok Kim, J. Oh, G. Lee, Min-Ho Kang, Young-Su Kim, J. Kim, Yang‐Kyu Choi","doi":"10.1109/IEDM.2012.6479147","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479147","url":null,"abstract":"A BJT named `biristor', a term derived from `bi-stable resistor', is demonstrated for 4F2 high speed volatile memory applications. For a floating body cell, a gate-less vertical silicon pillar, which is an n-p-n BJT with an open-base, is employed, whereas for its control device, a MOSFET composed of a vertical silicon pillar surrounded by a gate is utilized. A 4F2 memory cell array is realized by the unidirectional operation of a vertical two-terminal biristor, which consists of a cross-bar array. Due to the nature of the gate-less structure, the biristor cell shows excellent endurance of up to 1016.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"42 1","pages":"31.7.1-31.7.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76507632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479024
S. Parui, K. Rana, T. Banerjee
Here we discuss a non-destructive technique that characterizes spin and charge transport at the nanometer scale, across buried layers and interfaces, in magnetic memory elements as used in spin transfer torque based Magnetic Random Access Memory (STT-MRAM). While probing in the current-perpendicular-to-plane direction, this method enables quantification of essential spin transport parameters as length and time scale, spin polarization in buried layers and interfaces, visualization of domain wall evolution across buried interfaces, besides investigating the homogeneity of transport, at the nanoscale, in spintronics devices.
{"title":"Spin transport in metal and oxide devices at the nanoscale","authors":"S. Parui, K. Rana, T. Banerjee","doi":"10.1109/IEDM.2012.6479024","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479024","url":null,"abstract":"Here we discuss a non-destructive technique that characterizes spin and charge transport at the nanometer scale, across buried layers and interfaces, in magnetic memory elements as used in spin transfer torque based Magnetic Random Access Memory (STT-MRAM). While probing in the current-perpendicular-to-plane direction, this method enables quantification of essential spin transport parameters as length and time scale, spin polarization in buried layers and interfaces, visualization of domain wall evolution across buried interfaces, besides investigating the homogeneity of transport, at the nanoscale, in spintronics devices.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"135 1","pages":"11.4.1-11.4.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79543218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479077
L. Larcher, A. Padovani, O. Pirrotta, L. Vandelli, G. Bersuker
In this paper we investigate the physical mechanisms governing operations in HfOx RRAM devices. Forming set and reset processes are studied using a model including power dissipation associated with the charge transport, and the corresponding temperature increase, which assists ion diffusion.
{"title":"Microscopic understanding and modeling of HfO2 RRAM device physics","authors":"L. Larcher, A. Padovani, O. Pirrotta, L. Vandelli, G. Bersuker","doi":"10.1109/IEDM.2012.6479077","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479077","url":null,"abstract":"In this paper we investigate the physical mechanisms governing operations in HfOx RRAM devices. Forming set and reset processes are studied using a model including power dissipation associated with the charge transport, and the corresponding temperature increase, which assists ion diffusion.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"441 1","pages":"20.1.1-20.1.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79638338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479160
Yu-Chung Lien, J. Shieh, Wen-Hsien Huang, Wei-Shang Hsieh, Cheng-Hui Tu, Chieh-An Wang, C. Shen, T. Chou, Min-Cheng Chen, J. Y. Huang, C. Pan, Y. Lai, C. Hu, Fu-Liang Yang
For the first time, a sequentially processed 3D hybrid chip is demonstrated by stacking low-temperature (LT) Ferroelectric-like (FE-like) metal-oxide nonvolatile memory (NVM) and CMOS. The high-mobility (333 and 113 cm2/V-s) and low-subthreshold swing (97 and 112 mV/decade) N/P-type thin film transistors (TFTs) construct stacked inverters showing sharp transfer characteristic as the fundamental element of CMOS array and stacked 3D NVMs. The sequential layered integration is enabled by cutting-edge low thermal-budget plasma/laser processes and self-assembled FE-like metal-oxide materials. The implementation of sub-400°C new-type metal-ion (Eu+3)-mediated atomic-polar-structured (Eu+3-APS) dielectric realizes stackable FE-like NVMs with program speed of 100 nanosecond, toward future 3D layered CMOS with giant high-speed data-storage application era.
{"title":"3D Ferroelectric-like NVM/CMOS hybrid chip by sub-400 °C sequential layered integration","authors":"Yu-Chung Lien, J. Shieh, Wen-Hsien Huang, Wei-Shang Hsieh, Cheng-Hui Tu, Chieh-An Wang, C. Shen, T. Chou, Min-Cheng Chen, J. Y. Huang, C. Pan, Y. Lai, C. Hu, Fu-Liang Yang","doi":"10.1109/IEDM.2012.6479160","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479160","url":null,"abstract":"For the first time, a sequentially processed 3D hybrid chip is demonstrated by stacking low-temperature (LT) Ferroelectric-like (FE-like) metal-oxide nonvolatile memory (NVM) and CMOS. The high-mobility (333 and 113 cm2/V-s) and low-subthreshold swing (97 and 112 mV/decade) N/P-type thin film transistors (TFTs) construct stacked inverters showing sharp transfer characteristic as the fundamental element of CMOS array and stacked 3D NVMs. The sequential layered integration is enabled by cutting-edge low thermal-budget plasma/laser processes and self-assembled FE-like metal-oxide materials. The implementation of sub-400°C new-type metal-ion (Eu+3)-mediated atomic-polar-structured (Eu+3-APS) dielectric realizes stackable FE-like NVMs with program speed of 100 nanosecond, toward future 3D layered CMOS with giant high-speed data-storage application era.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"18 1","pages":"33.6.1-33.6.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77977677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479057
M. Luisier
In this paper, the electronic and thermal properties of ultra-scaled nanowire transistors are investigated using a single, atomistic, quantum transport simulator based on the Non-equilibrium Green's Function (NEGF) formalism as well as the tight-binding and valence-force-field methods to accurately describe the electron and phonon population, respectively. Although the length of the considered device structures does not exceed a few nanometers, dissipative scattering mechanisms such as electron-phonon and anharmonic phonon-phonon scattering still play an important role and should therefore be fully taken into account by the modeling approach. It will be shown here that these two effects strongly affect the performance of nanowire transistors, either by decreasing (backscattering) or increasing (opening of additional propagation channels) the electrical and thermal currents flowing through them.
{"title":"Towards atomistic simulations of the electro-thermal properties of nanowire transistors","authors":"M. Luisier","doi":"10.1109/IEDM.2012.6479057","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479057","url":null,"abstract":"In this paper, the electronic and thermal properties of ultra-scaled nanowire transistors are investigated using a single, atomistic, quantum transport simulator based on the Non-equilibrium Green's Function (NEGF) formalism as well as the tight-binding and valence-force-field methods to accurately describe the electron and phonon population, respectively. Although the length of the considered device structures does not exceed a few nanometers, dissipative scattering mechanisms such as electron-phonon and anharmonic phonon-phonon scattering still play an important role and should therefore be fully taken into account by the modeling approach. It will be shown here that these two effects strongly affect the performance of nanowire transistors, either by decreasing (backscattering) or increasing (opening of additional propagation channels) the electrical and thermal currents flowing through them.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"43 1","pages":"17.1.1-17.1.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74742903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6478996
T. Morita, S. Ujita, H. Umeda, Y. Kinoshita, S. Tamura, Y. Anda, T. Ueda, T. Tanaka
In this paper, we present a novel GaN-based normally-off transistor with an integrated Si Schottky barrier diode (SBD) for low voltage DC-DC converters. The integrated SBD is formed by the Si substrate for the epitaxial growth of AlGaN/GaN hetero-structure, which is connected to the normally-off GaN Gate Injection Transistor (GIT) over it with via-holes. The diode can flow the reverse current in the conversion operation with lower forward voltage than that of the lateral GaN transistor enabling lower operating loss. A DC-DC converter from 12V down to 1.3V using the integrated devices with the reduced gate length down to 0.5μm exhibits a high peak efficiency of 89% at 2MHz demonstrating the promising potential of GaN devices for the application.
{"title":"GaN Gate Injection Transistor with integrated Si Schottky barrier diode for highly efficient DC-DC converters","authors":"T. Morita, S. Ujita, H. Umeda, Y. Kinoshita, S. Tamura, Y. Anda, T. Ueda, T. Tanaka","doi":"10.1109/IEDM.2012.6478996","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6478996","url":null,"abstract":"In this paper, we present a novel GaN-based normally-off transistor with an integrated Si Schottky barrier diode (SBD) for low voltage DC-DC converters. The integrated SBD is formed by the Si substrate for the epitaxial growth of AlGaN/GaN hetero-structure, which is connected to the normally-off GaN Gate Injection Transistor (GIT) over it with via-holes. The diode can flow the reverse current in the conversion operation with lower forward voltage than that of the lateral GaN transistor enabling lower operating loss. A DC-DC converter from 12V down to 1.3V using the integrated devices with the reduced gate length down to 0.5μm exhibits a high peak efficiency of 89% at 2MHz demonstrating the promising potential of GaN devices for the application.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"28 1","pages":"7.2.1-7.2.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83084712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：