Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479065
A. Nainani, S. Gupta, V. Moroz, Munkang Choi, Y. Kim, Y. Cho, J. Gelatos, T. Mandekar, A. Brand, E. Ping, M. Abraham, K. Schuegraf
S/D epitaxy remains an effective source of strain engineering for both aggressively and conservatively scaled FinFETs. Not merging the S/D epitaxy between adjacent fins and recess etch into the fin before S/D epitaxy is recommended for maximizing the gain. With high active P concentration Si:C becomes an effective stressor for NMOS. Contact and gate metal fills provide new knobs for engineering strain in FinFET devices for the 22nm node and remain effective with conservative scaling of contact / gate CD only.
{"title":"Is strain engineering scalable in FinFET era?: Teaching the old dog some new tricks","authors":"A. Nainani, S. Gupta, V. Moroz, Munkang Choi, Y. Kim, Y. Cho, J. Gelatos, T. Mandekar, A. Brand, E. Ping, M. Abraham, K. Schuegraf","doi":"10.1109/IEDM.2012.6479065","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479065","url":null,"abstract":"S/D epitaxy remains an effective source of strain engineering for both aggressively and conservatively scaled FinFETs. Not merging the S/D epitaxy between adjacent fins and recess etch into the fin before S/D epitaxy is recommended for maximizing the gain. With high active P concentration Si:C becomes an effective stressor for NMOS. Contact and gate metal fills provide new knobs for engineering strain in FinFET devices for the 22nm node and remain effective with conservative scaling of contact / gate CD only.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"13 1","pages":"18.3.1-18.3.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83380345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6478969
Chia-Hong Jan, U. Bhattacharya, R. Brain, S. Choi, G. Curello, G. Gupta, Walid M. Hafez, M. Jang, M. Kang, K. Komeyli, T. Leo, N. Nidhi, L. Pan, Park Joodong, K. Phoa, Arifur Rahman, C. Staus, H. Tashiro, Tsai Curtis, P. Vandervoorn, Laurence T. Yang, J. Yeh, P. Bai
A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time. Low standby power and high voltage transistors exploiting the superior short channel control, <; 65mV/dec subthreshold slope and <;40mV DIBL, of the Tri-Gate architecture have been fabricated concurrently with high speed logic transistors in a single SoC chip to achieve industry leading drive currents at record low leakage levels. NMOS/PMOS Idsat=0.41/0.37mA/um at 30pA/um Ioff, 0.75V, were used to build a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages. This technology offers mix-and-match flexibility of transistor types, high-density interconnect stacks, and RF/mixed-signal features for leadership in mobile, handheld, wireless and embedded SoC products.
{"title":"A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications","authors":"Chia-Hong Jan, U. Bhattacharya, R. Brain, S. Choi, G. Curello, G. Gupta, Walid M. Hafez, M. Jang, M. Kang, K. Komeyli, T. Leo, N. Nidhi, L. Pan, Park Joodong, K. Phoa, Arifur Rahman, C. Staus, H. Tashiro, Tsai Curtis, P. Vandervoorn, Laurence T. Yang, J. Yeh, P. Bai","doi":"10.1109/IEDM.2012.6478969","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6478969","url":null,"abstract":"A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time. Low standby power and high voltage transistors exploiting the superior short channel control, <; 65mV/dec subthreshold slope and <;40mV DIBL, of the Tri-Gate architecture have been fabricated concurrently with high speed logic transistors in a single SoC chip to achieve industry leading drive currents at record low leakage levels. NMOS/PMOS Idsat=0.41/0.37mA/um at 30pA/um Ioff, 0.75V, were used to build a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages. This technology offers mix-and-match flexibility of transistor types, high-density interconnect stacks, and RF/mixed-signal features for leadership in mobile, handheld, wireless and embedded SoC products.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"32 1","pages":"3.1.1-3.1.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74409795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479071
H. Miki, N. Tega, M. Yamaoka, D. Frank, A. Bansal, M. Kobayashi, K. Cheng, C. D'Emic, Z. Ren, S. Wu, J. Yau, Y. Zhu, M. Guillorn, D. Park, W. Haensch, E. Leobandung, K. Torii
This paper presents results of statistical analysis of RTN in highly scaled HKMG FETs. A robust algorithm to extract multiple-trap RTN is proposed and applied to show that RTN can cause serious variation even when HKMG and undoped channel are introduced. We further focus on hysteretic behavior caused by RTN with time constants much longer than the circuit timescale. This reveals that RTN also induces novel instabilities such as short-term BTI and logic delay uncertainty. Extraction of RTN in SRAM arrays is also presented to discuss its impact on operational stability.
{"title":"Statistical measurement of random telegraph noise and its impact in scaled-down high-κ/metal-gate MOSFETs","authors":"H. Miki, N. Tega, M. Yamaoka, D. Frank, A. Bansal, M. Kobayashi, K. Cheng, C. D'Emic, Z. Ren, S. Wu, J. Yau, Y. Zhu, M. Guillorn, D. Park, W. Haensch, E. Leobandung, K. Torii","doi":"10.1109/IEDM.2012.6479071","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479071","url":null,"abstract":"This paper presents results of statistical analysis of RTN in highly scaled HKMG FETs. A robust algorithm to extract multiple-trap RTN is proposed and applied to show that RTN can cause serious variation even when HKMG and undoped channel are introduced. We further focus on hysteretic behavior caused by RTN with time constants much longer than the circuit timescale. This reveals that RTN also induces novel instabilities such as short-term BTI and logic delay uncertainty. Extraction of RTN in SRAM arrays is also presented to discuss its impact on operational stability.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"16 1","pages":"19.1.1-19.1.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78454803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479084
Seong-Geon Park, M. Yang, H. Ju, D. Seong, Jung Moo Lee, Eunmi Kim, Seungjae Jung, Lijie Zhang, Yoocheol Shin, I. Baek, Jungdal Choi, Ho-Kyu Kang, C. Chung
A non-linear RRAM cell with sub-1μA ultralow operating current has been successfully fabricated for high density vertical ReRAM (VRRAM) applications. A uniform and reproducible low power resistive switching was achieved by engineering transition metal oxides and imposing thin insulating layer as a tunnel barrier. The non-linear I-V characteristics ensure the possible incorporation of RRAM cell into high density cross-type array structure including VRRAM. By varying the current compliance, a multi level switching behavior was obtained. Moreover, excellent endurance of more than 107 cycles without read disturbance for up to 104 seconds was demonstrated.
{"title":"A non-linear ReRAM cell with sub-1μA ultralow operating current for high density vertical resistive memory (VRRAM)","authors":"Seong-Geon Park, M. Yang, H. Ju, D. Seong, Jung Moo Lee, Eunmi Kim, Seungjae Jung, Lijie Zhang, Yoocheol Shin, I. Baek, Jungdal Choi, Ho-Kyu Kang, C. Chung","doi":"10.1109/IEDM.2012.6479084","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479084","url":null,"abstract":"A non-linear RRAM cell with sub-1μA ultralow operating current has been successfully fabricated for high density vertical ReRAM (VRRAM) applications. A uniform and reproducible low power resistive switching was achieved by engineering transition metal oxides and imposing thin insulating layer as a tunnel barrier. The non-linear I-V characteristics ensure the possible incorporation of RRAM cell into high density cross-type array structure including VRRAM. By varying the current compliance, a multi level switching behavior was obtained. Moreover, excellent endurance of more than 107 cycles without read disturbance for up to 104 seconds was demonstrated.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"100 1","pages":"20.8.1-20.8.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78735422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479156
K. Lee, Y. Ohara, K. Kiyoyama, S. Konno, Y. Sato, S. Watanabe, A. Yabata, T. Kamada, J. Bea, H. Hashimoto, M. Murugesan, T. Fukushima, T. Tanaka, M. Koyanagi
We demonstrate the chip-based 3D heterogeneous integration technology for realizing highly parallel 3D-stacked image sensor. Three kinds of chips, CMOS image sensor chip, analog circuit chip, and ADC array chip, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking. The fundamental characteristics are evaluated in the fabricated prototype 3D-stacked image sensor.
{"title":"Characterization of chip-level hetero-integration technology for high-speed, highly parallel 3D-stacked image processing system","authors":"K. Lee, Y. Ohara, K. Kiyoyama, S. Konno, Y. Sato, S. Watanabe, A. Yabata, T. Kamada, J. Bea, H. Hashimoto, M. Murugesan, T. Fukushima, T. Tanaka, M. Koyanagi","doi":"10.1109/IEDM.2012.6479156","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479156","url":null,"abstract":"We demonstrate the chip-based 3D heterogeneous integration technology for realizing highly parallel 3D-stacked image sensor. Three kinds of chips, CMOS image sensor chip, analog circuit chip, and ADC array chip, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking. The fundamental characteristics are evaluated in the fabricated prototype 3D-stacked image sensor.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"40 1","pages":"33.2.1-33.2.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74432780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6478973
H. Fukutome, K. Cheon, J. P. Kim, J. Kim, J. Lee, S. Cha, U. Roh, S. Kwon, D. Sohn, S. Maeda
Extensibility of the high-k/metal gate (HK/MG) planar devices beyond 20nm node with high performance, low power consumption, less layout dependence and suppressed local variability were comprehensively studied among gate first (GF) and gate-last (GL) schemes for the first time. We demonstrated the N-/PFET drive current (Idsat) of 1.45/1.3 mA/μm with the off-leakage current (Ioff) of 100 nA/μm for the Vdd of 0.9V by scaling down the gate width (Wg) of GL-HK/MG devices to 60nm. Key layout dependence of the PFET with embedded SiGe source/drain (eSiGe) was improved by eSiGe interface engineering and scaling down the Wg with keeping the multiple threshold voltage (Vt) and improving the body-bias effect (BE). Moreover, we demonstrated reduction in the capacitance by conventional method even for such a scaled planar device. Finally, we achieved the sufficiently low Vt mismatch, which is required to reduce the design corner, by eSiGe interface engineering and reduction of interface states in the gate stack (Dit).
{"title":"Comprehensive extensibility of 20nm low power/high performance technology platform featuring scalable high-k/metal gate planar transistors with reduced design corner","authors":"H. Fukutome, K. Cheon, J. P. Kim, J. Kim, J. Lee, S. Cha, U. Roh, S. Kwon, D. Sohn, S. Maeda","doi":"10.1109/IEDM.2012.6478973","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6478973","url":null,"abstract":"Extensibility of the high-k/metal gate (HK/MG) planar devices beyond 20nm node with high performance, low power consumption, less layout dependence and suppressed local variability were comprehensively studied among gate first (GF) and gate-last (GL) schemes for the first time. We demonstrated the N-/PFET drive current (Idsat) of 1.45/1.3 mA/μm with the off-leakage current (Ioff) of 100 nA/μm for the Vdd of 0.9V by scaling down the gate width (Wg) of GL-HK/MG devices to 60nm. Key layout dependence of the PFET with embedded SiGe source/drain (eSiGe) was improved by eSiGe interface engineering and scaling down the Wg with keeping the multiple threshold voltage (Vt) and improving the body-bias effect (BE). Moreover, we demonstrated reduction in the capacitance by conventional method even for such a scaled planar device. Finally, we achieved the sufficiently low Vt mismatch, which is required to reduce the design corner, by eSiGe interface engineering and reduction of interface states in the gate stack (Dit).","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"1 1","pages":"3.5.1-3.5.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88704900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479142
N. Ciocchini, M. Cassinerio, D. Fugazza, D. Ielmini
Crystallization kinetics in phase change memory (PCM) control the device switching and retention times, thus an accurate characterization and prediction of crystallization speed is essential. We measured crystallization times in PCM devices in both the thermal crystallization regime at relatively low temperature (T <; 250 °C) and in pulsed-induced crystallization (set regime). By using a filamentary model for set transition, we evidence a non-Arrhenius temperature dependence of crystallization. This finding provides a key new element for the modeling of phase change materials and devices.
{"title":"Non-Arrhenius pulse-induced crystallization in phase change memories","authors":"N. Ciocchini, M. Cassinerio, D. Fugazza, D. Ielmini","doi":"10.1109/IEDM.2012.6479142","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479142","url":null,"abstract":"Crystallization kinetics in phase change memory (PCM) control the device switching and retention times, thus an accurate characterization and prediction of crystallization speed is essential. We measured crystallization times in PCM devices in both the thermal crystallization regime at relatively low temperature (T <; 250 °C) and in pulsed-induced crystallization (set regime). By using a filamentary model for set transition, we evidence a non-Arrhenius temperature dependence of crystallization. This finding provides a key new element for the modeling of phase change materials and devices.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"68 2 1","pages":"31.2.1-31.2.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87765572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479104
T. Matsumoto, K. Kobayashi, H. Onodera
Statistical nature of RTN-induced delay fluctuation is described by measuring 2,520 ROs fabricated in a commercial 40 nm CMOS technology. Small number of samples have a large RTN-induced delay fluctuation. RTN-induced delay fluctuation becomes as much as 10.4% of nominal oscillation frequency under low supply voltage (0.65V). By slightly increasing the transistor size, more than 50% reduction of frequency uncertainty can be achieved under 0.75V operation. The impact of the parameters that can be changed by circuit designers is clarified in view of RTN-induced CMOS logic delay uncertainty.
{"title":"Impact of random telegraph noise on CMOS logic delay uncertainty under low voltage operation","authors":"T. Matsumoto, K. Kobayashi, H. Onodera","doi":"10.1109/IEDM.2012.6479104","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479104","url":null,"abstract":"Statistical nature of RTN-induced delay fluctuation is described by measuring 2,520 ROs fabricated in a commercial 40 nm CMOS technology. Small number of samples have a large RTN-induced delay fluctuation. RTN-induced delay fluctuation becomes as much as 10.4% of nominal oscillation frequency under low supply voltage (0.65V). By slightly increasing the transistor size, more than 50% reduction of frequency uncertainty can be achieved under 0.75V operation. The impact of the parameters that can be changed by circuit designers is clarified in view of RTN-induced CMOS logic delay uncertainty.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"1 1","pages":"25.6.1-25.6.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90852339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479114
A. Inoue, R. Kato, A. Yamada, T. Yokogawa
A high current density over 1000 A/cm2 operation in a small chip size m-plane GaN-LED has been successfully demonstrated. The m-plane GaN-LED with a chip size 450 × 450 μm2 has emitted 1353 mW in a light output power and 39.2% in an external quantum efficiency (EQE) at 1000 A/cm2 (1134 mA). The m-plane GaN-LED has showed asymmetric radiation characteristics. The radiation patterns are controlled by the surface of LED packages, the height of the LED chips, and the striped texture on the top m-plane surface.
在小芯片尺寸的m平面GaN-LED中成功地实现了超过1000 A/cm2的高电流密度。芯片尺寸为450 × 450 μm2的m平面GaN-LED在1000 a /cm2 (1134 mA)时的光输出功率为1353 mW，外部量子效率(EQE)为39.2%。m平面GaN-LED具有非对称辐射特性。辐射模式由LED封装的表面、LED芯片的高度和顶部m平面表面的条纹纹理控制。
{"title":"Extremely high current density over 1000 A/cm2 operation in m-plane GaN small size LEDs with low efficiency droop and method for controlling radiation pattern and polarization","authors":"A. Inoue, R. Kato, A. Yamada, T. Yokogawa","doi":"10.1109/IEDM.2012.6479114","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479114","url":null,"abstract":"A high current density over 1000 A/cm2 operation in a small chip size m-plane GaN-LED has been successfully demonstrated. The m-plane GaN-LED with a chip size 450 × 450 μm2 has emitted 1353 mW in a light output power and 39.2% in an external quantum efficiency (EQE) at 1000 A/cm2 (1134 mA). The m-plane GaN-LED has showed asymmetric radiation characteristics. The radiation patterns are controlled by the surface of LED packages, the height of the LED chips, and the striped texture on the top m-plane surface.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"52 1","pages":"27.3.1-27.3.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90912776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479145
E. Vianello, G. Molas, F. Longnos, P. Blaise, E. Souchier, C. Cagli, G. Palma, J. Guy, M. Bernard, M. Reyboz, G. Rodriguez, A. Roule, C. Carabasse, V. Delaye, V. Jousseaume, S. Maitrejean, G. Reimbold, B. De Salvo, F. Dahmani, P. Verrier, D. Bretegnier, J. Liebault
In this work, for the first time at our knowledge, the improvement of chalcogenide-based CBRAM performance and reliability by Sb doping of the GeS2 electrolyte is presented. An original analysis, based on in-depth physico-chemical characterization, device electrical measurements, empirical model and first principle calculations, is shown. We argue that optimized ~10% Sb doping in the GeS2 electrolyte allows to achieve SET speed of 30ns at 2.2V (i.e. 0.66pJ SET programming power), while assuring 10 years data retention at 125°C, >105 cycling and high robustness to Sn-Pb soldering profile. Finally, the improved thermal stability of the filament in the GeS2-Sb matrix is clearly elucidated by means of molecular dynamics calculations.
{"title":"Sb-doped GeS2 as performance and reliability booster in Conductive Bridge RAM","authors":"E. Vianello, G. Molas, F. Longnos, P. Blaise, E. Souchier, C. Cagli, G. Palma, J. Guy, M. Bernard, M. Reyboz, G. Rodriguez, A. Roule, C. Carabasse, V. Delaye, V. Jousseaume, S. Maitrejean, G. Reimbold, B. De Salvo, F. Dahmani, P. Verrier, D. Bretegnier, J. Liebault","doi":"10.1109/IEDM.2012.6479145","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479145","url":null,"abstract":"In this work, for the first time at our knowledge, the improvement of chalcogenide-based CBRAM performance and reliability by Sb doping of the GeS2 electrolyte is presented. An original analysis, based on in-depth physico-chemical characterization, device electrical measurements, empirical model and first principle calculations, is shown. We argue that optimized ~10% Sb doping in the GeS2 electrolyte allows to achieve SET speed of 30ns at 2.2V (i.e. 0.66pJ SET programming power), while assuring 10 years data retention at 125°C, >105 cycling and high robustness to Sn-Pb soldering profile. Finally, the improved thermal stability of the filament in the GeS2-Sb matrix is clearly elucidated by means of molecular dynamics calculations.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"48 1","pages":"31.5.1-31.5.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91044481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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