Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479049
A. Ansari, V. Gokhale, J. Roberts, M. Rais-Zadeh
A platform for intimate integration of high-frequency gallium nitride (GaN) micromechanical resonators and AlGaN/GaN high electron mobility transistors (HEMTs) is reported. For the first time, cascade of a two-port GaN bulk acoustic resonator and AlGaN/GaN HEMT was co-fabricated on a silicon substrate. A high quality factor (Q) of 7413 is reported for a GaN contour-mode resonator at the resonance frequency of 119.8 MHz. More than 30 dB of signal tuning was achieved by using integrated HEMT for signal readout and amplification at the resonator output.
{"title":"Monolithic integration of GaN-based micromechanical resonators and HEMTs for timing applications","authors":"A. Ansari, V. Gokhale, J. Roberts, M. Rais-Zadeh","doi":"10.1109/IEDM.2012.6479049","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479049","url":null,"abstract":"A platform for intimate integration of high-frequency gallium nitride (GaN) micromechanical resonators and AlGaN/GaN high electron mobility transistors (HEMTs) is reported. For the first time, cascade of a two-port GaN bulk acoustic resonator and AlGaN/GaN HEMT was co-fabricated on a silicon substrate. A high quality factor (Q) of 7413 is reported for a GaN contour-mode resonator at the resonance frequency of 119.8 MHz. More than 30 dB of signal tuning was achieved by using integrated HEMT for signal readout and amplification at the resonator output.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"4 1","pages":"15.5.1-15.5.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85560239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479111
Y. Hsiao, H. Lue, Wei-Chen Chen, Chih-Ping Chen, Kuo-Ping Chang, Y. Shih, B. Tsui, Chih-Yuan Lu
The variability of the poly silicon thin film transistor (TFT) in 3D NAND Flash is a major concern. In this work, we have fabricated and characterized a 37.5nm half pitch 3D Vertical Gate (VG) NAND Flash, and successfully modeled the random grain boundary effect using TCAD simulation. In our model, the grain boundary creates interface states, resulting in large local band bending and a surface potential barrier. The gate-induced grain barrier lowering (GIGBL) and drain-induced grain barrier lowering (DIGBL) effects are the major physical mechanisms that affect the subthreshold behavior. By means of modeling, the impact of bit line (BL) and word line (WL) critical dimensions (CD) of the double-gate TFT device is studied extensively, where we find that narrower BL and larger WL CD's are the most critical parameters that provide tight Vt distribution and good memory window. For the first time, we have discovered an asymmetry of reverse read (RR) and forward read (FR) of the TFT device. The physical mechanism can be well explained by the DIGBL. With accurate modeling, the asymmetry of RR and FR can be used to determine the GB trap lateral location and interface trap density.
{"title":"Modeling the variability caused by random grain boundary and trap-location induced asymmetrical read behavior for a tight-pitch vertical gate 3D NAND Flash memory using double-gate thin-film transistor (TFT) device","authors":"Y. Hsiao, H. Lue, Wei-Chen Chen, Chih-Ping Chen, Kuo-Ping Chang, Y. Shih, B. Tsui, Chih-Yuan Lu","doi":"10.1109/IEDM.2012.6479111","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479111","url":null,"abstract":"The variability of the poly silicon thin film transistor (TFT) in 3D NAND Flash is a major concern. In this work, we have fabricated and characterized a 37.5nm half pitch 3D Vertical Gate (VG) NAND Flash, and successfully modeled the random grain boundary effect using TCAD simulation. In our model, the grain boundary creates interface states, resulting in large local band bending and a surface potential barrier. The gate-induced grain barrier lowering (GIGBL) and drain-induced grain barrier lowering (DIGBL) effects are the major physical mechanisms that affect the subthreshold behavior. By means of modeling, the impact of bit line (BL) and word line (WL) critical dimensions (CD) of the double-gate TFT device is studied extensively, where we find that narrower BL and larger WL CD's are the most critical parameters that provide tight Vt distribution and good memory window. For the first time, we have discovered an asymmetry of reverse read (RR) and forward read (FR) of the TFT device. The physical mechanism can be well explained by the DIGBL. With accurate modeling, the asymmetry of RR and FR can be used to determine the GB trap lateral location and interface trap density.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"1 1","pages":"26.7.1-26.7.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90661399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479143
W. J. Wang, D. Loke, L. Law, L. P. Shi, R. Zhao, M. Li, L. L. Chen, H. Yang, Y. Yeo, A. Adeyeye, T. Chong, A. Lacaita
Phase-change memory (PCM) represents one of the best candidates for a “universal memory”. However, its slow SET speed, high RESET power, and high resistance drift present key challenges towards this ambition. Here, grain-engineered Ge2Sb2Te5 is exploited to control the crystallization kinetics, and electrical properties of PCM. We report 120 % higher SET speeds with respect to conventional scaling. Good stability (140°C), 30 % RESET power reduction, and 2X lower resistance drift were also achieved. A 4-state/2-bit multilevel cell was further demonstrated. This provides a route to making high-density PCM devices.
{"title":"Engineering grains of Ge2Sb2Te5 for realizing fast-speed, low-power, and low-drift phase-change memories with further multilevel capabilities","authors":"W. J. Wang, D. Loke, L. Law, L. P. Shi, R. Zhao, M. Li, L. L. Chen, H. Yang, Y. Yeo, A. Adeyeye, T. Chong, A. Lacaita","doi":"10.1109/IEDM.2012.6479143","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479143","url":null,"abstract":"Phase-change memory (PCM) represents one of the best candidates for a “universal memory”. However, its slow SET speed, high RESET power, and high resistance drift present key challenges towards this ambition. Here, grain-engineered Ge2Sb2Te5 is exploited to control the crystallization kinetics, and electrical properties of PCM. We report 120 % higher SET speeds with respect to conventional scaling. Good stability (140°C), 30 % RESET power reduction, and 2X lower resistance drift were also achieved. A 4-state/2-bit multilevel cell was further demonstrated. This provides a route to making high-density PCM devices.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"3 1","pages":"31.3.1-31.3.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91201403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479042
L. Clark, D. Zhao, T. Bakhishev, H. Ahn, E. Boling, M. Duane, K. Fujita, P. Gregory, T. Hoffmann, M. Hori, D. Kanai, D. Kidd, S. Lee, Y. Liu, J. Mitani, J. Nagayama, S. Pradhan, P. Ranade, R. Rogenmoser, L. Scudder, L. Shifren, Y. Torii, M. Wojko, Y. Asada, T. Ema, S. Thompson
65nm Deeply Depleted Channel (DDCTM) transistors have been fabricated with a halo-free, un-doped epitaxial channel and enable reduced threshold voltage (VT) variation, lower supply voltage (VCC), enhanced body effect and IEFF. Digital circuits made using this technology show benefits ranging from 47% power reduction to 38% frequency increase. Analog circuits exhibit 4x greater amplifier gain despite lower VDD, and current mirror mismatch (both global and local) shows 40% and 30% reduction for NMOS and PMOS, respectively.
{"title":"A highly integrated 65-nm SoC process with enhanced power/performance of digital and analog circuits","authors":"L. Clark, D. Zhao, T. Bakhishev, H. Ahn, E. Boling, M. Duane, K. Fujita, P. Gregory, T. Hoffmann, M. Hori, D. Kanai, D. Kidd, S. Lee, Y. Liu, J. Mitani, J. Nagayama, S. Pradhan, P. Ranade, R. Rogenmoser, L. Scudder, L. Shifren, Y. Torii, M. Wojko, Y. Asada, T. Ema, S. Thompson","doi":"10.1109/IEDM.2012.6479042","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479042","url":null,"abstract":"65nm Deeply Depleted Channel (DDCTM) transistors have been fabricated with a halo-free, un-doped epitaxial channel and enable reduced threshold voltage (VT) variation, lower supply voltage (VCC), enhanced body effect and IEFF. Digital circuits made using this technology show benefits ranging from 47% power reduction to 38% frequency increase. Analog circuits exhibit 4x greater amplifier gain despite lower VDD, and current mirror mismatch (both global and local) shows 40% and 30% reduction for NMOS and PMOS, respectively.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"24 1","pages":"14.4.1-14.4.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73453374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479011
Eun-seok Choi, Sung-Kye Park
Recently, we have suggested highly manufacturable and reliable 3D NAND flash cell called “SMArT”[1], which is intended to minimize both stack height and word line resistance. Because the storage node of this cell is charge trap nitride, its device characteristics were far different from conventional floating gate. In this paper, the key cell characteristics such as cell Vth distribution, disturbance, and reliability are compared with our FG cell of 2y node in chip level, and several future challenges for 3D era will be addressed.
{"title":"Device considerations for high density and highly reliable 3D NAND flash cell in near future","authors":"Eun-seok Choi, Sung-Kye Park","doi":"10.1109/IEDM.2012.6479011","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479011","url":null,"abstract":"Recently, we have suggested highly manufacturable and reliable 3D NAND flash cell called “SMArT”[1], which is intended to minimize both stack height and word line resistance. Because the storage node of this cell is charge trap nitride, its device characteristics were far different from conventional floating gate. In this paper, the key cell characteristics such as cell Vth distribution, disturbance, and reliability are compared with our FG cell of 2y node in chip level, and several future challenges for 3D era will be addressed.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"1 1","pages":"9.4.1-9.4.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88565439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a first comprehensive study of SET speed-disturb dilemma in RRAM using statistically-based prediction methodologies. A rapid ramped-voltage stress based on percolation model and power-law V-t dependence showed excellent agreement with the time-consuming constant-voltage stress, and was applied to evaluate current status of RRAM devices in the literature.
{"title":"RRAM SET speed-disturb dilemma and rapid statistical prediction methodology","authors":"Wun-Cheng Luo, Jen-Chieh Liu, Hsien-Tsung Feng, Yen-Chuan Lin, Jiun-Jia Huang, Kuan-Liang Lin, T. Hou","doi":"10.1109/IEDM.2012.6479012","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479012","url":null,"abstract":"This paper presents a first comprehensive study of SET speed-disturb dilemma in RRAM using statistically-based prediction methodologies. A rapid ramped-voltage stress based on percolation model and power-law V-t dependence showed excellent agreement with the time-consuming constant-voltage stress, and was applied to evaluate current status of RRAM devices in the literature.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"25 1","pages":"9.5.1-9.5.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89084641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479159
M. Nihei, A. Kawabata, T. Murakami, M. Sato, N. Yokoyama
This paper reports the tailoring thermal conductivity of novel dense vertical and horizontal graphene (DVHG) structures, which we previously discovered. By removing horizontal graphene layers, resulting in forming vertical graphene contacts to the electrode, we not only improved the thermal conductivity by a factor of 10 but also improved the electrical conductivity by a factor of 100. The pyrolytic graphite, grown at a higher temperature than the DVHG, showed a high thermal conductivity of 1426 W/mK by forming vertical graphene contacts. Although the DVHG showed poor thermal properties at this point, we found that the vertical graphene contact formation can be an important technology to realize high thermal conductivity for carbon-based thermal through-silicon-vias (TSV).
{"title":"Improved thermal conductivity by vertical graphene contact formation for thermal TSV","authors":"M. Nihei, A. Kawabata, T. Murakami, M. Sato, N. Yokoyama","doi":"10.1109/IEDM.2012.6479159","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479159","url":null,"abstract":"This paper reports the tailoring thermal conductivity of novel dense vertical and horizontal graphene (DVHG) structures, which we previously discovered. By removing horizontal graphene layers, resulting in forming vertical graphene contacts to the electrode, we not only improved the thermal conductivity by a factor of 10 but also improved the electrical conductivity by a factor of 100. The pyrolytic graphite, grown at a higher temperature than the DVHG, showed a high thermal conductivity of 1426 W/mK by forming vertical graphene contacts. Although the DVHG showed poor thermal properties at this point, we found that the vertical graphene contact formation can be an important technology to realize high thermal conductivity for carbon-based thermal through-silicon-vias (TSV).","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"42 1","pages":"33.5.1-33.5.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85085675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6478995
M. Treu, E. Vecino, M. Pippan, O. Haberlen, G. Curatola, G. Deboy, M. Kutschak, U. Kirchner
Silicon carbide (SiC) and latest gallium nitride (GaN) are two semiconductor materials which entered the power device arena which has been set up and still is being dominated by silicon based devices. The following paper will make a basic comparison of power devices out of these three base materials valid for medium voltage classes of some hundred to above 1000V. This paper will start with comparisons of common electrical figures of merit (FOM) and will focus less on the exact values but on the possible trends and current limits concerning the different materials. These findings will be brought in relation to application requirements.
{"title":"The role of silicon, silicon carbide and gallium nitride in power electronics","authors":"M. Treu, E. Vecino, M. Pippan, O. Haberlen, G. Curatola, G. Deboy, M. Kutschak, U. Kirchner","doi":"10.1109/IEDM.2012.6478995","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6478995","url":null,"abstract":"Silicon carbide (SiC) and latest gallium nitride (GaN) are two semiconductor materials which entered the power device arena which has been set up and still is being dominated by silicon based devices. The following paper will make a basic comparison of power devices out of these three base materials valid for medium voltage classes of some hundred to above 1000V. This paper will start with comparisons of common electrical figures of merit (FOM) and will focus less on the exact values but on the possible trends and current limits concerning the different materials. These findings will be brought in relation to application requirements.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"71 1","pages":"7.1.1-7.1.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85134061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479034
J. Bae, I. Hwang, Jongmin Shin, H. Kwon, C. Park, J. Ha, Jaewon Lee, Hyoji Choi, Jongseob Kim, Jong-bong Park, Jae-joon Oh, Jaikwang Shin, U. Chung, Jong-Ho Lee
Traps and trap-related effects in recessed-gate normally-off AlGaN/GaN-based MOSHEMT with SiO2 gate dielectric were characterized. Hysteresis in ID-VG was observed at elevated temperature (~120°C) due to the traps. To understand the traps, current transient in drain was investigated at given gate and drain pulses with different temperatures. Two groups of time constants were extracted: one is nearly constant and the other is decreased with temperature. Extracted activation energies from the drain current transients with temperature are 0.66 eV and 0.73 eV, respectively, for given gate and drain pulses. Using extracted exponential trap density profile from frequency dependent conductance method [4], we could understand C-V behavior with frequency. It was shown that traps inside AlGaN layer are a main cause for the decrease of capacitance at high frequency in inversion region. The pulsed I-V characteristics also show frequency dependence.
{"title":"Characterization of traps and trap-related effects in recessed-gate normally-off AlGaN/GaN-based MOSHEMT","authors":"J. Bae, I. Hwang, Jongmin Shin, H. Kwon, C. Park, J. Ha, Jaewon Lee, Hyoji Choi, Jongseob Kim, Jong-bong Park, Jae-joon Oh, Jaikwang Shin, U. Chung, Jong-Ho Lee","doi":"10.1109/IEDM.2012.6479034","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479034","url":null,"abstract":"Traps and trap-related effects in recessed-gate normally-off AlGaN/GaN-based MOSHEMT with SiO2 gate dielectric were characterized. Hysteresis in ID-VG was observed at elevated temperature (~120°C) due to the traps. To understand the traps, current transient in drain was investigated at given gate and drain pulses with different temperatures. Two groups of time constants were extracted: one is nearly constant and the other is decreased with temperature. Extracted activation energies from the drain current transients with temperature are 0.66 eV and 0.73 eV, respectively, for given gate and drain pulses. Using extracted exponential trap density profile from frequency dependent conductance method [4], we could understand C-V behavior with frequency. It was shown that traps inside AlGaN layer are a main cause for the decrease of capacitance at high frequency in inversion region. The pulsed I-V characteristics also show frequency dependence.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"24 1","pages":"13.2.1-13.2.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89330618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479110
P. Huang, X. Liu, W. H. Li, Y. X. Deng, B. Chen, Y. Lu, B. Gao, L. Zeng, K. Wei, G. Du, X. Zhang, J. Kang
A physical based analytic model of metal oxide based RRAM cell under DC and pulse operation modes is presented. In this model, the transport behaviors of oxygen vacancies and oxygen ions, metal conductivity, electron hopping and heat conduction and the parasitic capacitance and resistance effects are covered. The developed analytic model is verified and calibrated by measured data. Furthermore, we implement the analytic model in a 2×2 RRAM array simulation and investigate the reliability of RRAM array for the first time.
{"title":"A physical based analytic model of RRAM operation for circuit simulation","authors":"P. Huang, X. Liu, W. H. Li, Y. X. Deng, B. Chen, Y. Lu, B. Gao, L. Zeng, K. Wei, G. Du, X. Zhang, J. Kang","doi":"10.1109/IEDM.2012.6479110","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479110","url":null,"abstract":"A physical based analytic model of metal oxide based RRAM cell under DC and pulse operation modes is presented. In this model, the transport behaviors of oxygen vacancies and oxygen ions, metal conductivity, electron hopping and heat conduction and the parasitic capacitance and resistance effects are covered. The developed analytic model is verified and calibrated by measured data. Furthermore, we implement the analytic model in a 2×2 RRAM array simulation and investigate the reliability of RRAM array for the first time.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"78 1","pages":"26.6.1-26.6.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85575245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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