Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479049
A. Ansari, V. Gokhale, J. Roberts, M. Rais-Zadeh
A platform for intimate integration of high-frequency gallium nitride (GaN) micromechanical resonators and AlGaN/GaN high electron mobility transistors (HEMTs) is reported. For the first time, cascade of a two-port GaN bulk acoustic resonator and AlGaN/GaN HEMT was co-fabricated on a silicon substrate. A high quality factor (Q) of 7413 is reported for a GaN contour-mode resonator at the resonance frequency of 119.8 MHz. More than 30 dB of signal tuning was achieved by using integrated HEMT for signal readout and amplification at the resonator output.
{"title":"Monolithic integration of GaN-based micromechanical resonators and HEMTs for timing applications","authors":"A. Ansari, V. Gokhale, J. Roberts, M. Rais-Zadeh","doi":"10.1109/IEDM.2012.6479049","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479049","url":null,"abstract":"A platform for intimate integration of high-frequency gallium nitride (GaN) micromechanical resonators and AlGaN/GaN high electron mobility transistors (HEMTs) is reported. For the first time, cascade of a two-port GaN bulk acoustic resonator and AlGaN/GaN HEMT was co-fabricated on a silicon substrate. A high quality factor (Q) of 7413 is reported for a GaN contour-mode resonator at the resonance frequency of 119.8 MHz. More than 30 dB of signal tuning was achieved by using integrated HEMT for signal readout and amplification at the resonator output.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"4 1","pages":"15.5.1-15.5.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85560239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479111
Y. Hsiao, H. Lue, Wei-Chen Chen, Chih-Ping Chen, Kuo-Ping Chang, Y. Shih, B. Tsui, Chih-Yuan Lu
The variability of the poly silicon thin film transistor (TFT) in 3D NAND Flash is a major concern. In this work, we have fabricated and characterized a 37.5nm half pitch 3D Vertical Gate (VG) NAND Flash, and successfully modeled the random grain boundary effect using TCAD simulation. In our model, the grain boundary creates interface states, resulting in large local band bending and a surface potential barrier. The gate-induced grain barrier lowering (GIGBL) and drain-induced grain barrier lowering (DIGBL) effects are the major physical mechanisms that affect the subthreshold behavior. By means of modeling, the impact of bit line (BL) and word line (WL) critical dimensions (CD) of the double-gate TFT device is studied extensively, where we find that narrower BL and larger WL CD's are the most critical parameters that provide tight Vt distribution and good memory window. For the first time, we have discovered an asymmetry of reverse read (RR) and forward read (FR) of the TFT device. The physical mechanism can be well explained by the DIGBL. With accurate modeling, the asymmetry of RR and FR can be used to determine the GB trap lateral location and interface trap density.
{"title":"Modeling the variability caused by random grain boundary and trap-location induced asymmetrical read behavior for a tight-pitch vertical gate 3D NAND Flash memory using double-gate thin-film transistor (TFT) device","authors":"Y. Hsiao, H. Lue, Wei-Chen Chen, Chih-Ping Chen, Kuo-Ping Chang, Y. Shih, B. Tsui, Chih-Yuan Lu","doi":"10.1109/IEDM.2012.6479111","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479111","url":null,"abstract":"The variability of the poly silicon thin film transistor (TFT) in 3D NAND Flash is a major concern. In this work, we have fabricated and characterized a 37.5nm half pitch 3D Vertical Gate (VG) NAND Flash, and successfully modeled the random grain boundary effect using TCAD simulation. In our model, the grain boundary creates interface states, resulting in large local band bending and a surface potential barrier. The gate-induced grain barrier lowering (GIGBL) and drain-induced grain barrier lowering (DIGBL) effects are the major physical mechanisms that affect the subthreshold behavior. By means of modeling, the impact of bit line (BL) and word line (WL) critical dimensions (CD) of the double-gate TFT device is studied extensively, where we find that narrower BL and larger WL CD's are the most critical parameters that provide tight Vt distribution and good memory window. For the first time, we have discovered an asymmetry of reverse read (RR) and forward read (FR) of the TFT device. The physical mechanism can be well explained by the DIGBL. With accurate modeling, the asymmetry of RR and FR can be used to determine the GB trap lateral location and interface trap density.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"1 1","pages":"26.7.1-26.7.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90661399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479143
W. J. Wang, D. Loke, L. Law, L. P. Shi, R. Zhao, M. Li, L. L. Chen, H. Yang, Y. Yeo, A. Adeyeye, T. Chong, A. Lacaita
Phase-change memory (PCM) represents one of the best candidates for a “universal memory”. However, its slow SET speed, high RESET power, and high resistance drift present key challenges towards this ambition. Here, grain-engineered Ge2Sb2Te5 is exploited to control the crystallization kinetics, and electrical properties of PCM. We report 120 % higher SET speeds with respect to conventional scaling. Good stability (140°C), 30 % RESET power reduction, and 2X lower resistance drift were also achieved. A 4-state/2-bit multilevel cell was further demonstrated. This provides a route to making high-density PCM devices.
{"title":"Engineering grains of Ge2Sb2Te5 for realizing fast-speed, low-power, and low-drift phase-change memories with further multilevel capabilities","authors":"W. J. Wang, D. Loke, L. Law, L. P. Shi, R. Zhao, M. Li, L. L. Chen, H. Yang, Y. Yeo, A. Adeyeye, T. Chong, A. Lacaita","doi":"10.1109/IEDM.2012.6479143","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479143","url":null,"abstract":"Phase-change memory (PCM) represents one of the best candidates for a “universal memory”. However, its slow SET speed, high RESET power, and high resistance drift present key challenges towards this ambition. Here, grain-engineered Ge2Sb2Te5 is exploited to control the crystallization kinetics, and electrical properties of PCM. We report 120 % higher SET speeds with respect to conventional scaling. Good stability (140°C), 30 % RESET power reduction, and 2X lower resistance drift were also achieved. A 4-state/2-bit multilevel cell was further demonstrated. This provides a route to making high-density PCM devices.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"3 1","pages":"31.3.1-31.3.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91201403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479042
L. Clark, D. Zhao, T. Bakhishev, H. Ahn, E. Boling, M. Duane, K. Fujita, P. Gregory, T. Hoffmann, M. Hori, D. Kanai, D. Kidd, S. Lee, Y. Liu, J. Mitani, J. Nagayama, S. Pradhan, P. Ranade, R. Rogenmoser, L. Scudder, L. Shifren, Y. Torii, M. Wojko, Y. Asada, T. Ema, S. Thompson
65nm Deeply Depleted Channel (DDCTM) transistors have been fabricated with a halo-free, un-doped epitaxial channel and enable reduced threshold voltage (VT) variation, lower supply voltage (VCC), enhanced body effect and IEFF. Digital circuits made using this technology show benefits ranging from 47% power reduction to 38% frequency increase. Analog circuits exhibit 4x greater amplifier gain despite lower VDD, and current mirror mismatch (both global and local) shows 40% and 30% reduction for NMOS and PMOS, respectively.
{"title":"A highly integrated 65-nm SoC process with enhanced power/performance of digital and analog circuits","authors":"L. Clark, D. Zhao, T. Bakhishev, H. Ahn, E. Boling, M. Duane, K. Fujita, P. Gregory, T. Hoffmann, M. Hori, D. Kanai, D. Kidd, S. Lee, Y. Liu, J. Mitani, J. Nagayama, S. Pradhan, P. Ranade, R. Rogenmoser, L. Scudder, L. Shifren, Y. Torii, M. Wojko, Y. Asada, T. Ema, S. Thompson","doi":"10.1109/IEDM.2012.6479042","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479042","url":null,"abstract":"65nm Deeply Depleted Channel (DDCTM) transistors have been fabricated with a halo-free, un-doped epitaxial channel and enable reduced threshold voltage (VT) variation, lower supply voltage (VCC), enhanced body effect and IEFF. Digital circuits made using this technology show benefits ranging from 47% power reduction to 38% frequency increase. Analog circuits exhibit 4x greater amplifier gain despite lower VDD, and current mirror mismatch (both global and local) shows 40% and 30% reduction for NMOS and PMOS, respectively.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"24 1","pages":"14.4.1-14.4.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73453374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6478969
Chia-Hong Jan, U. Bhattacharya, R. Brain, S. Choi, G. Curello, G. Gupta, Walid M. Hafez, M. Jang, M. Kang, K. Komeyli, T. Leo, N. Nidhi, L. Pan, Park Joodong, K. Phoa, Arifur Rahman, C. Staus, H. Tashiro, Tsai Curtis, P. Vandervoorn, Laurence T. Yang, J. Yeh, P. Bai
A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time. Low standby power and high voltage transistors exploiting the superior short channel control, <; 65mV/dec subthreshold slope and <;40mV DIBL, of the Tri-Gate architecture have been fabricated concurrently with high speed logic transistors in a single SoC chip to achieve industry leading drive currents at record low leakage levels. NMOS/PMOS Idsat=0.41/0.37mA/um at 30pA/um Ioff, 0.75V, were used to build a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages. This technology offers mix-and-match flexibility of transistor types, high-density interconnect stacks, and RF/mixed-signal features for leadership in mobile, handheld, wireless and embedded SoC products.
{"title":"A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications","authors":"Chia-Hong Jan, U. Bhattacharya, R. Brain, S. Choi, G. Curello, G. Gupta, Walid M. Hafez, M. Jang, M. Kang, K. Komeyli, T. Leo, N. Nidhi, L. Pan, Park Joodong, K. Phoa, Arifur Rahman, C. Staus, H. Tashiro, Tsai Curtis, P. Vandervoorn, Laurence T. Yang, J. Yeh, P. Bai","doi":"10.1109/IEDM.2012.6478969","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6478969","url":null,"abstract":"A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time. Low standby power and high voltage transistors exploiting the superior short channel control, <; 65mV/dec subthreshold slope and <;40mV DIBL, of the Tri-Gate architecture have been fabricated concurrently with high speed logic transistors in a single SoC chip to achieve industry leading drive currents at record low leakage levels. NMOS/PMOS Idsat=0.41/0.37mA/um at 30pA/um Ioff, 0.75V, were used to build a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages. This technology offers mix-and-match flexibility of transistor types, high-density interconnect stacks, and RF/mixed-signal features for leadership in mobile, handheld, wireless and embedded SoC products.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"32 1","pages":"3.1.1-3.1.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74409795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479057
M. Luisier
In this paper, the electronic and thermal properties of ultra-scaled nanowire transistors are investigated using a single, atomistic, quantum transport simulator based on the Non-equilibrium Green's Function (NEGF) formalism as well as the tight-binding and valence-force-field methods to accurately describe the electron and phonon population, respectively. Although the length of the considered device structures does not exceed a few nanometers, dissipative scattering mechanisms such as electron-phonon and anharmonic phonon-phonon scattering still play an important role and should therefore be fully taken into account by the modeling approach. It will be shown here that these two effects strongly affect the performance of nanowire transistors, either by decreasing (backscattering) or increasing (opening of additional propagation channels) the electrical and thermal currents flowing through them.
{"title":"Towards atomistic simulations of the electro-thermal properties of nanowire transistors","authors":"M. Luisier","doi":"10.1109/IEDM.2012.6479057","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479057","url":null,"abstract":"In this paper, the electronic and thermal properties of ultra-scaled nanowire transistors are investigated using a single, atomistic, quantum transport simulator based on the Non-equilibrium Green's Function (NEGF) formalism as well as the tight-binding and valence-force-field methods to accurately describe the electron and phonon population, respectively. Although the length of the considered device structures does not exceed a few nanometers, dissipative scattering mechanisms such as electron-phonon and anharmonic phonon-phonon scattering still play an important role and should therefore be fully taken into account by the modeling approach. It will be shown here that these two effects strongly affect the performance of nanowire transistors, either by decreasing (backscattering) or increasing (opening of additional propagation channels) the electrical and thermal currents flowing through them.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"43 1","pages":"17.1.1-17.1.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74742903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479090
Shu‐Han Hsu, Hung-Chih Chang, C. Chu, Yen‐Ting Chen, W. Tu, F. Hou, Chih-hung Lo, P. Sung, Bo-Yuan Chen, G. Huang, G. Luo, Cheewee Liu, C. Hu, Fu-Liang Yang
Due to the highest electron mobility (2200 cm2/Vs) on (111) Ge surface, the n-channel triangular Ge gate-all-around (GAA) FET with (111) sidewalls on Si and Lg=350 nm shows 2x enhanced Ion of 110 μA/μm at 1V with respect to the devices with near (110) sidewalls. A novel process to etch away the defective Ge near Ge/Si interface from epitaxial Ge grown on SOI achieves a nearly defect-free channel, good gate control triangular gate, and larger effective width. Electrostatic control of SS= 94 mV/dec (at 1V) can be further improved if superior gate stack than EOT= 5.5 nm and Dit= 1×1012 cm-2eV-1 is used. The Ion can be further enhanced if the line edge roughness (LER) can be reduced. The Ge GAA n-FET is reported for the first time with CMOS compatible process, which makes the circuits integration much easier.
{"title":"Triangular-channel Ge NFETs on Si with (111) sidewall-enhanced Ion and nearly defect-free channels","authors":"Shu‐Han Hsu, Hung-Chih Chang, C. Chu, Yen‐Ting Chen, W. Tu, F. Hou, Chih-hung Lo, P. Sung, Bo-Yuan Chen, G. Huang, G. Luo, Cheewee Liu, C. Hu, Fu-Liang Yang","doi":"10.1109/IEDM.2012.6479090","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479090","url":null,"abstract":"Due to the highest electron mobility (2200 cm<sup>2</sup>/Vs) on (111) Ge surface, the n-channel triangular Ge gate-all-around (GAA) FET with (111) sidewalls on Si and L<sub>g</sub>=350 nm shows 2x enhanced I<sub>on</sub> of 110 μA/μm at 1V with respect to the devices with near (110) sidewalls. A novel process to etch away the defective Ge near Ge/Si interface from epitaxial Ge grown on SOI achieves a nearly defect-free channel, good gate control triangular gate, and larger effective width. Electrostatic control of SS= 94 mV/dec (at 1V) can be further improved if superior gate stack than EOT= 5.5 nm and D<sub>it</sub>= 1×10<sup>12</sup> cm<sup>-2</sup>eV<sup>-1</sup> is used. The I<sub>on</sub> can be further enhanced if the line edge roughness (LER) can be reduced. The Ge GAA n-FET is reported for the first time with CMOS compatible process, which makes the circuits integration much easier.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"21 1","pages":"23.6.1-23.6.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77726614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479147
Dong-il Moon, Sung-Jin Choi, Jee-Yeon Kim, Seungwon Ko, Moon-Seok Kim, J. Oh, G. Lee, Min-Ho Kang, Young-Su Kim, J. Kim, Yang‐Kyu Choi
A BJT named `biristor', a term derived from `bi-stable resistor', is demonstrated for 4F2 high speed volatile memory applications. For a floating body cell, a gate-less vertical silicon pillar, which is an n-p-n BJT with an open-base, is employed, whereas for its control device, a MOSFET composed of a vertical silicon pillar surrounded by a gate is utilized. A 4F2 memory cell array is realized by the unidirectional operation of a vertical two-terminal biristor, which consists of a cross-bar array. Due to the nature of the gate-less structure, the biristor cell shows excellent endurance of up to 1016.
{"title":"Highly endurable floating body cell memory: Vertical biristor","authors":"Dong-il Moon, Sung-Jin Choi, Jee-Yeon Kim, Seungwon Ko, Moon-Seok Kim, J. Oh, G. Lee, Min-Ho Kang, Young-Su Kim, J. Kim, Yang‐Kyu Choi","doi":"10.1109/IEDM.2012.6479147","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479147","url":null,"abstract":"A BJT named `biristor', a term derived from `bi-stable resistor', is demonstrated for 4F2 high speed volatile memory applications. For a floating body cell, a gate-less vertical silicon pillar, which is an n-p-n BJT with an open-base, is employed, whereas for its control device, a MOSFET composed of a vertical silicon pillar surrounded by a gate is utilized. A 4F2 memory cell array is realized by the unidirectional operation of a vertical two-terminal biristor, which consists of a cross-bar array. Due to the nature of the gate-less structure, the biristor cell shows excellent endurance of up to 1016.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"42 1","pages":"31.7.1-31.7.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76507632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6478998
T. Hosoi, Shuji Azumo, Yusaku Kashiwagi, S. Hosaka, R. Nakamura, Shuhei Mitani, Y. Nakano, H. Asahara, Takashi Nakamura, Tsunenobu Kimoto, T. Shimura, Heiji Watanabe
We have developed AlON high-k gate dielectric technology that can be easily implemented into both planar and trench SiC-based MOSFETs. On the basis of electrical characterization and numerical simulation, the thickness ratio of the AlON layer to the SiO2 interlayer and nitrogen content in AlON film were carefully optimized to enhance device performance and reliability.
{"title":"Performance and reliability improvement in SiC power MOSFETs by implementing AlON high-k gate dielectrics","authors":"T. Hosoi, Shuji Azumo, Yusaku Kashiwagi, S. Hosaka, R. Nakamura, Shuhei Mitani, Y. Nakano, H. Asahara, Takashi Nakamura, Tsunenobu Kimoto, T. Shimura, Heiji Watanabe","doi":"10.1109/IEDM.2012.6478998","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6478998","url":null,"abstract":"We have developed AlON high-k gate dielectric technology that can be easily implemented into both planar and trench SiC-based MOSFETs. On the basis of electrical characterization and numerical simulation, the thickness ratio of the AlON layer to the SiO2 interlayer and nitrogen content in AlON film were carefully optimized to enhance device performance and reliability.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"240 1","pages":"7.4.1-7.4.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80463782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6478996
T. Morita, S. Ujita, H. Umeda, Y. Kinoshita, S. Tamura, Y. Anda, T. Ueda, T. Tanaka
In this paper, we present a novel GaN-based normally-off transistor with an integrated Si Schottky barrier diode (SBD) for low voltage DC-DC converters. The integrated SBD is formed by the Si substrate for the epitaxial growth of AlGaN/GaN hetero-structure, which is connected to the normally-off GaN Gate Injection Transistor (GIT) over it with via-holes. The diode can flow the reverse current in the conversion operation with lower forward voltage than that of the lateral GaN transistor enabling lower operating loss. A DC-DC converter from 12V down to 1.3V using the integrated devices with the reduced gate length down to 0.5μm exhibits a high peak efficiency of 89% at 2MHz demonstrating the promising potential of GaN devices for the application.
{"title":"GaN Gate Injection Transistor with integrated Si Schottky barrier diode for highly efficient DC-DC converters","authors":"T. Morita, S. Ujita, H. Umeda, Y. Kinoshita, S. Tamura, Y. Anda, T. Ueda, T. Tanaka","doi":"10.1109/IEDM.2012.6478996","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6478996","url":null,"abstract":"In this paper, we present a novel GaN-based normally-off transistor with an integrated Si Schottky barrier diode (SBD) for low voltage DC-DC converters. The integrated SBD is formed by the Si substrate for the epitaxial growth of AlGaN/GaN hetero-structure, which is connected to the normally-off GaN Gate Injection Transistor (GIT) over it with via-holes. The diode can flow the reverse current in the conversion operation with lower forward voltage than that of the lateral GaN transistor enabling lower operating loss. A DC-DC converter from 12V down to 1.3V using the integrated devices with the reduced gate length down to 0.5μm exhibits a high peak efficiency of 89% at 2MHz demonstrating the promising potential of GaN devices for the application.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"28 1","pages":"7.2.1-7.2.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83084712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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