Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487677
Qiyang Wu, T. Quach, A. Mattamana, S. Elabd, S. Dooley, J. Mccue, P. Orlando, G. Creech, W. Khalil
The continued scaling of digital CMOS technology has enabled mm-Wave VCOs with record figures of merit [1-5]. This is mainly driven by the increase in cutoff frequency and decrease in power consumption brought by lower supply voltages. However, at mm-Wave, challenges such as low Q-factor of the tuning varactors and switched capacitors result in a sharp degradation in the resonator Q. For an NMOS LC-VCO (Fig. 8.8.1), a large bias current and high transconductance (gm) are needed to maintain a given oscillation amplitude and to satisfy the startup condition. Since gm has a weak dependency on current in strong inversion, it can primarily be increased by enlarging the device width, W1, as illustrated in Fig. 8.8.2. Further degradation in the device gm is experienced when the VCO operates near the transistor cutoff frequency, necessitating an even larger W1 (Fig. 8.8.2). This results in a large fixed capacitance Cfix1 and hence a limited VCO tuning range (TR) [1,2]. It can also be shown that for the same bias current (i.e. output swing), increasing W1 comes at the expense of large thermal (1/f2) noise. This can be illustrated by examining the excess noise factor F, defined as the ratio between the transistors' switching noise and the tank resistor noise [6]. As depicted in Fig. 8.8.2, an extra 5dB of 1/f2 noise is added to the VCO output when the transistor W1 is increased from 20μm to 60μm, which is required to meet a 2× startup margin. Moreover, increasing W1 leads to a higher contribution of 1/f3 noise from up-converted 1/f noise [7].
{"title":"A 10mW 37.8GHz current-redistribution BiCMOS VCO with an average FOMT of −193.5dBc/Hz","authors":"Qiyang Wu, T. Quach, A. Mattamana, S. Elabd, S. Dooley, J. Mccue, P. Orlando, G. Creech, W. Khalil","doi":"10.1109/ISSCC.2013.6487677","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487677","url":null,"abstract":"The continued scaling of digital CMOS technology has enabled mm-Wave VCOs with record figures of merit [1-5]. This is mainly driven by the increase in cutoff frequency and decrease in power consumption brought by lower supply voltages. However, at mm-Wave, challenges such as low Q-factor of the tuning varactors and switched capacitors result in a sharp degradation in the resonator Q. For an NMOS LC-VCO (Fig. 8.8.1), a large bias current and high transconductance (gm) are needed to maintain a given oscillation amplitude and to satisfy the startup condition. Since gm has a weak dependency on current in strong inversion, it can primarily be increased by enlarging the device width, W1, as illustrated in Fig. 8.8.2. Further degradation in the device gm is experienced when the VCO operates near the transistor cutoff frequency, necessitating an even larger W1 (Fig. 8.8.2). This results in a large fixed capacitance Cfix1 and hence a limited VCO tuning range (TR) [1,2]. It can also be shown that for the same bias current (i.e. output swing), increasing W1 comes at the expense of large thermal (1/f2) noise. This can be illustrated by examining the excess noise factor F, defined as the ratio between the transistors' switching noise and the tank resistor noise [6]. As depicted in Fig. 8.8.2, an extra 5dB of 1/f2 noise is added to the VCO output when the transistor W1 is increased from 20μm to 60μm, which is required to meet a 2× startup margin. Moreover, increasing W1 leads to a higher contribution of 1/f3 noise from up-converted 1/f noise [7].","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87498521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487825
S. Sukegawa, T. Umebayashi, T. Nakajima, Hiroshi Kawanobe, K. Koseki, I. Hirota, T. Haruta, Masanori Kasai, Koji Fukumoto, T. Wakano, Keishi Inoue, Hiroshi Takahashi, T. Nagano, Y. Nitta, T. Hirayama, Noriyuki Fukushima
In recent years, cellphone cameras have come to require much more diversification and increased functionalities, due to the strong growth of the smartphone market. In addition to the image quality, speed, and pixel counts that conventional image sensors require, there is high demand for new functions that can respond to various photo-taking scenes. We developed a stacked CMOS image sensor (CIS), composed of conventional back-illuminated (BI) image-sensor technology and 65nm standard logic technology.
{"title":"A 1/4-inch 8Mpixel back-illuminated stacked CMOS image sensor","authors":"S. Sukegawa, T. Umebayashi, T. Nakajima, Hiroshi Kawanobe, K. Koseki, I. Hirota, T. Haruta, Masanori Kasai, Koji Fukumoto, T. Wakano, Keishi Inoue, Hiroshi Takahashi, T. Nagano, Y. Nitta, T. Hirayama, Noriyuki Fukushima","doi":"10.1109/ISSCC.2013.6487825","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487825","url":null,"abstract":"In recent years, cellphone cameras have come to require much more diversification and increased functionalities, due to the strong growth of the smartphone market. In addition to the image quality, speed, and pixel counts that conventional image sensors require, there is high demand for new functions that can respond to various photo-taking scenes. We developed a stacked CMOS image sensor (CIS), composed of conventional back-illuminated (BI) image-sensor technology and 65nm standard logic technology.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86034992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To satisfy the demand of higher storage density, storing multiple-bits-per-cell technique is widely adopted. As presented in [1], a 4b/cell Flash memory by using error-detection (ED) scheme stores 2b data on two sides of a memory cell individually. Since the noise margin becomes smaller, the distribution drifts due to program disturb, data retention and temperature variation will cause higher raw bit-error-rate (RBER) if the sensing level (voltage) are not adjusted accordingly. The ED scheme can detect the drift direction by counting and storing the number of cells (Ni) with threshold voltage (VTH) below the ith sensing level (VREF i). A simple example with page size 1KB is demonstrated in Fig. 12.7.1. During a read operation, the number of cells (Ni, measured) whose VTH below VREF i is counted and compared to Ni. The ED scheme can find out a sub-optimal sensing level when Ni, measured and Ni is close enough. In this paper, a production 16Gb 45nm 4b/cell ONO-based charge-trapping (CT) Flash memory is demonstrated to achieve 6b/cell capability. Since the adjacent distributions for 6b/cell are much closer to each other, even a BCH code with ED scheme fails to correct all the patterns. However, by using a new 1-3-3 mapping and LDPC codes with a developed drift-immune soft-sensing (DI-SS) engine, the 45nm 4b/cell CT Flash memory is boosted to 6b/cell. The data flow of programming data is also shown in Fig. 12.7.1.
{"title":"A 45nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine","authors":"Kin-Chu Ho, Po-Chao Fang, Hsiang-Pang Li, Cheng-Yuan Michael Wang, Hsie-Chia Chang","doi":"10.1109/ISSCC.2013.6487709","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487709","url":null,"abstract":"To satisfy the demand of higher storage density, storing multiple-bits-per-cell technique is widely adopted. As presented in [1], a 4b/cell Flash memory by using error-detection (ED) scheme stores 2b data on two sides of a memory cell individually. Since the noise margin becomes smaller, the distribution drifts due to program disturb, data retention and temperature variation will cause higher raw bit-error-rate (RBER) if the sensing level (voltage) are not adjusted accordingly. The ED scheme can detect the drift direction by counting and storing the number of cells (Ni) with threshold voltage (VTH) below the ith sensing level (VREF i). A simple example with page size 1KB is demonstrated in Fig. 12.7.1. During a read operation, the number of cells (Ni, measured) whose VTH below VREF i is counted and compared to Ni. The ED scheme can find out a sub-optimal sensing level when Ni, measured and Ni is close enough. In this paper, a production 16Gb 45nm 4b/cell ONO-based charge-trapping (CT) Flash memory is demonstrated to achieve 6b/cell capability. Since the adjacent distributions for 6b/cell are much closer to each other, even a BCH code with ED scheme fails to correct all the patterns. However, by using a new 1-3-3 mapping and LDPC codes with a developed drift-immune soft-sensing (DI-SS) engine, the 45nm 4b/cell CT Flash memory is boosted to 6b/cell. The data flow of programming data is also shown in Fig. 12.7.1.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88625685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487727
Seon-Kyoo Lee, Seung-Hun Lee, D. Sylvester, D. Blaauw, J. Sim
Data communication between local system blocks through on-chip global interconnects presents significant design challenges in scaled VLSI systems. The goal of this research is to reduce the energy consumed per bit transmitted, while achieving Gb/s data rates over interconnect lengths up to 10mm. Voltage-mode signaling with capacitive boosting [1-2] has been proposed for low-power on-chip interconnects. To increase the data rate over RC-limited interconnect, aggressive equalization schemes should be used in receivers [1-3] and transmitters [1-2] at the cost of significant power consumption. As an alternative to voltage-mode signaling, current-mode signaling has been considered. It was originally used for fast bitline sensing in memory [4-5] to take inherent advantage of a reduced RC time constant. However, prior work on current-mode transceivers for on-chip interconnect shows worse energy efficiency than their voltage-mode counterparts due to large static power dissipation by current-sensing circuit [6-7]. This paper presents a 95fJ/b current-mode transceiver for on-chip global interconnect. The transceiver is implemented in 65nm CMOS and achieves a data rate of up to 4Gb/s over a 10mm link with a BER of less than 10-12.
{"title":"A 95fJ/b current-mode transceiver for 10mm on-chip interconnect","authors":"Seon-Kyoo Lee, Seung-Hun Lee, D. Sylvester, D. Blaauw, J. Sim","doi":"10.1109/ISSCC.2013.6487727","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487727","url":null,"abstract":"Data communication between local system blocks through on-chip global interconnects presents significant design challenges in scaled VLSI systems. The goal of this research is to reduce the energy consumed per bit transmitted, while achieving Gb/s data rates over interconnect lengths up to 10mm. Voltage-mode signaling with capacitive boosting [1-2] has been proposed for low-power on-chip interconnects. To increase the data rate over RC-limited interconnect, aggressive equalization schemes should be used in receivers [1-3] and transmitters [1-2] at the cost of significant power consumption. As an alternative to voltage-mode signaling, current-mode signaling has been considered. It was originally used for fast bitline sensing in memory [4-5] to take inherent advantage of a reduced RC time constant. However, prior work on current-mode transceivers for on-chip interconnect shows worse energy efficiency than their voltage-mode counterparts due to large static power dissipation by current-sensing circuit [6-7]. This paper presents a 95fJ/b current-mode transceiver for on-chip global interconnect. The transceiver is implemented in 65nm CMOS and achieves a data rate of up to 4Gb/s over a 10mm link with a BER of less than 10-12.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88673648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487670
Z. Wang, Pei-Yuan Chiang, Peyman Nazari, Chun-Cheng Wang, Zhiming Chen, P. Heydari
The vastly under-utilized spectrum in the sub-THz frequency range enables disruptive applications including 10Gb/s chip-to-chip wireless communications and imaging/spectroscopy. Owing to aggressive scaling in feature size and device fT/fmax, nanoscale CMOS technology potentially enables integration of sophisticated systems at this frequency range. For example, CMOS sub-THz signal sources and TRXs have been reported [1-4], employing techniques such as distributed active radiator (DAR) and super-harmonic signal generator. The lack of RF amplification in CMOS sub-THz TRXs reported in prior work, however, results in low efficiency (and thus higher power dissipation), and high noise-figure (NF). This paper addresses these issues by demonstrating a 210GHz TRX with on-off-keying (OOK) modulation incorporating a 2×2 TX antenna array, a 2×2 spatial combining power amplifier (PA), a fundamental frequency VCO, and a low noise amplifier (LNA) in a 32nm SOI CMOS process (fT/fmax=250/350GHz).
亚太赫兹频率范围内未充分利用的频谱可以实现颠覆性应用，包括10Gb/s芯片对芯片无线通信和成像/光谱。由于特征尺寸和器件fT/fmax的积极缩放，纳米级CMOS技术有可能在该频率范围内集成复杂的系统。例如，已经报道了CMOS亚太赫兹信号源和trx[1-4]，它们采用了分布式有源辐射器(DAR)和超谐波信号发生器等技术。然而，在先前的工作中报道的CMOS亚太赫兹trx缺乏RF放大，导致效率低(因此更高的功耗)和高噪声系数(NF)。本文通过在32nm SOI CMOS工艺(fT/fmax=250/350GHz)中演示具有开关键控(OOK)调制的210GHz TRX，该调制包含2×2 TX天线阵列、2×2空间组合功率放大器(PA)、基频VCO和低噪声放大器(LNA)。
{"title":"A 210GHz fully integrated differential transceiver with fundamental-frequency VCO in 32nm SOI CMOS","authors":"Z. Wang, Pei-Yuan Chiang, Peyman Nazari, Chun-Cheng Wang, Zhiming Chen, P. Heydari","doi":"10.1109/ISSCC.2013.6487670","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487670","url":null,"abstract":"The vastly under-utilized spectrum in the sub-THz frequency range enables disruptive applications including 10Gb/s chip-to-chip wireless communications and imaging/spectroscopy. Owing to aggressive scaling in feature size and device fT/fmax, nanoscale CMOS technology potentially enables integration of sophisticated systems at this frequency range. For example, CMOS sub-THz signal sources and TRXs have been reported [1-4], employing techniques such as distributed active radiator (DAR) and super-harmonic signal generator. The lack of RF amplification in CMOS sub-THz TRXs reported in prior work, however, results in low efficiency (and thus higher power dissipation), and high noise-figure (NF). This paper addresses these issues by demonstrating a 210GHz TRX with on-off-keying (OOK) modulation incorporating a 2×2 TX antenna array, a 2×2 spatial combining power amplifier (PA), a fundamental frequency VCO, and a low noise amplifier (LNA) in a 32nm SOI CMOS process (fT/fmax=250/350GHz).","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85007802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487661
G. Kalogerakis, T. Moran, Thelinh Nguyen, Gilles Denoyer
The push for 100Gb/s optical transport and beyond necessitates electronic components at higher speed and integration level in order to drive down cost, complexity and size of transceivers [1-2]. This requires parallel multi-channel optical transceivers each operating at 25Gb/s and beyond. Due to variations in the output power of transmitters and in some cases different optical paths the parallel receivers have to operate at different input optical power levels. This trend places increasing strain to the acceptable inter-channel crosstalk in integrated multi-channel receivers [3]. Minimizing this cross-talk penalty when all channels are operational is becoming increasingly important in ultra-high throughput optical links.
{"title":"A quad 25Gb/s 270mW TIA in 0.13µm BiCMOS with <0.15dB crosstalk penalty","authors":"G. Kalogerakis, T. Moran, Thelinh Nguyen, Gilles Denoyer","doi":"10.1109/ISSCC.2013.6487661","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487661","url":null,"abstract":"The push for 100Gb/s optical transport and beyond necessitates electronic components at higher speed and integration level in order to drive down cost, complexity and size of transceivers [1-2]. This requires parallel multi-channel optical transceivers each operating at 25Gb/s and beyond. Due to variations in the output power of transmitters and in some cases different optical paths the parallel receivers have to operate at different input optical power levels. This trend places increasing strain to the acceptable inter-channel crosstalk in integrated multi-channel receivers [3]. Minimizing this cross-talk penalty when all channels are operational is becoming increasingly important in ultra-high throughput optical links.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82129424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487771
P. Riehl, P. Fowers, Hao-Ping Hong, Michael Ashburn
High-data-rate wireless technologies such as HSUPA and LTE are power-hungry because of the fundamental correlation between data rate and transmit power. Furthermore, the high peak-to-average power ratio (PAPR) of the modulated signals causes a degradation in PA efficiency, since the supply voltage of the PA must be high enough to provide the peak output voltage without loss of linearity. Envelope tracking modulators have been proposed to improve the efficiency and linearity of transmitters. Modulators using multiple input voltages have been shown to improve efficiency, but generating multiple supplies imposes substantial overhead. Several recent works have demonstrated a hybrid modulator, combining the output current of a buck output stage with that of a linear amplifier. The hybrid modulator has the notable advantage that the low-frequency power (which constitutes the majority of power, even in high-PAPR scenarios) can be provided through the efficient buck stage. The inherently less efficient linear amplifier stage needs only to supply the high-frequency power. The efficiency of hybrid modulators degrades at moderate power levels, when the ac amplitude is much less than the supply voltage of the linear amplifier. At low power levels, the power savings afforded by the modulator do not offset its own quiescent current, resulting in a lower efficiency than can be achieved using a fixed-drain, average-power-tracking (FD-APT) supply.
{"title":"An AC-coupled hybrid envelope modulator for HSUPA transmitters with 80% modulator efficiency","authors":"P. Riehl, P. Fowers, Hao-Ping Hong, Michael Ashburn","doi":"10.1109/ISSCC.2013.6487771","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487771","url":null,"abstract":"High-data-rate wireless technologies such as HSUPA and LTE are power-hungry because of the fundamental correlation between data rate and transmit power. Furthermore, the high peak-to-average power ratio (PAPR) of the modulated signals causes a degradation in PA efficiency, since the supply voltage of the PA must be high enough to provide the peak output voltage without loss of linearity. Envelope tracking modulators have been proposed to improve the efficiency and linearity of transmitters. Modulators using multiple input voltages have been shown to improve efficiency, but generating multiple supplies imposes substantial overhead. Several recent works have demonstrated a hybrid modulator, combining the output current of a buck output stage with that of a linear amplifier. The hybrid modulator has the notable advantage that the low-frequency power (which constitutes the majority of power, even in high-PAPR scenarios) can be provided through the efficient buck stage. The inherently less efficient linear amplifier stage needs only to supply the high-frequency power. The efficiency of hybrid modulators degrades at moderate power levels, when the ac amplitude is much less than the supply voltage of the linear amplifier. At low power levels, the power savings afforded by the modulator do not offset its own quiescent current, resulting in a lower efficiency than can be achieved using a fixed-drain, average-power-tracking (FD-APT) supply.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84569858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487648
M. Mikhemar, D. Murphy, A. Mirzaei, H. Darabi
Recent passive-mixer-based architectures, such as [1], have shown that blockers as large as 0dBm can be tolerated without excessive gain compression. However, even in a perfectly linear receiver, reciprocal mixing of the blocker with LO phase noise deposits additive noise on the wanted signal, as shown in Fig. 5.3.1. This is an inevitable limitation to any mixer-based receiver. Assuming that the blocker experiences no passive RF filtering, the noise figure of such a receiver in the presence of a given blocker is only lowered through improving the LO phase noise. To overcome this challenge, most wireless receivers use LC-oscillators that despite their superior phase noise to ring oscillators [2], still consume a large portion of the radio power. As the quality factor of on-chip resonators does not scale with technology, the phase noise of an LC-oscillator can only be improved by consuming more power, while the benefits of circuit innovation are fundamentally limited [3]. Although increasing current helps, it does come at a cost, and is ultimately limited by the maximum allowable amplitude, and how reliably small inductor values can be fabricated without Q-degradation. In this paper, we propose a mixed-signal reciprocal-mixing cancellation technique that leads to a substantial reciprocal-mixing noise figure improvement independent of the LO phase noise.
{"title":"A phase-noise and spur filtering technique using reciprocal-mixing cancellation","authors":"M. Mikhemar, D. Murphy, A. Mirzaei, H. Darabi","doi":"10.1109/ISSCC.2013.6487648","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487648","url":null,"abstract":"Recent passive-mixer-based architectures, such as [1], have shown that blockers as large as 0dBm can be tolerated without excessive gain compression. However, even in a perfectly linear receiver, reciprocal mixing of the blocker with LO phase noise deposits additive noise on the wanted signal, as shown in Fig. 5.3.1. This is an inevitable limitation to any mixer-based receiver. Assuming that the blocker experiences no passive RF filtering, the noise figure of such a receiver in the presence of a given blocker is only lowered through improving the LO phase noise. To overcome this challenge, most wireless receivers use LC-oscillators that despite their superior phase noise to ring oscillators [2], still consume a large portion of the radio power. As the quality factor of on-chip resonators does not scale with technology, the phase noise of an LC-oscillator can only be improved by consuming more power, while the benefits of circuit innovation are fundamentally limited [3]. Although increasing current helps, it does come at a cost, and is ultimately limited by the maximum allowable amplitude, and how reliably small inductor values can be fabricated without Q-degradation. In this paper, we propose a mixed-signal reciprocal-mixing cancellation technique that leads to a substantial reciprocal-mixing noise figure improvement independent of the LO phase noise.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81577811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487657
Sahel Abdinia, M. Benwadih, R. Coppard, S. Jacob, G. Maiellaro, G. Palmisano, M. Rizzo, A. Scuderi, F. Tramontana, A. Roermund, E. Cantatore
Organic transistors (OTFTs) can be printed on thin plastic substrates to obtain mechanically flexible large-area electronics with high throughput. Examples of applications include sensor-augmented RFIDs fabricated on the packaging of retail items and smart surfaces integrating sensors or actuators. Printed OTFTs have been used to design circuits [1-4], however, these implementations have been mainly limited to digital circuits or large-area switch matrices. A major challenge in the design of printed circuits is the relatively high variability in the characteristics of the OTFTs, which is caused by the low degree of spatial correlation typical of printing processes. A relatively high rate of hard faults is also typical in printed electronics (at the state of the art, yield is acceptable only for a circuit complexity of ~100 transistors).
{"title":"A 4b ADC manufactured in a fully-printed organic complementary technology including resistors","authors":"Sahel Abdinia, M. Benwadih, R. Coppard, S. Jacob, G. Maiellaro, G. Palmisano, M. Rizzo, A. Scuderi, F. Tramontana, A. Roermund, E. Cantatore","doi":"10.1109/ISSCC.2013.6487657","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487657","url":null,"abstract":"Organic transistors (OTFTs) can be printed on thin plastic substrates to obtain mechanically flexible large-area electronics with high throughput. Examples of applications include sensor-augmented RFIDs fabricated on the packaging of retail items and smart surfaces integrating sensors or actuators. Printed OTFTs have been used to design circuits [1-4], however, these implementations have been mainly limited to digital circuits or large-area switch matrices. A major challenge in the design of printed circuits is the relatively high variability in the characteristics of the OTFTs, which is caused by the low degree of spatial correlation typical of printing processes. A relatively high rate of hard faults is also typical in printed electronics (at the state of the art, yield is acceptable only for a circuit complexity of ~100 transistors).","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87184042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487620
M. V. D. Brink
Chip makers are increasingly concerned about the shrink and cost. This concern drives different lithography solutions for different products. Two major trends can be observed: aggressive adoption of EUV, or aggressive extension of immersion. Further cost reduction could be achieved by introducing 450mm wafers.
{"title":"Continuing to shrink: Next-generation lithography - Progress and prospects","authors":"M. V. D. Brink","doi":"10.1109/ISSCC.2013.6487620","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487620","url":null,"abstract":"Chip makers are increasingly concerned about the shrink and cost. This concern drives different lithography solutions for different products. Two major trends can be observed: aggressive adoption of EUV, or aggressive extension of immersion. Further cost reduction could be achieved by introducing 450mm wafers.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77810316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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