Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248828
J. Tsai, A. Zhang, G. Li, M. Bachman
This paper describes the use of optical laminate optics that utilizes both passive 2-D optical elements and active components. This is demonstrated in a proof-of-concept 1×2 optical switch concept that is compatible with micro electrical mechanical systems (MEMS) fabricated in laminates. The device uses a waveguide structure that is precision cut to form a cantilever structure. The cantilever, which acts as a bendable waveguide, can be positioned into two locations to align with one of two corresponding waveguides. A light beam is directed into the front end of the cantilever which couples the signal to the tip of the cantilever. The cantilever tip can be positioned to align with one of two second waveguides, thereby sending the optical signal into a specified output. The cantilever is moved using an electromagnetic actuation force, and can be magnetically latched in position so that no further power is required to hold it in place. The unique aspect of this work is that the entire device can be fabricated using laminate technology commonly found in packaging and precision PCB foundries. This allows one to utilize materials and manufacturing methods not available to silicon processing, such as the use of a flexible polymer cantilever waveguide and magnetic materials. Further, it allows integration into printed circuits. We have demonstrated proof-of-concept for this device. This paper describes the design of the structure in laminates and shows initial results.
{"title":"A laminate cantilever waveguide optical switch","authors":"J. Tsai, A. Zhang, G. Li, M. Bachman","doi":"10.1109/ECTC.2012.6248828","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248828","url":null,"abstract":"This paper describes the use of optical laminate optics that utilizes both passive 2-D optical elements and active components. This is demonstrated in a proof-of-concept 1×2 optical switch concept that is compatible with micro electrical mechanical systems (MEMS) fabricated in laminates. The device uses a waveguide structure that is precision cut to form a cantilever structure. The cantilever, which acts as a bendable waveguide, can be positioned into two locations to align with one of two corresponding waveguides. A light beam is directed into the front end of the cantilever which couples the signal to the tip of the cantilever. The cantilever tip can be positioned to align with one of two second waveguides, thereby sending the optical signal into a specified output. The cantilever is moved using an electromagnetic actuation force, and can be magnetically latched in position so that no further power is required to hold it in place. The unique aspect of this work is that the entire device can be fabricated using laminate technology commonly found in packaging and precision PCB foundries. This allows one to utilize materials and manufacturing methods not available to silicon processing, such as the use of a flexible polymer cantilever waveguide and magnetic materials. Further, it allows integration into printed circuits. We have demonstrated proof-of-concept for this device. This paper describes the design of the structure in laminates and shows initial results.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81000669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249134
J. You, Yu-Chou Shih, Yeong-Her Lin, B. Yan, F. Shi
A special liquid encapsulant and the liquid encapsulation process are developed for enhancing passive cooling for the packaging of monochromatic LED emitters. It was observed that the liquid encapsulation process is superior than the conventional solid silicone encapsulation process in terms of the junction temperature for all the packaged emitters of various wavelengths using the liquid encapsulant. An enhanced reliability in terms of lifetime is thus expected for the emitters encapsulated with the liquid encapsulant. Moreover, an enhanced light output is also demonstrated for the emitters packaged with the liquid encapsulant, which can be attributed to be a result of the improved heat dissipation by convection and conduction in the upward direction through the liquid as well as in the downward direction through the contact area between the liquid and the reflective cup.
{"title":"Liquid encapsulation for monochromatic LED emitter packages: Enhancement of thermal-optical performance and reliability","authors":"J. You, Yu-Chou Shih, Yeong-Her Lin, B. Yan, F. Shi","doi":"10.1109/ECTC.2012.6249134","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249134","url":null,"abstract":"A special liquid encapsulant and the liquid encapsulation process are developed for enhancing passive cooling for the packaging of monochromatic LED emitters. It was observed that the liquid encapsulation process is superior than the conventional solid silicone encapsulation process in terms of the junction temperature for all the packaged emitters of various wavelengths using the liquid encapsulant. An enhanced reliability in terms of lifetime is thus expected for the emitters encapsulated with the liquid encapsulant. Moreover, an enhanced light output is also demonstrated for the emitters packaged with the liquid encapsulant, which can be attributed to be a result of the improved heat dissipation by convection and conduction in the upward direction through the liquid as well as in the downward direction through the contact area between the liquid and the reflective cup.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73606973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248902
Jing Zhou, L. Wan, Fengwei Dai, Huijuan Wang, Chongshen Song, Tianmin Du, Yanbiao Chu, M. Pan, D. Guidotti, Liqiang Cao, Daquan Yu
In this paper, a group of coplanar lines on a silicon dioxide insulating layer on a nominally doped silicon substrate is simulated and measured. Electrical parameters extracted from published data are used and lead to substantially improved agreement with measurements. In addition, several models of redistribution layer (RDL) with different shape-TSVs (through silicon vias) are simulated, along with two different joint structures between TSV and RDL. Simulation result suggest that because the electrical length is very short reflection losses attributed to the structural details of the TSV may be ignored in the applicable frequency band of the TSV. In addition, several optimized transmission line structures are designed and simulated. Results suggest that design criteria used to optimize lines in organic substrates are not directly transferable to a silicon substrate. This paper shows a simple but effective method with which to analyze the influences exerted by the metal oxide semiconductor (MOS) capacitance at the TSV interface and eddy currents in the substrate on a transmission line. Finally, newly de-embedded test structures are provided to extract spice model parameters for TSV modeling.
{"title":"Accurate electrical simulation and design optimization for silicon interposer considering the MOS effect and eddy currents in the silicon substrate","authors":"Jing Zhou, L. Wan, Fengwei Dai, Huijuan Wang, Chongshen Song, Tianmin Du, Yanbiao Chu, M. Pan, D. Guidotti, Liqiang Cao, Daquan Yu","doi":"10.1109/ECTC.2012.6248902","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248902","url":null,"abstract":"In this paper, a group of coplanar lines on a silicon dioxide insulating layer on a nominally doped silicon substrate is simulated and measured. Electrical parameters extracted from published data are used and lead to substantially improved agreement with measurements. In addition, several models of redistribution layer (RDL) with different shape-TSVs (through silicon vias) are simulated, along with two different joint structures between TSV and RDL. Simulation result suggest that because the electrical length is very short reflection losses attributed to the structural details of the TSV may be ignored in the applicable frequency band of the TSV. In addition, several optimized transmission line structures are designed and simulated. Results suggest that design criteria used to optimize lines in organic substrates are not directly transferable to a silicon substrate. This paper shows a simple but effective method with which to analyze the influences exerted by the metal oxide semiconductor (MOS) capacitance at the TSV interface and eddy currents in the substrate on a transmission line. Finally, newly de-embedded test structures are provided to extract spice model parameters for TSV modeling.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77927394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249098
Jamin Ling, Tao Xu, R. Chen, O. Valentin, C. Luechinger
As power-device technology evolves toward higher power density and devices require longer product lifespans, improving interconnect technologies becomes an increasingly important priority. Several alternatives to the widely accepted aluminum (Al) wire interconnect are being considered. Aluminum ribbon offers the first step of performance improvement in specific applications due to its higher current-carrying capacity and superior heat dissipation and is proven in high volume production. The next level of improvement is aluminum copper (Al-Cu) wire or ribbon. The Al-Cu interconnect can be used with standard Al die metallization with a tested reliability improvement of 4-5 times over Al wire. However, a robust process is yet to be developed that will achieve sufficiently high yields. The final level of performance improvement is copper (Cu) wire and ribbon. Recently it was reported that Cu wire bonding can improve bond reliability more than tenfold over Al wire. Significant technical challenges must be overcome, however, before large-Cu-wire and ribbon bonding is suitable for high-volume production. Testing shows that large-Cu-wire bonding with bond heads made specifically for Cu wire is feasible, but due to the uncertain availability of suitably metallized die, a process assessment of production requirements has not been finalized. This paper examines the relative benefits and challenges of the Al, Al-Cu and Cu interconnect technologies. The results show that Al-Cu could be an attractive solution from a performance and cost standpoint with existing Al based die metallization. Process studies and test results show that many characteristics of Al-Cu are common to Cu bonding, making the process development a stepping stone to affirming the more challenging but higher performance Cu process.
{"title":"Cu and Al-Cu composite-material interconnects for power devices","authors":"Jamin Ling, Tao Xu, R. Chen, O. Valentin, C. Luechinger","doi":"10.1109/ECTC.2012.6249098","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249098","url":null,"abstract":"As power-device technology evolves toward higher power density and devices require longer product lifespans, improving interconnect technologies becomes an increasingly important priority. Several alternatives to the widely accepted aluminum (Al) wire interconnect are being considered. Aluminum ribbon offers the first step of performance improvement in specific applications due to its higher current-carrying capacity and superior heat dissipation and is proven in high volume production. The next level of improvement is aluminum copper (Al-Cu) wire or ribbon. The Al-Cu interconnect can be used with standard Al die metallization with a tested reliability improvement of 4-5 times over Al wire. However, a robust process is yet to be developed that will achieve sufficiently high yields. The final level of performance improvement is copper (Cu) wire and ribbon. Recently it was reported that Cu wire bonding can improve bond reliability more than tenfold over Al wire. Significant technical challenges must be overcome, however, before large-Cu-wire and ribbon bonding is suitable for high-volume production. Testing shows that large-Cu-wire bonding with bond heads made specifically for Cu wire is feasible, but due to the uncertain availability of suitably metallized die, a process assessment of production requirements has not been finalized. This paper examines the relative benefits and challenges of the Al, Al-Cu and Cu interconnect technologies. The results show that Al-Cu could be an attractive solution from a performance and cost standpoint with existing Al based die metallization. Process studies and test results show that many characteristics of Al-Cu are common to Cu bonding, making the process development a stepping stone to affirming the more challenging but higher performance Cu process.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76642270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248881
K. Fujimoto, N. Maeda, H. Kitada, Y. Kim, S. Kodama, T. Nakamura, K. Suzuki, T. Ohba
The multi-stack processes for wafer-on-wafer (WOW) have been developed. The key features are bumpless interconnects adapted to TSVs and extendibility for chip-on-wafer (COW) taking high throughput into account. In order to realize the multi-stacked wafers with ultra thinned wafer of less than 10μm with an adhesive polymer, several processes have been optimized. The thickness of the wafer after back-grinding was controlled within the total thickness variation (TTV) of 1.2μm on wafer-level of 8 inch. As the dielectric film for the side wall of though silicon vias (TSV), SiN film with low deposition temperature of 150 °C has been developed and applied for TSV process without degradation for electrical characteristics. The uniformity of Cu electro-plating has been improved that the overburdened Cu from the surface was decreased from 13.3 μm to 0.7 μm by optimizing plating solution. The CMP process following Cu electro-plating has been customized for the high rate of 5 μm/min. Finally, the stacked wafer has been evaluated for thermal cycle test (TCT) of 100 cycles with -65 to 150 °C. The result showed that there was no degradation for reliability and packaging process.
{"title":"Development of cost-effective wafer level process for 3D-integration with bump-less TSV interconnects","authors":"K. Fujimoto, N. Maeda, H. Kitada, Y. Kim, S. Kodama, T. Nakamura, K. Suzuki, T. Ohba","doi":"10.1109/ECTC.2012.6248881","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248881","url":null,"abstract":"The multi-stack processes for wafer-on-wafer (WOW) have been developed. The key features are bumpless interconnects adapted to TSVs and extendibility for chip-on-wafer (COW) taking high throughput into account. In order to realize the multi-stacked wafers with ultra thinned wafer of less than 10μm with an adhesive polymer, several processes have been optimized. The thickness of the wafer after back-grinding was controlled within the total thickness variation (TTV) of 1.2μm on wafer-level of 8 inch. As the dielectric film for the side wall of though silicon vias (TSV), SiN film with low deposition temperature of 150 °C has been developed and applied for TSV process without degradation for electrical characteristics. The uniformity of Cu electro-plating has been improved that the overburdened Cu from the surface was decreased from 13.3 μm to 0.7 μm by optimizing plating solution. The CMP process following Cu electro-plating has been customized for the high rate of 5 μm/min. Finally, the stacked wafer has been evaluated for thermal cycle test (TCT) of 100 cycles with -65 to 150 °C. The result showed that there was no degradation for reliability and packaging process.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82574491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248866
K. Sakuma, K. Smith, K. Tunga, E. Perfecto, T. Wassick, F. Pompeo, J. Nah
A differential heating/cooling chip join method was developed for Pb-free flip chip packaging of ultra low-k (ULK) technology Si chips on organic substrates to prevent Chip-Package Interaction (CPI) - related damage upon chip joining. A chip was mounted to a bonder head and a substrate was located on a base plate and they were held at different elevated temperatures during the bonding process. The temperature difference between the Si chip and the organic substrate during assembly provides a substantially matched thermal expansion and minimizes stress induced by coefficient of thermal expansion (CTE) mismatch. From the modeling study, it was confirmed that chip warpage, Controlled Collapse Chip Connection (C4) stresses/strains, and ULK stresses decreased significantly by differential heating/cooling chip join method, with further improvement noted as the substrate temperature was decreased during the bonding process. X-ray, scanning electron microscope (SEM) and C-mode scanning acoustic microscope (C-SAM) were used to examine the defects after flip chip assembly. Noncontact white light reflectometry was also used to measure the warpage shape of the assembled silicon chip and the organic substrate. Observation under C-SAM indicated that fractures in the ULK layers were dramatically reduced by the differential heating/cooling chip joining process compared to the conventional reflow process. Non-destructive X-ray images indicated there were no solder bridging in any area of the chip interconnects. The experimental results showed that the differential heating/cooling chip join process can effectively reduce fractures in the ULK layers and prevent C4 bump bridging in a large die package with low-K dielectric constant device integration and high Ag content solder bumps.
{"title":"Differential heating/cooling chip joining method to prevent chip package interaction issue in large die with ultra low-k technology","authors":"K. Sakuma, K. Smith, K. Tunga, E. Perfecto, T. Wassick, F. Pompeo, J. Nah","doi":"10.1109/ECTC.2012.6248866","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248866","url":null,"abstract":"A differential heating/cooling chip join method was developed for Pb-free flip chip packaging of ultra low-k (ULK) technology Si chips on organic substrates to prevent Chip-Package Interaction (CPI) - related damage upon chip joining. A chip was mounted to a bonder head and a substrate was located on a base plate and they were held at different elevated temperatures during the bonding process. The temperature difference between the Si chip and the organic substrate during assembly provides a substantially matched thermal expansion and minimizes stress induced by coefficient of thermal expansion (CTE) mismatch. From the modeling study, it was confirmed that chip warpage, Controlled Collapse Chip Connection (C4) stresses/strains, and ULK stresses decreased significantly by differential heating/cooling chip join method, with further improvement noted as the substrate temperature was decreased during the bonding process. X-ray, scanning electron microscope (SEM) and C-mode scanning acoustic microscope (C-SAM) were used to examine the defects after flip chip assembly. Noncontact white light reflectometry was also used to measure the warpage shape of the assembled silicon chip and the organic substrate. Observation under C-SAM indicated that fractures in the ULK layers were dramatically reduced by the differential heating/cooling chip joining process compared to the conventional reflow process. Non-destructive X-ray images indicated there were no solder bridging in any area of the chip interconnects. The experimental results showed that the differential heating/cooling chip join process can effectively reduce fractures in the ULK layers and prevent C4 bump bridging in a large die package with low-K dielectric constant device integration and high Ag content solder bumps.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87763259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249106
Su-Heon Jeong, W. Nakayama, Sung-Ki Nam, Sun-Kyu Lee
Recently, liquid bridge heat switch has been suggested as effective thermal management solutions for the various thermal problems. The liquid bridge heat switch can control the thermal resistance and the temperature of desired position by regulating the liquid bridge between objective areas. The liquid bridge heat switch system is composed of hot plate as an upper plate, cold plate as a lower plate, and actuators. “On” state demand, the supplied liquid generates liquid bridge between two plates and conducts heat from hot plate to cold plate. The amount of conducting heat and thermal resistance are controlled by the diameter and height of generated liquid bridge. To be an “Off” state, the generated liquid bridge is retrieved and ruptured eventually. At that time, the heat switch system has maximum thermal resistance. This result decreased conduction of heat. In order to realize the desired switch operation, the precise liquid bridge control is required. In this research, the liquid bridge behavior was studied to design the heat switch system. The effects of channel geometry and clearance on the liquid bridge behavior were verified and the liquid bridge rupture conditions were found out. Based on the investigation, the liquid bridge heat switch system was designed for the high power LED cooling system. In a series of experiment, the stable liquid bridge operation was achieved by designed channel geometry. The results also showed that proposed heat switch system was able to decrease the LED junction temperature and regulate the thermal resistance between hot and cold plate.
{"title":"Design of a liquid bridge heat switch system based on the liquid bridge control for electronics cooling","authors":"Su-Heon Jeong, W. Nakayama, Sung-Ki Nam, Sun-Kyu Lee","doi":"10.1109/ECTC.2012.6249106","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249106","url":null,"abstract":"Recently, liquid bridge heat switch has been suggested as effective thermal management solutions for the various thermal problems. The liquid bridge heat switch can control the thermal resistance and the temperature of desired position by regulating the liquid bridge between objective areas. The liquid bridge heat switch system is composed of hot plate as an upper plate, cold plate as a lower plate, and actuators. “On” state demand, the supplied liquid generates liquid bridge between two plates and conducts heat from hot plate to cold plate. The amount of conducting heat and thermal resistance are controlled by the diameter and height of generated liquid bridge. To be an “Off” state, the generated liquid bridge is retrieved and ruptured eventually. At that time, the heat switch system has maximum thermal resistance. This result decreased conduction of heat. In order to realize the desired switch operation, the precise liquid bridge control is required. In this research, the liquid bridge behavior was studied to design the heat switch system. The effects of channel geometry and clearance on the liquid bridge behavior were verified and the liquid bridge rupture conditions were found out. Based on the investigation, the liquid bridge heat switch system was designed for the high power LED cooling system. In a series of experiment, the stable liquid bridge operation was achieved by designed channel geometry. The results also showed that proposed heat switch system was able to decrease the LED junction temperature and regulate the thermal resistance between hot and cold plate.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88328557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248797
C. Ko, Z. Hsiao, Y. J. Chang, P. S. Chen, J. Huang, H. Fu, Y. J. Huang, C. Chiang, C. K. Lee, H. Chang, W. Tsai, Y. -. Chen, W. Lo, K. N. Chen
In this study, a wafer-level 3D integration scheme with Cu TSVs based on Cu/Sn micro-bump and BCB adhesive hybrid bonding is demonstrated. To realize the signal transmission effects in high speed digital signaling via Cu TSV and Cu/Sn micro-joint interconnection, the insertion loss was investigated by simulation analysis with variable TSV pitches, micro-bump diameters and chip thicknesses. Key technologies include TSV fabrication, micro-bumping, hybrid scheme making, hybrid bonding, wafer thinning and backside RDL formation were well developed and integrated to perform the 3D integration scheme. 5μm TSV, 10μm micro-bump, 20μm pitch, 40μm thin wafer, and 250°C low temperature W2W hybrid bonding have been successfully integrated in the integration platform. The 3D scheme was characterized and assessed to have excellent electrical performance and reliability, and is potentially to be applied for 3D product applications.
{"title":"Structural design, process, and reliability of a wafer-level 3D integration scheme with Cu TSVs based on micro-bump/adhesive hybrid wafer bonding","authors":"C. Ko, Z. Hsiao, Y. J. Chang, P. S. Chen, J. Huang, H. Fu, Y. J. Huang, C. Chiang, C. K. Lee, H. Chang, W. Tsai, Y. -. Chen, W. Lo, K. N. Chen","doi":"10.1109/ECTC.2012.6248797","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248797","url":null,"abstract":"In this study, a wafer-level 3D integration scheme with Cu TSVs based on Cu/Sn micro-bump and BCB adhesive hybrid bonding is demonstrated. To realize the signal transmission effects in high speed digital signaling via Cu TSV and Cu/Sn micro-joint interconnection, the insertion loss was investigated by simulation analysis with variable TSV pitches, micro-bump diameters and chip thicknesses. Key technologies include TSV fabrication, micro-bumping, hybrid scheme making, hybrid bonding, wafer thinning and backside RDL formation were well developed and integrated to perform the 3D integration scheme. 5μm TSV, 10μm micro-bump, 20μm pitch, 40μm thin wafer, and 250°C low temperature W2W hybrid bonding have been successfully integrated in the integration platform. The 3D scheme was characterized and assessed to have excellent electrical performance and reliability, and is potentially to be applied for 3D product applications.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86201114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248952
Y. Liu, Qiuxiao Qian, S. Qu, S. Martin, O. Jeon
Intensive FEA modeling was applied to the investigation of early solder joint failures of WLCSP mounted on test PCBs. In particular, stress in assembly reflow process was studied with 25 balls; 0.4 mm pitch WLCSP and PCBs with specially placed plated though vias. The 25 ball WLCSP in the study has 5×5 ball array, which corresponds to 16 outmost solder joints and nine inner solder joints, all soldered to the matching copper pads on the test PCB. Three PCB designs were modeled to understand the impact of PCB through via arrangement on stresses in solder joints during assembly reflow process: design #1 has no PCB through vias at all; design #2 has plated through vias under nine inner PCB copper pads; design #3 has plated through vias under all 25 PCB copper pads. The modeling results disclose that PCB design #2 with plated through vias under nine inner PCB copper pads induces the highest solder stress in all three models. Contrary to common sense of higher stress on corner solder joints due to coefficient of thermal expansion (CTE) mismatch of silicon and PCB, the maximum stresses of design #2 actually occur on the inner solder joints. The simulation results match well with experimental observations. For PCB design #1 and #3, highest solder stress is lower than stress in design #2. In addition, in both cases, the maximum stress locates on the corner solder joints. New PCB design guidelines have since been implemented based on the simulation. Due to the improvement of the design, premature solder joint failure has not been recorded.
{"title":"Investigation of the assembly reflow process and PCB design on the reliability of WLCSP","authors":"Y. Liu, Qiuxiao Qian, S. Qu, S. Martin, O. Jeon","doi":"10.1109/ECTC.2012.6248952","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248952","url":null,"abstract":"Intensive FEA modeling was applied to the investigation of early solder joint failures of WLCSP mounted on test PCBs. In particular, stress in assembly reflow process was studied with 25 balls; 0.4 mm pitch WLCSP and PCBs with specially placed plated though vias. The 25 ball WLCSP in the study has 5×5 ball array, which corresponds to 16 outmost solder joints and nine inner solder joints, all soldered to the matching copper pads on the test PCB. Three PCB designs were modeled to understand the impact of PCB through via arrangement on stresses in solder joints during assembly reflow process: design #1 has no PCB through vias at all; design #2 has plated through vias under nine inner PCB copper pads; design #3 has plated through vias under all 25 PCB copper pads. The modeling results disclose that PCB design #2 with plated through vias under nine inner PCB copper pads induces the highest solder stress in all three models. Contrary to common sense of higher stress on corner solder joints due to coefficient of thermal expansion (CTE) mismatch of silicon and PCB, the maximum stresses of design #2 actually occur on the inner solder joints. The simulation results match well with experimental observations. For PCB design #1 and #3, highest solder stress is lower than stress in design #2. In addition, in both cases, the maximum stress locates on the corner solder joints. New PCB design guidelines have since been implemented based on the simulation. Due to the improvement of the design, premature solder joint failure has not been recorded.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89051972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248913
W. Chen, S. Kang, C. Kao
Reliability issues of Pb-free solder joints used in microelectronic interconnects, such as BGA, flip-chip, or even 3D-IC, are becoming more critical recently when high performance electronic systems demand more rigorous reliability requirements. The selection of new solder materials has been an important topic in order to enhance the reliability of Pb-free solder joints. In the past few years, numerous studies have been conducted on the beneficial effects of minor alloying elements, including Co, Cu, Fe, Ni, Zn and others, into Sn-rich Pb-free solders [1-6]. Only recently have Liu et al. [7] first reported the beneficial effect of Ti in SAC (Sn-Ag-Cu) solder for BGA applications with superior drop-impact performance. Getting such a superior drop-impact performance usually compromises high temperature mechanical properties such as creep resistance. But they found SAC-Ti having enhanced drop-impact performance without sacrificing a good creep property. Improving simultaneously these two mechanical properties was regarded as an excellent achievement of SAC-Ti. Moreover, considerable suppression of the undercooling and retardation of interfacial IMCs were also reported owing to the addition of Ti to SAC. Nevertheless, V. Vuorinen and his coworkers [8] lately reported the result of a thermal aging experiment on SnAg solder modified with Ti and asserted that the minor addition of Ti cannot change the activities of components nor influence the stability of the IMC layers. This study did not support the beneficial effects of minor alloying addition of Ti in SAC of the previous report [7]. Hence, it is essential to clarify the effect of Ti-addition on Sn-rich solders by further investigation. The objectives of our present work are (a) to understand the intrinsic consequence of Ti-addition on Sn-Ag and Sn-Cu solders, (b) to observe whether Ti-addition can influence the interfacial reactions between solders and under-bump metallurgies (UBMs), and (c) to reveal the contribution of Ti-addition on any other reliability performance, such as electro-migration (EM) resistance. In this study, two Ti-added Sn-Ag and Sn-Cu solders were commercially prepared; Sn-1.0Ag-0.2Ti (wt.%) and Sn-0.7Cu-0.2Ti (wt.%) in the form of solder ingots. They were cut into small pieces and evaluated for their metallurgical properties and interfacial reactions with Cu and Ni UBMs. Pure Sn-1.0Ag (wt.%) and Sn-0.7Cu (wt.%) were also prepared in the form of solder balls as control samples. DSC (differential scanning calorimetry) analysis was used to study the melting/solidification behavior of Ti-added solders. It was confirmed that a small amount of Ti addition can effectively reduce the undercooling to a few degrees, while a large undercooling is persistent in Sn-Ag or Sn-Cu solders without Ti addition. It is worth noting that a small undercooling can lessen a possibility of non-uniform solidification among many neighboring solder joints during reflow, which is beneficial for joint integ
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