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2012 IEEE 62nd Electronic Components and Technology Conference最新文献

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A laminate cantilever waveguide optical switch 一种层状悬臂波导光开关
Pub Date : 2012-07-30 DOI: 10.1109/ECTC.2012.6248828
J. Tsai, A. Zhang, G. Li, M. Bachman
This paper describes the use of optical laminate optics that utilizes both passive 2-D optical elements and active components. This is demonstrated in a proof-of-concept 1×2 optical switch concept that is compatible with micro electrical mechanical systems (MEMS) fabricated in laminates. The device uses a waveguide structure that is precision cut to form a cantilever structure. The cantilever, which acts as a bendable waveguide, can be positioned into two locations to align with one of two corresponding waveguides. A light beam is directed into the front end of the cantilever which couples the signal to the tip of the cantilever. The cantilever tip can be positioned to align with one of two second waveguides, thereby sending the optical signal into a specified output. The cantilever is moved using an electromagnetic actuation force, and can be magnetically latched in position so that no further power is required to hold it in place. The unique aspect of this work is that the entire device can be fabricated using laminate technology commonly found in packaging and precision PCB foundries. This allows one to utilize materials and manufacturing methods not available to silicon processing, such as the use of a flexible polymer cantilever waveguide and magnetic materials. Further, it allows integration into printed circuits. We have demonstrated proof-of-concept for this device. This paper describes the design of the structure in laminates and shows initial results.
本文介绍了利用无源二维光学元件和有源光学元件的光学层压板光学的使用。这在概念验证1×2光开关概念中得到了证明,该概念与层压板制造的微机电系统(MEMS)兼容。该装置采用精密切割形成悬臂结构的波导结构。悬臂作为一个可弯曲的波导,可以定位到两个位置,与两个相应的波导中的一个对齐。光束被引导到悬臂梁的前端,该悬臂梁将信号耦合到悬臂梁的尖端。悬臂尖端可以定位为与两个第二波导中的一个对齐,从而将光信号发送到指定的输出端。悬臂使用电磁致动力移动,并且可以磁锁定在位置上,因此不需要进一步的动力来保持它。这项工作的独特之处在于,整个设备可以使用封装和精密PCB代工厂中常见的层压板技术制造。这使得人们可以利用硅加工所不具备的材料和制造方法,例如使用柔性聚合物悬臂波导和磁性材料。此外,它还可以集成到印刷电路中。我们已经展示了这个设备的概念验证。本文介绍了层压板结构的设计,并给出了初步结果。
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引用次数: 2
Liquid encapsulation for monochromatic LED emitter packages: Enhancement of thermal-optical performance and reliability 单色LED发射器封装的液体封装:增强热光学性能和可靠性
Pub Date : 2012-07-30 DOI: 10.1109/ECTC.2012.6249134
J. You, Yu-Chou Shih, Yeong-Her Lin, B. Yan, F. Shi
A special liquid encapsulant and the liquid encapsulation process are developed for enhancing passive cooling for the packaging of monochromatic LED emitters. It was observed that the liquid encapsulation process is superior than the conventional solid silicone encapsulation process in terms of the junction temperature for all the packaged emitters of various wavelengths using the liquid encapsulant. An enhanced reliability in terms of lifetime is thus expected for the emitters encapsulated with the liquid encapsulant. Moreover, an enhanced light output is also demonstrated for the emitters packaged with the liquid encapsulant, which can be attributed to be a result of the improved heat dissipation by convection and conduction in the upward direction through the liquid as well as in the downward direction through the contact area between the liquid and the reflective cup.
为提高单色LED发光器件封装的被动冷却性能,研制了一种特殊的液体封装剂和液体封装工艺。结果表明,液体封装工艺对不同波长的封装发射体的结温均优于传统的固体硅封装工艺。因此,期望用液体封装剂封装的发射器在寿命方面具有增强的可靠性。此外,对于装有液体封装剂的发射器,还演示了增强的光输出,这可归因于通过液体向上以及通过液体与反射杯之间的接触区域向下通过对流和传导改善了散热。
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引用次数: 1
Accurate electrical simulation and design optimization for silicon interposer considering the MOS effect and eddy currents in the silicon substrate 考虑MOS效应和硅衬底涡流的硅中间体的精确电学仿真与设计优化
Pub Date : 2012-07-30 DOI: 10.1109/ECTC.2012.6248902
Jing Zhou, L. Wan, Fengwei Dai, Huijuan Wang, Chongshen Song, Tianmin Du, Yanbiao Chu, M. Pan, D. Guidotti, Liqiang Cao, Daquan Yu
In this paper, a group of coplanar lines on a silicon dioxide insulating layer on a nominally doped silicon substrate is simulated and measured. Electrical parameters extracted from published data are used and lead to substantially improved agreement with measurements. In addition, several models of redistribution layer (RDL) with different shape-TSVs (through silicon vias) are simulated, along with two different joint structures between TSV and RDL. Simulation result suggest that because the electrical length is very short reflection losses attributed to the structural details of the TSV may be ignored in the applicable frequency band of the TSV. In addition, several optimized transmission line structures are designed and simulated. Results suggest that design criteria used to optimize lines in organic substrates are not directly transferable to a silicon substrate. This paper shows a simple but effective method with which to analyze the influences exerted by the metal oxide semiconductor (MOS) capacitance at the TSV interface and eddy currents in the substrate on a transmission line. Finally, newly de-embedded test structures are provided to extract spice model parameters for TSV modeling.
本文对名义掺杂硅衬底上二氧化硅绝缘层上的一组共面线进行了模拟和测量。从公布的数据中提取的电气参数被使用,并导致与测量结果的一致性大大提高。此外,还模拟了具有不同形状的TSV(通过硅孔)的重分配层(RDL)模型,以及TSV和RDL之间的两种不同连接结构。仿真结果表明,由于电长度很短,在TSV的适用频段内,由TSV结构细节引起的反射损耗可以忽略不计。此外,还对几种优化的输电线路结构进行了设计和仿真。结果表明,用于优化有机衬底线的设计标准不能直接转移到硅衬底。本文给出了一种简单而有效的方法来分析TSV接口处的金属氧化物半导体(MOS)电容和传输线衬底涡流的影响。最后,提供了新的去嵌入测试结构,用于提取TSV建模所需的spice模型参数。
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引用次数: 8
Cu and Al-Cu composite-material interconnects for power devices 电力器件用Cu和Al-Cu复合材料互连
Pub Date : 2012-07-30 DOI: 10.1109/ECTC.2012.6249098
Jamin Ling, Tao Xu, R. Chen, O. Valentin, C. Luechinger
As power-device technology evolves toward higher power density and devices require longer product lifespans, improving interconnect technologies becomes an increasingly important priority. Several alternatives to the widely accepted aluminum (Al) wire interconnect are being considered. Aluminum ribbon offers the first step of performance improvement in specific applications due to its higher current-carrying capacity and superior heat dissipation and is proven in high volume production. The next level of improvement is aluminum copper (Al-Cu) wire or ribbon. The Al-Cu interconnect can be used with standard Al die metallization with a tested reliability improvement of 4-5 times over Al wire. However, a robust process is yet to be developed that will achieve sufficiently high yields. The final level of performance improvement is copper (Cu) wire and ribbon. Recently it was reported that Cu wire bonding can improve bond reliability more than tenfold over Al wire. Significant technical challenges must be overcome, however, before large-Cu-wire and ribbon bonding is suitable for high-volume production. Testing shows that large-Cu-wire bonding with bond heads made specifically for Cu wire is feasible, but due to the uncertain availability of suitably metallized die, a process assessment of production requirements has not been finalized. This paper examines the relative benefits and challenges of the Al, Al-Cu and Cu interconnect technologies. The results show that Al-Cu could be an attractive solution from a performance and cost standpoint with existing Al based die metallization. Process studies and test results show that many characteristics of Al-Cu are common to Cu bonding, making the process development a stepping stone to affirming the more challenging but higher performance Cu process.
随着功率器件技术向更高的功率密度发展,器件需要更长的产品寿命,改进互连技术变得越来越重要。目前正在考虑几种替代广泛接受的铝(Al)线互连的方法。铝带由于其更高的载流能力和优越的散热能力,在特定应用中提供了性能改进的第一步,并在大批量生产中得到了验证。下一个改进级别是铝铜(Al-Cu)线或带。铝铜互连可以与标准铝模具金属化一起使用,经测试的可靠性比铝线提高4-5倍。然而,一个强大的过程尚未开发,将实现足够高的产量。性能改进的最后一级是铜(Cu)线和带。最近有报道称,铜丝键合可以将键合可靠性提高到铝丝的10倍以上。然而,在大型铜线和带状键合适合大批量生产之前,必须克服重大的技术挑战。测试表明,使用专门为铜线制作的键头进行大型铜线键合是可行的,但由于不确定是否可以获得适当的金属化模具,对生产要求的工艺评估尚未最终确定。本文探讨了铝、铝铜和铜互连技术的相对优势和挑战。结果表明,从性能和成本的角度来看,铝铜可以成为现有铝基模具金属化的一个有吸引力的解决方案。工艺研究和试验结果表明,Al-Cu的许多特征是铜键合所共有的,这使得工艺开发成为确定更具挑战性但性能更高的铜工艺的垫脚石。
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引用次数: 8
Development of cost-effective wafer level process for 3D-integration with bump-less TSV interconnects 开发具有成本效益的晶圆级3d集成工艺与无碰撞TSV互连
Pub Date : 2012-07-30 DOI: 10.1109/ECTC.2012.6248881
K. Fujimoto, N. Maeda, H. Kitada, Y. Kim, S. Kodama, T. Nakamura, K. Suzuki, T. Ohba
The multi-stack processes for wafer-on-wafer (WOW) have been developed. The key features are bumpless interconnects adapted to TSVs and extendibility for chip-on-wafer (COW) taking high throughput into account. In order to realize the multi-stacked wafers with ultra thinned wafer of less than 10μm with an adhesive polymer, several processes have been optimized. The thickness of the wafer after back-grinding was controlled within the total thickness variation (TTV) of 1.2μm on wafer-level of 8 inch. As the dielectric film for the side wall of though silicon vias (TSV), SiN film with low deposition temperature of 150 °C has been developed and applied for TSV process without degradation for electrical characteristics. The uniformity of Cu electro-plating has been improved that the overburdened Cu from the surface was decreased from 13.3 μm to 0.7 μm by optimizing plating solution. The CMP process following Cu electro-plating has been customized for the high rate of 5 μm/min. Finally, the stacked wafer has been evaluated for thermal cycle test (TCT) of 100 cycles with -65 to 150 °C. The result showed that there was no degradation for reliability and packaging process.
硅片对硅片(WOW)的多层叠工艺得到了发展。主要特点是适合tsv的无凹凸互连和考虑到高吞吐量的片上(COW)的可扩展性。为了实现小于10μm的超薄晶片与粘接聚合物的多层堆叠,对几种工艺进行了优化。反磨后的晶圆厚度在8英寸晶圆级上控制在总厚度变化(TTV) 1.2μm以内。作为透硅通孔(TSV)侧壁的介质膜,沉积温度低至150℃的SiN薄膜已被开发出来并应用于TSV工艺,且其电特性没有退化。通过对镀液的优化,Cu镀层的均匀性得到了改善,镀层表面的过量Cu从13.3 μm减小到0.7 μm。定制了铜电镀后的CMP工艺,速度可达5 μm/min。最后,对堆叠晶圆进行了-65至150°C的100次热循环测试(TCT)。结果表明,在可靠性和封装过程中没有退化。
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引用次数: 2
Differential heating/cooling chip joining method to prevent chip package interaction issue in large die with ultra low-k technology 采用超低k技术,采用差分加热/冷却芯片连接方法,防止大型芯片封装相互作用问题
Pub Date : 2012-07-30 DOI: 10.1109/ECTC.2012.6248866
K. Sakuma, K. Smith, K. Tunga, E. Perfecto, T. Wassick, F. Pompeo, J. Nah
A differential heating/cooling chip join method was developed for Pb-free flip chip packaging of ultra low-k (ULK) technology Si chips on organic substrates to prevent Chip-Package Interaction (CPI) - related damage upon chip joining. A chip was mounted to a bonder head and a substrate was located on a base plate and they were held at different elevated temperatures during the bonding process. The temperature difference between the Si chip and the organic substrate during assembly provides a substantially matched thermal expansion and minimizes stress induced by coefficient of thermal expansion (CTE) mismatch. From the modeling study, it was confirmed that chip warpage, Controlled Collapse Chip Connection (C4) stresses/strains, and ULK stresses decreased significantly by differential heating/cooling chip join method, with further improvement noted as the substrate temperature was decreased during the bonding process. X-ray, scanning electron microscope (SEM) and C-mode scanning acoustic microscope (C-SAM) were used to examine the defects after flip chip assembly. Noncontact white light reflectometry was also used to measure the warpage shape of the assembled silicon chip and the organic substrate. Observation under C-SAM indicated that fractures in the ULK layers were dramatically reduced by the differential heating/cooling chip joining process compared to the conventional reflow process. Non-destructive X-ray images indicated there were no solder bridging in any area of the chip interconnects. The experimental results showed that the differential heating/cooling chip join process can effectively reduce fractures in the ULK layers and prevent C4 bump bridging in a large die package with low-K dielectric constant device integration and high Ag content solder bumps.
针对有机衬底上超低k (ULK)技术Si芯片的无铅反转封装,提出了一种不同的加热/冷却芯片连接方法,以防止芯片连接时芯片封装相互作用(CPI)相关的损伤。将芯片安装在粘合头上,将基板置于基板上,并在粘合过程中保持在不同的高温下。在组装过程中,硅片和有机衬底之间的温差提供了基本匹配的热膨胀,并将热膨胀系数(CTE)不匹配引起的应力降至最低。从建模研究中可以证实,通过不同的加热/冷却芯片连接方法,芯片翘曲、可控崩溃芯片连接(C4)应力/应变和ULK应力显著降低,并且随着结合过程中衬底温度的降低,进一步改善。采用x射线、扫描电镜(SEM)和c模扫描声显微镜(C-SAM)对倒装芯片组装后的缺陷进行了检测。非接触式白光反射法还用于测量组装硅芯片和有机衬底的翘曲形状。C-SAM观察表明,与常规回流工艺相比,采用不同的加热/冷却芯片连接工艺可以显著减少ULK层的裂缝。非破坏性x射线图像显示,在芯片互连的任何区域都没有焊接桥接。实验结果表明,在具有低k介电常数器件集成和高Ag含量焊料凸点的大型晶片封装中,采用不同的加热/冷却芯片连接工艺可以有效减少ULK层的断裂,防止C4凸点桥接。
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引用次数: 19
Design of a liquid bridge heat switch system based on the liquid bridge control for electronics cooling 基于液桥控制的电子冷却液桥热开关系统的设计
Pub Date : 2012-07-30 DOI: 10.1109/ECTC.2012.6249106
Su-Heon Jeong, W. Nakayama, Sung-Ki Nam, Sun-Kyu Lee
Recently, liquid bridge heat switch has been suggested as effective thermal management solutions for the various thermal problems. The liquid bridge heat switch can control the thermal resistance and the temperature of desired position by regulating the liquid bridge between objective areas. The liquid bridge heat switch system is composed of hot plate as an upper plate, cold plate as a lower plate, and actuators. “On” state demand, the supplied liquid generates liquid bridge between two plates and conducts heat from hot plate to cold plate. The amount of conducting heat and thermal resistance are controlled by the diameter and height of generated liquid bridge. To be an “Off” state, the generated liquid bridge is retrieved and ruptured eventually. At that time, the heat switch system has maximum thermal resistance. This result decreased conduction of heat. In order to realize the desired switch operation, the precise liquid bridge control is required. In this research, the liquid bridge behavior was studied to design the heat switch system. The effects of channel geometry and clearance on the liquid bridge behavior were verified and the liquid bridge rupture conditions were found out. Based on the investigation, the liquid bridge heat switch system was designed for the high power LED cooling system. In a series of experiment, the stable liquid bridge operation was achieved by designed channel geometry. The results also showed that proposed heat switch system was able to decrease the LED junction temperature and regulate the thermal resistance between hot and cold plate.
近年来,液体桥式热交换器被认为是解决各种热问题的有效方法。液桥热开关通过调节目标区域之间的液桥来控制热阻和期望位置的温度。液桥式热开关系统由热板为上板,冷板为下板和执行器组成。“接通”状态要求,供给的液体在两板之间产生液桥,并将热量从热板传导到冷板。导热量和热阻由生成液桥的直径和高度控制。在“关闭”状态下,生成的液桥被回收并最终破裂。此时,热交换系统具有最大的热阻。这一结果减少了热传导。为了实现理想的开关操作,需要精确的液桥控制。在本研究中,通过研究液桥特性来设计热交换系统。验证了通道几何形状和间隙对液桥性能的影响,找出了液桥破裂的条件。在此基础上,设计了用于大功率LED散热系统的液桥式热开关系统。在一系列的实验中,通过设计通道的几何形状,实现了稳定的液桥运行。结果还表明,该热开关系统能够降低LED结温,调节冷热板之间的热阻。
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引用次数: 1
Structural design, process, and reliability of a wafer-level 3D integration scheme with Cu TSVs based on micro-bump/adhesive hybrid wafer bonding 基于微凹凸/粘接混合晶圆键合的Cu tsv晶圆级三维集成方案的结构设计、工艺和可靠性
Pub Date : 2012-07-30 DOI: 10.1109/ECTC.2012.6248797
C. Ko, Z. Hsiao, Y. J. Chang, P. S. Chen, J. Huang, H. Fu, Y. J. Huang, C. Chiang, C. K. Lee, H. Chang, W. Tsai, Y. -. Chen, W. Lo, K. N. Chen
In this study, a wafer-level 3D integration scheme with Cu TSVs based on Cu/Sn micro-bump and BCB adhesive hybrid bonding is demonstrated. To realize the signal transmission effects in high speed digital signaling via Cu TSV and Cu/Sn micro-joint interconnection, the insertion loss was investigated by simulation analysis with variable TSV pitches, micro-bump diameters and chip thicknesses. Key technologies include TSV fabrication, micro-bumping, hybrid scheme making, hybrid bonding, wafer thinning and backside RDL formation were well developed and integrated to perform the 3D integration scheme. 5μm TSV, 10μm micro-bump, 20μm pitch, 40μm thin wafer, and 250°C low temperature W2W hybrid bonding have been successfully integrated in the integration platform. The 3D scheme was characterized and assessed to have excellent electrical performance and reliability, and is potentially to be applied for 3D product applications.
本文提出了一种基于Cu/Sn微凸点和BCB胶杂化键合的晶圆级三维集成方案。为了实现高速数字信号中Cu - TSV和Cu/Sn微接头互连的信号传输效果,通过仿真分析研究了不同TSV节距、微凸点直径和芯片厚度下的插入损耗。开发并集成了TSV制造、微碰撞、混合方案制作、混合键合、晶圆减薄和背面RDL形成等关键技术,实现了三维集成方案。5μm TSV、10μm微凸点、20μm间距、40μm薄晶片和250°C低温W2W杂化键合已成功集成在集成平台上。该方案具有优异的电气性能和可靠性,具有应用于3D产品的潜力。
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引用次数: 6
Investigation of the assembly reflow process and PCB design on the reliability of WLCSP 装配回流工艺及PCB设计对WLCSP可靠性的影响研究
Pub Date : 2012-07-30 DOI: 10.1109/ECTC.2012.6248952
Y. Liu, Qiuxiao Qian, S. Qu, S. Martin, O. Jeon
Intensive FEA modeling was applied to the investigation of early solder joint failures of WLCSP mounted on test PCBs. In particular, stress in assembly reflow process was studied with 25 balls; 0.4 mm pitch WLCSP and PCBs with specially placed plated though vias. The 25 ball WLCSP in the study has 5×5 ball array, which corresponds to 16 outmost solder joints and nine inner solder joints, all soldered to the matching copper pads on the test PCB. Three PCB designs were modeled to understand the impact of PCB through via arrangement on stresses in solder joints during assembly reflow process: design #1 has no PCB through vias at all; design #2 has plated through vias under nine inner PCB copper pads; design #3 has plated through vias under all 25 PCB copper pads. The modeling results disclose that PCB design #2 with plated through vias under nine inner PCB copper pads induces the highest solder stress in all three models. Contrary to common sense of higher stress on corner solder joints due to coefficient of thermal expansion (CTE) mismatch of silicon and PCB, the maximum stresses of design #2 actually occur on the inner solder joints. The simulation results match well with experimental observations. For PCB design #1 and #3, highest solder stress is lower than stress in design #2. In addition, in both cases, the maximum stress locates on the corner solder joints. New PCB design guidelines have since been implemented based on the simulation. Due to the improvement of the design, premature solder joint failure has not been recorded.
采用深入的有限元分析方法,对安装在测试电路板上的WLCSP的早期焊点失效进行了研究。特别研究了25个钢球在装配回流过程中的应力;0.4毫米间距的WLCSP和pcb,特别放置的电镀通孔。研究中的25球WLCSP具有5×5球阵,对应16个最外焊点和9个内焊点,全部焊接到测试PCB上匹配的铜垫上。我们对三种PCB设计进行了建模,以了解PCB通孔布置对组装回流过程中焊点应力的影响:设计#1根本没有PCB通孔;设计#2在九个内部PCB铜衬垫下镀有通孔;设计#3在所有25个PCB铜衬垫下镀过孔。建模结果表明,PCB设计#2在九个内部PCB铜衬垫下镀通孔,在所有三种模型中产生最高的焊接应力。通常情况下,由于硅和PCB的热膨胀系数(CTE)不匹配,转角焊点的应力较高,而设计#2的最大应力实际上发生在内部焊点上。仿真结果与实验结果吻合较好。对于PCB设计#1和#3,最高焊料应力低于设计#2中的应力。此外,在这两种情况下,最大应力位于拐角焊点上。新的PCB设计准则已经基于仿真实现。由于设计的改进,没有记录过早的焊点失效。
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引用次数: 2
Systematic investigation of Sn-Ag and Sn-Cu modified by minor alloying element of titanium 微量合金元素钛改性Sn-Ag和Sn-Cu的系统研究
Pub Date : 2012-07-30 DOI: 10.1109/ECTC.2012.6248913
W. Chen, S. Kang, C. Kao
Reliability issues of Pb-free solder joints used in microelectronic interconnects, such as BGA, flip-chip, or even 3D-IC, are becoming more critical recently when high performance electronic systems demand more rigorous reliability requirements. The selection of new solder materials has been an important topic in order to enhance the reliability of Pb-free solder joints. In the past few years, numerous studies have been conducted on the beneficial effects of minor alloying elements, including Co, Cu, Fe, Ni, Zn and others, into Sn-rich Pb-free solders [1-6]. Only recently have Liu et al. [7] first reported the beneficial effect of Ti in SAC (Sn-Ag-Cu) solder for BGA applications with superior drop-impact performance. Getting such a superior drop-impact performance usually compromises high temperature mechanical properties such as creep resistance. But they found SAC-Ti having enhanced drop-impact performance without sacrificing a good creep property. Improving simultaneously these two mechanical properties was regarded as an excellent achievement of SAC-Ti. Moreover, considerable suppression of the undercooling and retardation of interfacial IMCs were also reported owing to the addition of Ti to SAC. Nevertheless, V. Vuorinen and his coworkers [8] lately reported the result of a thermal aging experiment on SnAg solder modified with Ti and asserted that the minor addition of Ti cannot change the activities of components nor influence the stability of the IMC layers. This study did not support the beneficial effects of minor alloying addition of Ti in SAC of the previous report [7]. Hence, it is essential to clarify the effect of Ti-addition on Sn-rich solders by further investigation. The objectives of our present work are (a) to understand the intrinsic consequence of Ti-addition on Sn-Ag and Sn-Cu solders, (b) to observe whether Ti-addition can influence the interfacial reactions between solders and under-bump metallurgies (UBMs), and (c) to reveal the contribution of Ti-addition on any other reliability performance, such as electro-migration (EM) resistance. In this study, two Ti-added Sn-Ag and Sn-Cu solders were commercially prepared; Sn-1.0Ag-0.2Ti (wt.%) and Sn-0.7Cu-0.2Ti (wt.%) in the form of solder ingots. They were cut into small pieces and evaluated for their metallurgical properties and interfacial reactions with Cu and Ni UBMs. Pure Sn-1.0Ag (wt.%) and Sn-0.7Cu (wt.%) were also prepared in the form of solder balls as control samples. DSC (differential scanning calorimetry) analysis was used to study the melting/solidification behavior of Ti-added solders. It was confirmed that a small amount of Ti addition can effectively reduce the undercooling to a few degrees, while a large undercooling is persistent in Sn-Ag or Sn-Cu solders without Ti addition. It is worth noting that a small undercooling can lessen a possibility of non-uniform solidification among many neighboring solder joints during reflow, which is beneficial for joint integ
当高性能电子系统需要更严格的可靠性要求时,用于微电子互连(如BGA,倒装芯片甚至3D-IC)的无铅焊点的可靠性问题变得越来越重要。为了提高无铅焊点的可靠性,新型焊料的选择一直是一个重要的课题。近年来,人们对Co、Cu、Fe、Ni、Zn等少量合金元素在富锡无铅钎料中的有益作用进行了大量研究[1-6]。直到最近,Liu等人[7]才首次报道了SAC (Sn-Ag-Cu)焊料中Ti对BGA应用的有益作用,具有优越的跌落冲击性能。获得如此优异的跌落冲击性能通常会损害高温机械性能,如抗蠕变性能。但他们发现SAC-Ti在不牺牲良好蠕变性能的情况下提高了跌落冲击性能。同时提高这两种力学性能被认为是SAC-Ti的一项优异成就。此外,还报道了在SAC中加入Ti对界面IMCs过冷性和迟滞性的显著抑制。然而,V. Vuorinen和他的同事[8]最近报道了用Ti改性SnAg焊料的热老化实验结果,并断言少量添加Ti不会改变组分的活性,也不会影响IMC层的稳定性。本研究不支持之前报道的在SAC中少量添加Ti合金的有益效果[7]。因此,有必要通过进一步的研究来阐明添加钛对富锡焊料的影响。我们目前工作的目标是(a)了解添加ti对Sn-Ag和Sn-Cu焊料的内在影响,(b)观察添加ti是否会影响焊料与凹凸下冶金(ubm)之间的界面反应,以及(c)揭示添加ti对任何其他可靠性性能的贡献,例如电迁移(EM)电阻。本研究制备了两种添加ti的Sn-Ag和Sn-Cu钎料;Sn-1.0Ag-0.2Ti (wt.%)和Sn-0.7Cu-0.2Ti (wt.%)焊锡锭。它们被切成小块,并评估了它们的冶金性能和与Cu和Ni UBMs的界面反应。同时制备了纯Sn-1.0Ag (wt.%)和Sn-0.7Cu (wt.%)作为对照样品。采用DSC(差示扫描量热法)分析研究了添加ti钎料的熔化/凝固行为。结果表明,少量加入Ti可有效降低过冷度,而未加入Ti的Sn-Ag或Sn-Cu钎料过冷度较大。值得注意的是,较小的过冷度可以减少回流过程中相邻焊点之间不均匀凝固的可能性,有利于焊点的完整性和可靠性。一些焊锡样品也通过注射成型焊锡(IMS)工艺以小型焊锡瓶的形式生产[9],该工艺是IBM晶圆碰撞技术C4NP的前身。然后将部分焊料筒暴露在200℃下进行高温时效实验。对于添加ti的钎料,Ti2Sn3网络可以通过抑制其晶粒生长来稳定β-Sn的形貌,这意味着它们可能是抵抗EM破坏和保持钎料高温强度的良好候选者。测定了高温时效试样的显微硬度,显示了硬度随时效时间的变化趋势。不同钎料与不同UBM之间的界面反应显示了Ti添加量对界面IMCs形成的影响。对于回流样品(240°C, 1 min),当Sn-Ag-Ti和Sn-Cu-Ti焊料与Cu UBM反应时,观察到界面Cu6Sn5的显著阻滞。然而,Ti的加入似乎对阻碍Cu3Sn的形成没有那么有效。当Sn-Cu-Ti钎料与Ni反应时,界面IMC (Cu, Ni)6Sn5也受到阻碍。当Sn-Ag-Ti钎料在Ni上进行回流过程时,Ni3Sn4在界面处形成一层平衡IMC, Ti的加入意外地加速了Ni3Sn4的形成。本研究还将讨论钛浓度效应和不同IMCs的固态生长动力学。在未来的研究中,我们将通过在电磁应力作用下提供均匀电流密度的铜丝模型来评估添加ti对Sn-Ag和Sn-Cu焊点电迁移性能的影响。
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引用次数: 1
期刊
2012 IEEE 62nd Electronic Components and Technology Conference
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