Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248899
C. Taylor, S. Sitaraman
With increasing importance of 3D packaging systems, more and more dies will be stacked on top of each other and connected using through silicon vias (TSVs) and solder bumps. In-situ stress measurements near these bump pads are important to help understand the evolution of die stresses associated with the packaging process. Unlike piezoresistive doped Si sensors that require high-temperature processing, metal-based sensors use low-temperature fabrication processes. The sensor fabrication uses standard cleanroom processes such as UV lithography and physical vapor deposition. In this paper, thin-film micro-scale metallic (Ni/Cr) resistors have been studied with different design dimensions including gauge width, film thickness, and spacing between the lines in the serpentine pattern. Silicon test strips with sensors have been subjected to four-point bend testing, and finite-element simulations have been carried out to mimic the four-point bend testing as well as to determine stress contours where the sensors are placed.
{"title":"In-situ strain measurement with metallic thin film sensors","authors":"C. Taylor, S. Sitaraman","doi":"10.1109/ECTC.2012.6248899","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248899","url":null,"abstract":"With increasing importance of 3D packaging systems, more and more dies will be stacked on top of each other and connected using through silicon vias (TSVs) and solder bumps. In-situ stress measurements near these bump pads are important to help understand the evolution of die stresses associated with the packaging process. Unlike piezoresistive doped Si sensors that require high-temperature processing, metal-based sensors use low-temperature fabrication processes. The sensor fabrication uses standard cleanroom processes such as UV lithography and physical vapor deposition. In this paper, thin-film micro-scale metallic (Ni/Cr) resistors have been studied with different design dimensions including gauge width, film thickness, and spacing between the lines in the serpentine pattern. Silicon test strips with sensors have been subjected to four-point bend testing, and finite-element simulations have been carried out to mimic the four-point bend testing as well as to determine stress contours where the sensors are placed.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"33 1","pages":"641-646"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89149470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248975
H. Abe, Dong Kang, T. Yamamoto, T. Yagihashi, Y. Endo, H. Saito, T. Horie, H. Tamate, Y. Ejiri, N. Watanabe, T. Iwasaki
Cu wire is drastically replacing Au wire due to surge of Au price. However, Cu wire package has poorer humidity reliability than Au wire package. Although Pd coated Cu wire package could show better humidity reliability than Cu wire, it is still worse than Au. Enough information regarding failure mechanism was not available. For failure analysis, x-section has been widely used to identify the Cu/Al IMC after failure. However, the x-section is the results of corrosion reaction and doesn't show the IMC status before corrosion. Therefore, the failure mechanism could not be estimated precisely. We used chemical model simulation to predict what kinds of IMC could be created after wire bonding, then which IMC could be corroded more easily during HAST. The Desorption energy was used to estimate reactivity between specified Cu/Al IMC and chlorine ion. The simulation suggested that the formation of Cu rich and Cu poor Cu/Al IMC and the Cu rich IMC was estimated to be corroded by chlorine ion. These chemical model simulations are the effective way to have fundamental understanding of the mechanism of Cu/Al IMC corrosion. Furthermore, chemical model simulation for Pd coated Cu wire was done to explore the effect of Pd existence and distribution of Pd in Cu/Al IMC. Dispersed Pd contributed to create new IMC of Cu/Al/Pd instead of easily corroded Cu rich Cu/Al IMC. Cu and Al diffusion and also Cl ion diffusion were inhibited by Pd at surface. Even Cl ion catching effect by Pd is also discussed. To improve humidity reliability performance with Cu wire, we developed new ion trapper using chemical model simulation technique. Developed molding compounds with the ion trapper showed significant improvement at bias HAST with Cu wire, which was even better than conventional Cu wire compatible molding compounds.
{"title":"Cu wire and Pd-Cu wire package reliability and molding compounds","authors":"H. Abe, Dong Kang, T. Yamamoto, T. Yagihashi, Y. Endo, H. Saito, T. Horie, H. Tamate, Y. Ejiri, N. Watanabe, T. Iwasaki","doi":"10.1109/ECTC.2012.6248975","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248975","url":null,"abstract":"Cu wire is drastically replacing Au wire due to surge of Au price. However, Cu wire package has poorer humidity reliability than Au wire package. Although Pd coated Cu wire package could show better humidity reliability than Cu wire, it is still worse than Au. Enough information regarding failure mechanism was not available. For failure analysis, x-section has been widely used to identify the Cu/Al IMC after failure. However, the x-section is the results of corrosion reaction and doesn't show the IMC status before corrosion. Therefore, the failure mechanism could not be estimated precisely. We used chemical model simulation to predict what kinds of IMC could be created after wire bonding, then which IMC could be corroded more easily during HAST. The Desorption energy was used to estimate reactivity between specified Cu/Al IMC and chlorine ion. The simulation suggested that the formation of Cu rich and Cu poor Cu/Al IMC and the Cu rich IMC was estimated to be corroded by chlorine ion. These chemical model simulations are the effective way to have fundamental understanding of the mechanism of Cu/Al IMC corrosion. Furthermore, chemical model simulation for Pd coated Cu wire was done to explore the effect of Pd existence and distribution of Pd in Cu/Al IMC. Dispersed Pd contributed to create new IMC of Cu/Al/Pd instead of easily corroded Cu rich Cu/Al IMC. Cu and Al diffusion and also Cl ion diffusion were inhibited by Pd at surface. Even Cl ion catching effect by Pd is also discussed. To improve humidity reliability performance with Cu wire, we developed new ion trapper using chemical model simulation technique. Developed molding compounds with the ion trapper showed significant improvement at bias HAST with Cu wire, which was even better than conventional Cu wire compatible molding compounds.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"99 1","pages":"1117-1123"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88974218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248949
Cheolbok Kim, Kyung-Hoon Lee, Sangrok Lee, Kyoung-Tae Kim, Y. Yoon
A high gain patch antenna with a four-leaf clover shape metamaterial slab on top is implemented using the combination of multiple ceramic and organic layers for global positioning system (GPS) applications. The four-leaf clover shape metamaterial slab showing a refractive index of zero or close to zero is designed for high gain antenna applications. An effective refractive index of 0.5 is obtained for a designed architecture. As a source antenna, a circularly polarized rectangular patch antenna is implemented with two diagonal corners truncated. The demonstrated architecture not only increases the antenna gain, but also maintains the circular polarization. The antenna size is reduced by using a high dielectric constant ceramic substrate, where the overall antenna size is as small as 25 × 25 × 4 mm3. It is surface mountable and has circular polarization with a center frequency of 1.58 GHz, and a gain of 4.48 dB.
{"title":"A surface micromachined high directivity GPS patch antenna with a four-leaf clover shape metamaterial slab","authors":"Cheolbok Kim, Kyung-Hoon Lee, Sangrok Lee, Kyoung-Tae Kim, Y. Yoon","doi":"10.1109/ECTC.2012.6248949","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248949","url":null,"abstract":"A high gain patch antenna with a four-leaf clover shape metamaterial slab on top is implemented using the combination of multiple ceramic and organic layers for global positioning system (GPS) applications. The four-leaf clover shape metamaterial slab showing a refractive index of zero or close to zero is designed for high gain antenna applications. An effective refractive index of 0.5 is obtained for a designed architecture. As a source antenna, a circularly polarized rectangular patch antenna is implemented with two diagonal corners truncated. The demonstrated architecture not only increases the antenna gain, but also maintains the circular polarization. The antenna size is reduced by using a high dielectric constant ceramic substrate, where the overall antenna size is as small as 25 × 25 × 4 mm3. It is surface mountable and has circular polarization with a center frequency of 1.58 GHz, and a gain of 4.48 dB.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"18 1","pages":"942-947"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86912859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248951
Y. H. Lin, F. Kuo, Y. F. Chen, C. Ho, J. Y. Lai, S. Chen, F. Chien, R. Lee, J. Lau
Ball mount technology uses performed solder spheres dropping through a metal template onto wafer at once. This technology is directly producing bumps on wafer with high throughput and consistent bump results. Ball mounting process without using electroplating decreases cost and chemical pollution. This technique is applicable for many applications but several issues associated with this technology that limits its widespread use in high volume and high yield applications. These limitations include: (1) a practical lower limit to the size of sphere that can be dropped, and (2) the stencil between the performed solder spheres and the wafer can fail, causing a release of all the spheres into the tool (often referred to as bursts or escapes), and the yields are statistically low. To meet high I/O density IC request, the trend of wafer level chip scale package (WLCSP) I/O pad distributed design is toward to reduce the I/O pitch and increase the I/O density, and therefore impact solder ball size application of ball mount process, WLCSP micro-ball mount technology is requested. In this study, a low-cost and fine-pitch micro-ball mounting technology is developed. Emphasis is placed on determining the most important factors such as accurate dropping parameters, stencil quality and reflow conditions for microball mounting design, materials, and process. Three different ball sizes are considered: 70μm, 100μm, and 250μm. Their corresponding pitches are 130μm, 180μm, and 400μm. WLCSP micro balls with diameter = 70μm and pitch = 130μm on 300mm wafers (with ~2KK I/Os) have been successful produced. The yield is more than 99.99% without any missing micro ball and bridging.
球贴装技术使用焊料球体通过金属模板一次性滴到晶圆上。该技术直接在晶圆上产生凸点，具有高通量和一致的凸点结果。不使用电镀的滚珠安装工艺降低了成本和化学污染。该技术适用于许多应用，但与该技术相关的几个问题限制了其在大批量和高产量应用中的广泛应用。这些限制包括:(1)可以掉落的球体尺寸的实际下限，(2)所执行的焊接球体和晶圆之间的模板可能失效，导致所有球体释放到工具中(通常称为爆裂或逃逸)，并且产量在统计上很低。为了满足高I/O密度集成电路的要求，晶圆级芯片规模封装(WLCSP) I/O焊盘分布式设计的趋势是减小I/O间距和增加I/O密度，因此影响滚珠安装工艺中焊球尺寸的应用，要求采用WLCSP微滚珠安装技术。本研究开发了一种低成本、小间距的微球安装技术。重点放在确定最重要的因素，如准确的下降参数，模板质量和回流条件的微球安装设计，材料和工艺。滚珠尺寸分为70μm、100μm和250μm。分别为130μm、180μm和400μm。在300mm晶圆(I/ o ~2KK)上成功制备了直径为70μm、节距为130μm的WLCSP微球。产率大于99.99%，无微球丢失和桥接现象。
{"title":"Low-cost and fine-pitch micro-ball mounting technology for WLCSP","authors":"Y. H. Lin, F. Kuo, Y. F. Chen, C. Ho, J. Y. Lai, S. Chen, F. Chien, R. Lee, J. Lau","doi":"10.1109/ECTC.2012.6248951","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248951","url":null,"abstract":"Ball mount technology uses performed solder spheres dropping through a metal template onto wafer at once. This technology is directly producing bumps on wafer with high throughput and consistent bump results. Ball mounting process without using electroplating decreases cost and chemical pollution. This technique is applicable for many applications but several issues associated with this technology that limits its widespread use in high volume and high yield applications. These limitations include: (1) a practical lower limit to the size of sphere that can be dropped, and (2) the stencil between the performed solder spheres and the wafer can fail, causing a release of all the spheres into the tool (often referred to as bursts or escapes), and the yields are statistically low. To meet high I/O density IC request, the trend of wafer level chip scale package (WLCSP) I/O pad distributed design is toward to reduce the I/O pitch and increase the I/O density, and therefore impact solder ball size application of ball mount process, WLCSP micro-ball mount technology is requested. In this study, a low-cost and fine-pitch micro-ball mounting technology is developed. Emphasis is placed on determining the most important factors such as accurate dropping parameters, stencil quality and reflow conditions for microball mounting design, materials, and process. Three different ball sizes are considered: 70μm, 100μm, and 250μm. Their corresponding pitches are 130μm, 180μm, and 400μm. WLCSP micro balls with diameter = 70μm and pitch = 130μm on 300mm wafers (with ~2KK I/Os) have been successful produced. The yield is more than 99.99% without any missing micro ball and bridging.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"18 1","pages":"953-958"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86935464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248983
L. Kai, L. Hung, L. Wu, Chiang Yeh Men, D. Jiang, Chun-An Huang, Yu Po Wang
In semiconductor packaging, wire bonding is the main technology for electrical connections between chip and leadframe or substrate. Gold wire bonding has the advantages of a fast bonding process, excellent electrical property and stable chemical property. It has been widely used in various electronic packages. Gold prices have been raised significantly over the last few years. Many manufactures have been investigating ways to replace the conventional gold wire with various new materials. Copper wire bonding is an alternative interconnection technology. Cu wire has superior electrical and thermal conductivities as well as higher tensile strength, elongation and better “ball neck” strength. On the other hand, the higher hardness of Cu wire requires higher ultrasonic power and bonding force, which lead to high risk of cratering for ball bonding and tearing for wedge bonding. These will cause some package limitation and wire bonder machine downtime or low units per hour (UPH). Ag alloy wire has low Young's modulus and hardness property. It is a low cost wire bonding solution other than gold wire. In this study, Ag alloy wire is proposed as an alternative to Au bonding wire. Emphasis is placed on the wire bonding workability and reliability of using Ag-Au-Pd alloy wire for TSOP package. Also, wire bonding parameter such as electronic flame off (EFO), bond force, ultrasonic power, heat block temperature and time for ball and wedge bonding are optimized. Furthermore, the response for parameter optimization is determined by the Dage bond tester. Package reliability is determined through environmental tests that include pressure cooker test (PCT), temperature cycle test (TCT) and high temperature storage life test (HTSL). The tested samples were studied by focused ion beam (FIB), scanning electron microscopy (SEM) and energy dispersive spectrometer analyses (EDS). Intermetallic compound growth behavior during reliability test is characterized and compared to Al-Au and Al-Cu systems. Ag-Al didn't have excessive volume variation and void occurrence to get better bonding performance during various reliability tests.
{"title":"Silver alloy wire bonding","authors":"L. Kai, L. Hung, L. Wu, Chiang Yeh Men, D. Jiang, Chun-An Huang, Yu Po Wang","doi":"10.1109/ECTC.2012.6248983","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248983","url":null,"abstract":"In semiconductor packaging, wire bonding is the main technology for electrical connections between chip and leadframe or substrate. Gold wire bonding has the advantages of a fast bonding process, excellent electrical property and stable chemical property. It has been widely used in various electronic packages. Gold prices have been raised significantly over the last few years. Many manufactures have been investigating ways to replace the conventional gold wire with various new materials. Copper wire bonding is an alternative interconnection technology. Cu wire has superior electrical and thermal conductivities as well as higher tensile strength, elongation and better “ball neck” strength. On the other hand, the higher hardness of Cu wire requires higher ultrasonic power and bonding force, which lead to high risk of cratering for ball bonding and tearing for wedge bonding. These will cause some package limitation and wire bonder machine downtime or low units per hour (UPH). Ag alloy wire has low Young's modulus and hardness property. It is a low cost wire bonding solution other than gold wire. In this study, Ag alloy wire is proposed as an alternative to Au bonding wire. Emphasis is placed on the wire bonding workability and reliability of using Ag-Au-Pd alloy wire for TSOP package. Also, wire bonding parameter such as electronic flame off (EFO), bond force, ultrasonic power, heat block temperature and time for ball and wedge bonding are optimized. Furthermore, the response for parameter optimization is determined by the Dage bond tester. Package reliability is determined through environmental tests that include pressure cooker test (PCT), temperature cycle test (TCT) and high temperature storage life test (HTSL). The tested samples were studied by focused ion beam (FIB), scanning electron microscopy (SEM) and energy dispersive spectrometer analyses (EDS). Intermetallic compound growth behavior during reliability test is characterized and compared to Al-Au and Al-Cu systems. Ag-Al didn't have excessive volume variation and void occurrence to get better bonding performance during various reliability tests.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"12 1","pages":"1163-1168"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90569361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249116
Fei Chen, Kai Wang, Sheng Liu
In this paper, we analyze the optical features of different LED packaging types in forward-lighting application. There are generally two packaging types: point source and line source. For the two different packaging types, we introduce several high-efficient supporting opticses in forward-lighting application.
{"title":"High-efficient optics for different LED packaging types in forward-lighting application","authors":"Fei Chen, Kai Wang, Sheng Liu","doi":"10.1109/ECTC.2012.6249116","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249116","url":null,"abstract":"In this paper, we analyze the optical features of different LED packaging types in forward-lighting application. There are generally two packaging types: point source and line source. For the two different packaging types, we introduce several high-efficient supporting opticses in forward-lighting application.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"26 1","pages":"2013-2017"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86071560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248945
T. Watanabe, S. Yamamichi
We have developed a U-shaped magnetic shield for packaging perpendicular magnetoresistive random access memories (MRAMs) and have determined that a non-oriented silicon steel is best suited for this shield in terms of fabrication and magnetic properties. Use of this shield material suppressed magnetic flux saturation for an external magnetic field of up to 300[Oe], which exceeds the target of 250[Oe]. A magnetic source can thus be placed as close as 1 cm to a shielded MRAM. An MRAM chip is packaged by separating the shield into two parts and then mounting the lower part, the chip, and the upper part in sequence. If the gap between the parts is 20[μm] and the permeability of the gap is 30, the target performance is still achieved. This shield is thus promising for high-speed, low-power MRAMs.
{"title":"A novel U-shaped magnetic shield for perpendicular MRAM","authors":"T. Watanabe, S. Yamamichi","doi":"10.1109/ECTC.2012.6248945","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248945","url":null,"abstract":"We have developed a U-shaped magnetic shield for packaging perpendicular magnetoresistive random access memories (MRAMs) and have determined that a non-oriented silicon steel is best suited for this shield in terms of fabrication and magnetic properties. Use of this shield material suppressed magnetic flux saturation for an external magnetic field of up to 300[Oe], which exceeds the target of 250[Oe]. A magnetic source can thus be placed as close as 1 cm to a shielded MRAM. An MRAM chip is packaged by separating the shield into two parts and then mounting the lower part, the chip, and the upper part in sequence. If the gap between the parts is 20[μm] and the permeability of the gap is 30, the target performance is still achieved. This shield is thus promising for high-speed, low-power MRAMs.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"34 1","pages":"920-925"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73883245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248933
S. Sheu, Z. H. Lin, C. S. Lin, J. Lau, S. H. Lee, K. Su, T. Ku, S. H. Wu, J. Hung, P. S. Chen, S. Lai, W. Lo, M. Kao
In this study, an on chip bus driver TEG (test element group) has been developed for the data transmission performance at TSVs for 3D IC integration. The on chip bus driver TEG consists of transceiver (TX), receiver (RX) and TSV group which has 2, 4 and 8 TSVs for the analysis of the TSV transmission performance with different load effects which are caused by different number (2, 4, and 8) of chip stack (each chip is with one TSV). This chip has been made by TSMC's 0.18μm process (FEOL) and ITRI's BEOL process. The square chip area is 1.69mm2 and power supply voltage is 1.8V with 30μm diameter TSVs on 30μm pitch and 100μm depth. Finally, a design guide line and a test tool will be proposed with the present on chip bus TEG.
{"title":"Electrical characterization of through silicon vias (TSVs) with an on chip bus driver for 3D IC integration","authors":"S. Sheu, Z. H. Lin, C. S. Lin, J. Lau, S. H. Lee, K. Su, T. Ku, S. H. Wu, J. Hung, P. S. Chen, S. Lai, W. Lo, M. Kao","doi":"10.1109/ECTC.2012.6248933","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248933","url":null,"abstract":"In this study, an on chip bus driver TEG (test element group) has been developed for the data transmission performance at TSVs for 3D IC integration. The on chip bus driver TEG consists of transceiver (TX), receiver (RX) and TSV group which has 2, 4 and 8 TSVs for the analysis of the TSV transmission performance with different load effects which are caused by different number (2, 4, and 8) of chip stack (each chip is with one TSV). This chip has been made by TSMC's 0.18μm process (FEOL) and ITRI's BEOL process. The square chip area is 1.69mm2 and power supply voltage is 1.8V with 30μm diameter TSVs on 30μm pitch and 100μm depth. Finally, a design guide line and a test tool will be proposed with the present on chip bus TEG.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"46 1","pages":"851-856"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73342849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248837
M. Nimura, A. Shigetou, K. Sakuma, H. Ogino, T. Enomoto, J. Mizuno, S. Shoji
We developed a novel hybrid bonding technology for Au ultralow-profiled bumps and underfill resin with a modified “lock-and-key structure.” The lock structure interlocks with the key structure. We applied these structures to perform an entire adhesion between the mating surfaces in place of conventional underfilling technique. To fabricate the key structure, we developed a simple process that can remove resin on the bumps. Lock structure was fabricated by photolithography and dry etching. After the bonding was carried out, the bonded interface was observed with a Scanning Electron Microscope (SEM), a transmission electron microscope (TEM) and a Scanning Acoustic Microscope (SAM). The results proved that no significant gap was existed at both Au-Au and resin-resin interface. Furthermore, the shear strength of the bonded sample with resin was ten times stronger than that without resin. The conduction of Au bump connections after hybrid bonding was also confirmed.
{"title":"Hybrid Au-underfill resin bonding with lock-and-key structure","authors":"M. Nimura, A. Shigetou, K. Sakuma, H. Ogino, T. Enomoto, J. Mizuno, S. Shoji","doi":"10.1109/ECTC.2012.6248837","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248837","url":null,"abstract":"We developed a novel hybrid bonding technology for Au ultralow-profiled bumps and underfill resin with a modified “lock-and-key structure.” The lock structure interlocks with the key structure. We applied these structures to perform an entire adhesion between the mating surfaces in place of conventional underfilling technique. To fabricate the key structure, we developed a simple process that can remove resin on the bumps. Lock structure was fabricated by photolithography and dry etching. After the bonding was carried out, the bonded interface was observed with a Scanning Electron Microscope (SEM), a transmission electron microscope (TEM) and a Scanning Acoustic Microscope (SAM). The results proved that no significant gap was existed at both Au-Au and resin-resin interface. Furthermore, the shear strength of the bonded sample with resin was ten times stronger than that without resin. The conduction of Au bump connections after hybrid bonding was also confirmed.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"16 1","pages":"258-262"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74849052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248874
Tae-Kyu Lee, Hongtao Ma
Isothermal aging effects on lead-free solders have been extensively investigated in recent studies for both bulk solders and package solder joints. Researches show that aging significantly degrades the mechanical properties of bulk lead-free solders and dynamic performances of lead-free solder joints. There are studies exploring the impact of aging on accelerated thermal cycling (ATC) performance of lead-free solder joints, however, the results are discrepant, some research shows minimal impact of isothermal aging on long term ATC performances since most of the failure mode are not related to intermetallic (IMC) growth which has been impacted more significantly during aging. Some others show significant degradation of the of ATC life due to evidence of weakening of solder joints after aging. This study is intended to explore the factors that may affect the aging impact on the lead-free solder joint fatigue life. The test vehicle is designed with different package types, pitch sizes, and solder alloy metallurgies to capture the impact of affecting factors. The test vehicles have been aged at 100°C and 150°C for different aging durations, ATC test were subsequently performed on the aged samples and with the non aged samples as control. The effects of aging on the fatigue life of lead-free solder joints are extensively explored in this study.
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