Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248899
C. Taylor, S. Sitaraman
With increasing importance of 3D packaging systems, more and more dies will be stacked on top of each other and connected using through silicon vias (TSVs) and solder bumps. In-situ stress measurements near these bump pads are important to help understand the evolution of die stresses associated with the packaging process. Unlike piezoresistive doped Si sensors that require high-temperature processing, metal-based sensors use low-temperature fabrication processes. The sensor fabrication uses standard cleanroom processes such as UV lithography and physical vapor deposition. In this paper, thin-film micro-scale metallic (Ni/Cr) resistors have been studied with different design dimensions including gauge width, film thickness, and spacing between the lines in the serpentine pattern. Silicon test strips with sensors have been subjected to four-point bend testing, and finite-element simulations have been carried out to mimic the four-point bend testing as well as to determine stress contours where the sensors are placed.
{"title":"In-situ strain measurement with metallic thin film sensors","authors":"C. Taylor, S. Sitaraman","doi":"10.1109/ECTC.2012.6248899","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248899","url":null,"abstract":"With increasing importance of 3D packaging systems, more and more dies will be stacked on top of each other and connected using through silicon vias (TSVs) and solder bumps. In-situ stress measurements near these bump pads are important to help understand the evolution of die stresses associated with the packaging process. Unlike piezoresistive doped Si sensors that require high-temperature processing, metal-based sensors use low-temperature fabrication processes. The sensor fabrication uses standard cleanroom processes such as UV lithography and physical vapor deposition. In this paper, thin-film micro-scale metallic (Ni/Cr) resistors have been studied with different design dimensions including gauge width, film thickness, and spacing between the lines in the serpentine pattern. Silicon test strips with sensors have been subjected to four-point bend testing, and finite-element simulations have been carried out to mimic the four-point bend testing as well as to determine stress contours where the sensors are placed.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89149470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248975
H. Abe, Dong Kang, T. Yamamoto, T. Yagihashi, Y. Endo, H. Saito, T. Horie, H. Tamate, Y. Ejiri, N. Watanabe, T. Iwasaki
Cu wire is drastically replacing Au wire due to surge of Au price. However, Cu wire package has poorer humidity reliability than Au wire package. Although Pd coated Cu wire package could show better humidity reliability than Cu wire, it is still worse than Au. Enough information regarding failure mechanism was not available. For failure analysis, x-section has been widely used to identify the Cu/Al IMC after failure. However, the x-section is the results of corrosion reaction and doesn't show the IMC status before corrosion. Therefore, the failure mechanism could not be estimated precisely. We used chemical model simulation to predict what kinds of IMC could be created after wire bonding, then which IMC could be corroded more easily during HAST. The Desorption energy was used to estimate reactivity between specified Cu/Al IMC and chlorine ion. The simulation suggested that the formation of Cu rich and Cu poor Cu/Al IMC and the Cu rich IMC was estimated to be corroded by chlorine ion. These chemical model simulations are the effective way to have fundamental understanding of the mechanism of Cu/Al IMC corrosion. Furthermore, chemical model simulation for Pd coated Cu wire was done to explore the effect of Pd existence and distribution of Pd in Cu/Al IMC. Dispersed Pd contributed to create new IMC of Cu/Al/Pd instead of easily corroded Cu rich Cu/Al IMC. Cu and Al diffusion and also Cl ion diffusion were inhibited by Pd at surface. Even Cl ion catching effect by Pd is also discussed. To improve humidity reliability performance with Cu wire, we developed new ion trapper using chemical model simulation technique. Developed molding compounds with the ion trapper showed significant improvement at bias HAST with Cu wire, which was even better than conventional Cu wire compatible molding compounds.
{"title":"Cu wire and Pd-Cu wire package reliability and molding compounds","authors":"H. Abe, Dong Kang, T. Yamamoto, T. Yagihashi, Y. Endo, H. Saito, T. Horie, H. Tamate, Y. Ejiri, N. Watanabe, T. Iwasaki","doi":"10.1109/ECTC.2012.6248975","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248975","url":null,"abstract":"Cu wire is drastically replacing Au wire due to surge of Au price. However, Cu wire package has poorer humidity reliability than Au wire package. Although Pd coated Cu wire package could show better humidity reliability than Cu wire, it is still worse than Au. Enough information regarding failure mechanism was not available. For failure analysis, x-section has been widely used to identify the Cu/Al IMC after failure. However, the x-section is the results of corrosion reaction and doesn't show the IMC status before corrosion. Therefore, the failure mechanism could not be estimated precisely. We used chemical model simulation to predict what kinds of IMC could be created after wire bonding, then which IMC could be corroded more easily during HAST. The Desorption energy was used to estimate reactivity between specified Cu/Al IMC and chlorine ion. The simulation suggested that the formation of Cu rich and Cu poor Cu/Al IMC and the Cu rich IMC was estimated to be corroded by chlorine ion. These chemical model simulations are the effective way to have fundamental understanding of the mechanism of Cu/Al IMC corrosion. Furthermore, chemical model simulation for Pd coated Cu wire was done to explore the effect of Pd existence and distribution of Pd in Cu/Al IMC. Dispersed Pd contributed to create new IMC of Cu/Al/Pd instead of easily corroded Cu rich Cu/Al IMC. Cu and Al diffusion and also Cl ion diffusion were inhibited by Pd at surface. Even Cl ion catching effect by Pd is also discussed. To improve humidity reliability performance with Cu wire, we developed new ion trapper using chemical model simulation technique. Developed molding compounds with the ion trapper showed significant improvement at bias HAST with Cu wire, which was even better than conventional Cu wire compatible molding compounds.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88974218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248949
Cheolbok Kim, Kyung-Hoon Lee, Sangrok Lee, Kyoung-Tae Kim, Y. Yoon
A high gain patch antenna with a four-leaf clover shape metamaterial slab on top is implemented using the combination of multiple ceramic and organic layers for global positioning system (GPS) applications. The four-leaf clover shape metamaterial slab showing a refractive index of zero or close to zero is designed for high gain antenna applications. An effective refractive index of 0.5 is obtained for a designed architecture. As a source antenna, a circularly polarized rectangular patch antenna is implemented with two diagonal corners truncated. The demonstrated architecture not only increases the antenna gain, but also maintains the circular polarization. The antenna size is reduced by using a high dielectric constant ceramic substrate, where the overall antenna size is as small as 25 × 25 × 4 mm3. It is surface mountable and has circular polarization with a center frequency of 1.58 GHz, and a gain of 4.48 dB.
{"title":"A surface micromachined high directivity GPS patch antenna with a four-leaf clover shape metamaterial slab","authors":"Cheolbok Kim, Kyung-Hoon Lee, Sangrok Lee, Kyoung-Tae Kim, Y. Yoon","doi":"10.1109/ECTC.2012.6248949","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248949","url":null,"abstract":"A high gain patch antenna with a four-leaf clover shape metamaterial slab on top is implemented using the combination of multiple ceramic and organic layers for global positioning system (GPS) applications. The four-leaf clover shape metamaterial slab showing a refractive index of zero or close to zero is designed for high gain antenna applications. An effective refractive index of 0.5 is obtained for a designed architecture. As a source antenna, a circularly polarized rectangular patch antenna is implemented with two diagonal corners truncated. The demonstrated architecture not only increases the antenna gain, but also maintains the circular polarization. The antenna size is reduced by using a high dielectric constant ceramic substrate, where the overall antenna size is as small as 25 × 25 × 4 mm3. It is surface mountable and has circular polarization with a center frequency of 1.58 GHz, and a gain of 4.48 dB.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86912859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248951
Y. H. Lin, F. Kuo, Y. F. Chen, C. Ho, J. Y. Lai, S. Chen, F. Chien, R. Lee, J. Lau
Ball mount technology uses performed solder spheres dropping through a metal template onto wafer at once. This technology is directly producing bumps on wafer with high throughput and consistent bump results. Ball mounting process without using electroplating decreases cost and chemical pollution. This technique is applicable for many applications but several issues associated with this technology that limits its widespread use in high volume and high yield applications. These limitations include: (1) a practical lower limit to the size of sphere that can be dropped, and (2) the stencil between the performed solder spheres and the wafer can fail, causing a release of all the spheres into the tool (often referred to as bursts or escapes), and the yields are statistically low. To meet high I/O density IC request, the trend of wafer level chip scale package (WLCSP) I/O pad distributed design is toward to reduce the I/O pitch and increase the I/O density, and therefore impact solder ball size application of ball mount process, WLCSP micro-ball mount technology is requested. In this study, a low-cost and fine-pitch micro-ball mounting technology is developed. Emphasis is placed on determining the most important factors such as accurate dropping parameters, stencil quality and reflow conditions for microball mounting design, materials, and process. Three different ball sizes are considered: 70μm, 100μm, and 250μm. Their corresponding pitches are 130μm, 180μm, and 400μm. WLCSP micro balls with diameter = 70μm and pitch = 130μm on 300mm wafers (with ~2KK I/Os) have been successful produced. The yield is more than 99.99% without any missing micro ball and bridging.
球贴装技术使用焊料球体通过金属模板一次性滴到晶圆上。该技术直接在晶圆上产生凸点，具有高通量和一致的凸点结果。不使用电镀的滚珠安装工艺降低了成本和化学污染。该技术适用于许多应用，但与该技术相关的几个问题限制了其在大批量和高产量应用中的广泛应用。这些限制包括:(1)可以掉落的球体尺寸的实际下限，(2)所执行的焊接球体和晶圆之间的模板可能失效，导致所有球体释放到工具中(通常称为爆裂或逃逸)，并且产量在统计上很低。为了满足高I/O密度集成电路的要求，晶圆级芯片规模封装(WLCSP) I/O焊盘分布式设计的趋势是减小I/O间距和增加I/O密度，因此影响滚珠安装工艺中焊球尺寸的应用，要求采用WLCSP微滚珠安装技术。本研究开发了一种低成本、小间距的微球安装技术。重点放在确定最重要的因素，如准确的下降参数，模板质量和回流条件的微球安装设计，材料和工艺。滚珠尺寸分为70μm、100μm和250μm。分别为130μm、180μm和400μm。在300mm晶圆(I/ o ~2KK)上成功制备了直径为70μm、节距为130μm的WLCSP微球。产率大于99.99%，无微球丢失和桥接现象。
{"title":"Low-cost and fine-pitch micro-ball mounting technology for WLCSP","authors":"Y. H. Lin, F. Kuo, Y. F. Chen, C. Ho, J. Y. Lai, S. Chen, F. Chien, R. Lee, J. Lau","doi":"10.1109/ECTC.2012.6248951","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248951","url":null,"abstract":"Ball mount technology uses performed solder spheres dropping through a metal template onto wafer at once. This technology is directly producing bumps on wafer with high throughput and consistent bump results. Ball mounting process without using electroplating decreases cost and chemical pollution. This technique is applicable for many applications but several issues associated with this technology that limits its widespread use in high volume and high yield applications. These limitations include: (1) a practical lower limit to the size of sphere that can be dropped, and (2) the stencil between the performed solder spheres and the wafer can fail, causing a release of all the spheres into the tool (often referred to as bursts or escapes), and the yields are statistically low. To meet high I/O density IC request, the trend of wafer level chip scale package (WLCSP) I/O pad distributed design is toward to reduce the I/O pitch and increase the I/O density, and therefore impact solder ball size application of ball mount process, WLCSP micro-ball mount technology is requested. In this study, a low-cost and fine-pitch micro-ball mounting technology is developed. Emphasis is placed on determining the most important factors such as accurate dropping parameters, stencil quality and reflow conditions for microball mounting design, materials, and process. Three different ball sizes are considered: 70μm, 100μm, and 250μm. Their corresponding pitches are 130μm, 180μm, and 400μm. WLCSP micro balls with diameter = 70μm and pitch = 130μm on 300mm wafers (with ~2KK I/Os) have been successful produced. The yield is more than 99.99% without any missing micro ball and bridging.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86935464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248983
L. Kai, L. Hung, L. Wu, Chiang Yeh Men, D. Jiang, Chun-An Huang, Yu Po Wang
In semiconductor packaging, wire bonding is the main technology for electrical connections between chip and leadframe or substrate. Gold wire bonding has the advantages of a fast bonding process, excellent electrical property and stable chemical property. It has been widely used in various electronic packages. Gold prices have been raised significantly over the last few years. Many manufactures have been investigating ways to replace the conventional gold wire with various new materials. Copper wire bonding is an alternative interconnection technology. Cu wire has superior electrical and thermal conductivities as well as higher tensile strength, elongation and better “ball neck” strength. On the other hand, the higher hardness of Cu wire requires higher ultrasonic power and bonding force, which lead to high risk of cratering for ball bonding and tearing for wedge bonding. These will cause some package limitation and wire bonder machine downtime or low units per hour (UPH). Ag alloy wire has low Young's modulus and hardness property. It is a low cost wire bonding solution other than gold wire. In this study, Ag alloy wire is proposed as an alternative to Au bonding wire. Emphasis is placed on the wire bonding workability and reliability of using Ag-Au-Pd alloy wire for TSOP package. Also, wire bonding parameter such as electronic flame off (EFO), bond force, ultrasonic power, heat block temperature and time for ball and wedge bonding are optimized. Furthermore, the response for parameter optimization is determined by the Dage bond tester. Package reliability is determined through environmental tests that include pressure cooker test (PCT), temperature cycle test (TCT) and high temperature storage life test (HTSL). The tested samples were studied by focused ion beam (FIB), scanning electron microscopy (SEM) and energy dispersive spectrometer analyses (EDS). Intermetallic compound growth behavior during reliability test is characterized and compared to Al-Au and Al-Cu systems. Ag-Al didn't have excessive volume variation and void occurrence to get better bonding performance during various reliability tests.
{"title":"Silver alloy wire bonding","authors":"L. Kai, L. Hung, L. Wu, Chiang Yeh Men, D. Jiang, Chun-An Huang, Yu Po Wang","doi":"10.1109/ECTC.2012.6248983","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248983","url":null,"abstract":"In semiconductor packaging, wire bonding is the main technology for electrical connections between chip and leadframe or substrate. Gold wire bonding has the advantages of a fast bonding process, excellent electrical property and stable chemical property. It has been widely used in various electronic packages. Gold prices have been raised significantly over the last few years. Many manufactures have been investigating ways to replace the conventional gold wire with various new materials. Copper wire bonding is an alternative interconnection technology. Cu wire has superior electrical and thermal conductivities as well as higher tensile strength, elongation and better “ball neck” strength. On the other hand, the higher hardness of Cu wire requires higher ultrasonic power and bonding force, which lead to high risk of cratering for ball bonding and tearing for wedge bonding. These will cause some package limitation and wire bonder machine downtime or low units per hour (UPH). Ag alloy wire has low Young's modulus and hardness property. It is a low cost wire bonding solution other than gold wire. In this study, Ag alloy wire is proposed as an alternative to Au bonding wire. Emphasis is placed on the wire bonding workability and reliability of using Ag-Au-Pd alloy wire for TSOP package. Also, wire bonding parameter such as electronic flame off (EFO), bond force, ultrasonic power, heat block temperature and time for ball and wedge bonding are optimized. Furthermore, the response for parameter optimization is determined by the Dage bond tester. Package reliability is determined through environmental tests that include pressure cooker test (PCT), temperature cycle test (TCT) and high temperature storage life test (HTSL). The tested samples were studied by focused ion beam (FIB), scanning electron microscopy (SEM) and energy dispersive spectrometer analyses (EDS). Intermetallic compound growth behavior during reliability test is characterized and compared to Al-Au and Al-Cu systems. Ag-Al didn't have excessive volume variation and void occurrence to get better bonding performance during various reliability tests.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90569361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249116
Fei Chen, Kai Wang, Sheng Liu
In this paper, we analyze the optical features of different LED packaging types in forward-lighting application. There are generally two packaging types: point source and line source. For the two different packaging types, we introduce several high-efficient supporting opticses in forward-lighting application.
{"title":"High-efficient optics for different LED packaging types in forward-lighting application","authors":"Fei Chen, Kai Wang, Sheng Liu","doi":"10.1109/ECTC.2012.6249116","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249116","url":null,"abstract":"In this paper, we analyze the optical features of different LED packaging types in forward-lighting application. There are generally two packaging types: point source and line source. For the two different packaging types, we introduce several high-efficient supporting opticses in forward-lighting application.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86071560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248883
C. Zhan, P. Tzeng, J. Lau, M. Dai, H. Chien, Ching-Kuan Lee, Shang-Tsai Wu, K. Kao, Shin-Yi Huang, Chia-Wen Fan, Su-Ching Chung, Yu-wei Huang, Yu-Min Lin, Jing-Yao Chang, Tsung-Fu Yang, Tai-Hung Chen, R. Lo, M. Kao
In this study, a 3D IC integration system-in-package (SiP) with TSV/RDL/IPD interposer is designed and developed. Emphasis is placed on the Cu revealing, embedded stress sensors, non-destructive inspection, thermal modeling and measurement, and final assembly and reliability assessments.
{"title":"Assembly process and reliability assessment of TSV/RDL/IPD interposer with multi-chip-stacking for 3D IC integration SiP","authors":"C. Zhan, P. Tzeng, J. Lau, M. Dai, H. Chien, Ching-Kuan Lee, Shang-Tsai Wu, K. Kao, Shin-Yi Huang, Chia-Wen Fan, Su-Ching Chung, Yu-wei Huang, Yu-Min Lin, Jing-Yao Chang, Tsung-Fu Yang, Tai-Hung Chen, R. Lo, M. Kao","doi":"10.1109/ECTC.2012.6248883","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248883","url":null,"abstract":"In this study, a 3D IC integration system-in-package (SiP) with TSV/RDL/IPD interposer is designed and developed. Emphasis is placed on the Cu revealing, embedded stress sensors, non-destructive inspection, thermal modeling and measurement, and final assembly and reliability assessments.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88670568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249103
Yu-Jen Chang, Tai-Yu Zheng, Hao-Hsiang Chuang, Chuen-De Wang, P. Chen, T. Kuo, C. Zhan, Shih-Hsien Wu, W. Lo, Yi-Chang Lu, Y. Chiou, Tzong-Lin Wu
A solution for reducing the signal distortion in SiO2-coated through silicon vias (TSVs) is proposed. The mechanism can be explained by using a verified equivalent circuit model of a four-TSV system. Based on this circuit model, the phenomena that larger thickness of dielectric layer causes lower slow-wave factor (SWF), smaller insertion loss and smaller crosstalk level can be observed. With the aid of ajinomoto-build-up-film-coated (ABF-coated) TSVs, the solution can be implemented. The insertion loss is 3 dB better, the near-end crosstalk is 5 dB better, and the far-end crosstalk is 25dB better than conventional SiO2-coated TSVs at 2 GHz. Measurement results are also given. Good consistency can be seen, and can support the conclusion of the simulation results.
{"title":"Low slow-wave effect and crosstalk for low-cost ABF-coated TSVs in 3-D IC interposer","authors":"Yu-Jen Chang, Tai-Yu Zheng, Hao-Hsiang Chuang, Chuen-De Wang, P. Chen, T. Kuo, C. Zhan, Shih-Hsien Wu, W. Lo, Yi-Chang Lu, Y. Chiou, Tzong-Lin Wu","doi":"10.1109/ECTC.2012.6249103","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249103","url":null,"abstract":"A solution for reducing the signal distortion in SiO2-coated through silicon vias (TSVs) is proposed. The mechanism can be explained by using a verified equivalent circuit model of a four-TSV system. Based on this circuit model, the phenomena that larger thickness of dielectric layer causes lower slow-wave factor (SWF), smaller insertion loss and smaller crosstalk level can be observed. With the aid of ajinomoto-build-up-film-coated (ABF-coated) TSVs, the solution can be implemented. The insertion loss is 3 dB better, the near-end crosstalk is 5 dB better, and the far-end crosstalk is 25dB better than conventional SiO2-coated TSVs at 2 GHz. Measurement results are also given. Good consistency can be seen, and can support the conclusion of the simulation results.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88838731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248989
Xi Liu, Ming Li, D. Mullen, J. Cline, S. Sitaraman
The microelectronic packaging field is moving into the third dimension for miniaturization, low power consumption, and better performance. In this paper, we present a double-sided flip-chip organic substrate with a memory controller on one side of the package, and 3D stacked disaggregated memory chips on the other side of the package. This design allows the controller to interface with the DRAM stack directly through the substrate providing the shortest possible interconnect path, and thus achieving the fastest signaling speed. However, this double-sided flip chip on organic substrate also causes yield, assembly, test, and reliability challenges. In order to optimize the assembly process, a sequential 3D finite-element model was developed to simulate the package assembly process. In these simulations, various assembly process sequences were simulated with different conditions and materials. In addition, a probing test model was also built to study the connectivity of the Land Grid Array (LGA) pin array with the PCB sockets. Results show that the careful selection of assembly steps and package materials are crucial for the successful package assembly and also important for the probing test.
{"title":"Design and assembly of a double-sided 3D package with a controller and a DRAM stack","authors":"Xi Liu, Ming Li, D. Mullen, J. Cline, S. Sitaraman","doi":"10.1109/ECTC.2012.6248989","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248989","url":null,"abstract":"The microelectronic packaging field is moving into the third dimension for miniaturization, low power consumption, and better performance. In this paper, we present a double-sided flip-chip organic substrate with a memory controller on one side of the package, and 3D stacked disaggregated memory chips on the other side of the package. This design allows the controller to interface with the DRAM stack directly through the substrate providing the shortest possible interconnect path, and thus achieving the fastest signaling speed. However, this double-sided flip chip on organic substrate also causes yield, assembly, test, and reliability challenges. In order to optimize the assembly process, a sequential 3D finite-element model was developed to simulate the package assembly process. In these simulations, various assembly process sequences were simulated with different conditions and materials. In addition, a probing test model was also built to study the connectivity of the Land Grid Array (LGA) pin array with the PCB sockets. Results show that the careful selection of assembly steps and package materials are crucial for the successful package assembly and also important for the probing test.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89751962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249130
Xiaoyu Cheng, E. David, Y. Yoon
A compact frequency equalizer based on distributed passive circuits is designed, analyzed and implemented for the front end circuit of a portable spectrum analyzer working between 100MHz to 7 GHz. The equalizer is based on a T-shape passive attenuator consisting of multiple distributed inductive and capacitive elements. As a test vehicle, a 3-stage broadband amplifier has been implemented, connected to the designed equalizer, and characterized in the targeted frequency range. Without the equalizer, the measured gain of the implemented amplifier varies from 34.7 dB to 46.97 dB showing a 12.27 dB roll off in the frequency range. After connecting the equalizer, overall gain variation is reduced to ± 1.1dB. Compared with other preexisting frequency equalizers, the implemented one features a small footprint of 6×8 mm2 and a wide frequency bandwidth of 100MHz to 7GHz. Detail description on the equivalent circuit model and general design guidelines are given, and parametric analysis is performed. The implemented equalizer is suitable for the front end circuits of compact broadband test and measurement instruments, such as a portable spectrum analyzer and vector network analyzer.
{"title":"A compact 100 MHz to 7 GHz frequency equalizer based on distributed passive circuits","authors":"Xiaoyu Cheng, E. David, Y. Yoon","doi":"10.1109/ECTC.2012.6249130","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249130","url":null,"abstract":"A compact frequency equalizer based on distributed passive circuits is designed, analyzed and implemented for the front end circuit of a portable spectrum analyzer working between 100MHz to 7 GHz. The equalizer is based on a T-shape passive attenuator consisting of multiple distributed inductive and capacitive elements. As a test vehicle, a 3-stage broadband amplifier has been implemented, connected to the designed equalizer, and characterized in the targeted frequency range. Without the equalizer, the measured gain of the implemented amplifier varies from 34.7 dB to 46.97 dB showing a 12.27 dB roll off in the frequency range. After connecting the equalizer, overall gain variation is reduced to ± 1.1dB. Compared with other preexisting frequency equalizers, the implemented one features a small footprint of 6×8 mm2 and a wide frequency bandwidth of 100MHz to 7GHz. Detail description on the equivalent circuit model and general design guidelines are given, and parametric analysis is performed. The implemented equalizer is suitable for the front end circuits of compact broadband test and measurement instruments, such as a portable spectrum analyzer and vector network analyzer.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87292004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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