Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248801
E. Schulte, K. Cooper, M. Phillips, S. Shinde
For applications such as 3D integration, flip chip, and other die interconnection processes, a variety of metals is used to form an electrical and mechanical bond between the two components. Native oxides, however, quickly form on many of the common bond materials, hindering the integrity of the joint and adversely affecting long-term reliability. A new method has been developed to reduce these surface oxides and passivate the exposed metal surfaces against re-oxidation. Avoiding the use of acids or the possible exposure to hot electrons, ions and highly energetic atoms of conventional vacuum plasma, the developed and tested processing is carried out in atmospheric ambient to remove native oxides from solders and contact metals, enabling consistent bonding at modest temperatures and bond forces. The processing approach has been applied to a variety of metal and alloy surfaces, with bonding pursued over a range of forces and temperatures. Analysis of treated and untreated surfaces will also be presented, including SEM images and surface analysis techniques such as laser ellipsometry. Finally, physical bonding results will demonstrate the efficacy of the proposed atmospheric surface preparation approach, lowering the temperatures and bond forces required to achieve effective joining between component parts.
{"title":"Characterization of a novel fluxless surface preparation process for die interconnect bonding","authors":"E. Schulte, K. Cooper, M. Phillips, S. Shinde","doi":"10.1109/ECTC.2012.6248801","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248801","url":null,"abstract":"For applications such as 3D integration, flip chip, and other die interconnection processes, a variety of metals is used to form an electrical and mechanical bond between the two components. Native oxides, however, quickly form on many of the common bond materials, hindering the integrity of the joint and adversely affecting long-term reliability. A new method has been developed to reduce these surface oxides and passivate the exposed metal surfaces against re-oxidation. Avoiding the use of acids or the possible exposure to hot electrons, ions and highly energetic atoms of conventional vacuum plasma, the developed and tested processing is carried out in atmospheric ambient to remove native oxides from solders and contact metals, enabling consistent bonding at modest temperatures and bond forces. The processing approach has been applied to a variety of metal and alloy surfaces, with bonding pursued over a range of forces and temperatures. Analysis of treated and untreated surfaces will also be presented, including SEM images and surface analysis techniques such as laser ellipsometry. Finally, physical bonding results will demonstrate the efficacy of the proposed atmospheric surface preparation approach, lowering the temperatures and bond forces required to achieve effective joining between component parts.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79624078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248804
M. Hossain, S. Aravamudhan, M. Nowakowski, Xiaoqing Ma, S. Walwadkar, V. Kulkarni, S. Muthukumar
Miniaturization of electronic components driven by “thin and light” products in portable and consumer electronics has lead to thinner and smaller Ball Grid Array (BGA) packages. Surface Mount (SMT) processes for these smaller and thinner packages present significant challenges, and the reduced Z-height requirements were met with improved process solutions. This study is focused on two technology options: (a) Solder Grid Array (SGA) and (b) Coreless packaging. Dynamic warpage and thermo mechanical analysis have significant impact on board level reliability from these technology options. Board level reliability tests indicates the SGA cored packages show lower temperature cycle performance compared to BGA cored packages due to the reduced solder joint height under fatigue loading. Shock tests are comparable for both BGA and SGA cored packages. Coreless BGA packages show significantly better reliability performance compared to the equivalent conventional cored BGA packages.
{"title":"Board level solder joint assembly and reliability for ultra thin BGA packages","authors":"M. Hossain, S. Aravamudhan, M. Nowakowski, Xiaoqing Ma, S. Walwadkar, V. Kulkarni, S. Muthukumar","doi":"10.1109/ECTC.2012.6248804","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248804","url":null,"abstract":"Miniaturization of electronic components driven by “thin and light” products in portable and consumer electronics has lead to thinner and smaller Ball Grid Array (BGA) packages. Surface Mount (SMT) processes for these smaller and thinner packages present significant challenges, and the reduced Z-height requirements were met with improved process solutions. This study is focused on two technology options: (a) Solder Grid Array (SGA) and (b) Coreless packaging. Dynamic warpage and thermo mechanical analysis have significant impact on board level reliability from these technology options. Board level reliability tests indicates the SGA cored packages show lower temperature cycle performance compared to BGA cored packages due to the reduced solder joint height under fatigue loading. Shock tests are comparable for both BGA and SGA cored packages. Coreless BGA packages show significantly better reliability performance compared to the equivalent conventional cored BGA packages.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80787654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248850
T. Frank, S. Moreau, C. Chappaz, L. Arnaud, P. Leduc, A. Thuaire, L. Anghel
The electromigration (EM) behavior of Through Silicon Via (TSV) interconnects used for 3D integration is studied. Impact of the TSV section size on EM lifetime and consideration of increasing metal level thickness are reported. Void nucleates and grows right after TSV, in the adjacent metal level. The TSV section size at metal level interface is critical for high EM performance. Thickness increase of metal level is revealed to not directly increase EM robustness, since irregular void nucleation and growth impact expected performances.
{"title":"Electromigration behavior of 3D-IC TSV interconnects","authors":"T. Frank, S. Moreau, C. Chappaz, L. Arnaud, P. Leduc, A. Thuaire, L. Anghel","doi":"10.1109/ECTC.2012.6248850","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248850","url":null,"abstract":"The electromigration (EM) behavior of Through Silicon Via (TSV) interconnects used for 3D integration is studied. Impact of the TSV section size on EM lifetime and consideration of increasing metal level thickness are reported. Void nucleates and grows right after TSV, in the adjacent metal level. The TSV section size at metal level interface is critical for high EM performance. Thickness increase of metal level is revealed to not directly increase EM robustness, since irregular void nucleation and growth impact expected performances.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88687251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248939
Chang-Yi Lan, C. Hsiao, J. Lau, E. So, B. Ma
Due to more build-in functions and smaller form factor requirements, mobile devices are required to have better thermal dissipation performance and thinner IC package profile. In this study, a new package which combines Cu pillar bumps with IC backside exposed-die properties is introduced. Compared with solder bumps, Cu pillar bumps can effectively increase substrate circuit layout density and then reduce substrate layers or shrink package sizes to achieve cost down benefit. Also, compared with traditional over-mold FCCSP, IC backside exposed-die molded FCCSP can effectively eliminate roughly 100μm of package height to achieve thin package requirement. Moreover, exposed-die also can provide better thermal dissipation performance, i.e., Theta JC, when it is attached to an external heat spreader/sink or EMC shielding case. However, compared with solder bumps, Cu pillar bumps (with higher modulus property) will introduce higher mechanical stress to ELK layer and may cause potential ELK cracking issue. Also, compared with traditional over mold package, exposed-die will introduce serious package warpage issue and may cause potential low SMT yield problem. Therefore, the solutions to reduce the mechanical stress from Cu pillar bump to the ELK layer and improve the warpage for exposed-die have aroused lots of attention in semiconductor industry, especially on FCCSP and PoP (Package on Package) recently. In this study, lots of mechanical simulation models and DOE studies used to address how to effectively reduce ELK stress such as adding PI, changing bump shapes, change to DUAL UBM, or adding one RDL layer. Moreover, how substrate or molding compound material selected (such as CTE or Tg adjustment) can effectively reduce package warpage and then eventually improve FCCSP SMT and stacking PoP yields are addressed as well
由于更多的内置功能和更小的外形尺寸要求，移动设备需要具有更好的散热性能和更薄的IC封装轮廓。本研究提出一种结合铜柱凸点与IC背面外露模特性的封装方法。与钎料凸点相比，铜柱凸点可以有效地增加衬底电路布局密度，从而减少衬底层数或缩小封装尺寸，从而达到降低成本的效果。此外，与传统的上模FCCSP相比，IC背面外露模FCCSP可以有效地消除约100μm的封装高度，以实现薄封装要求。此外，当外露芯片连接到外部散热片/散热器或EMC屏蔽盒时，还可以提供更好的散热性能，即Theta JC。然而，与钎料凸起相比，铜柱凸起(具有更高的模量)会给ELK层带来更高的机械应力，并可能导致潜在的ELK开裂问题。此外，与传统的过模封装相比，外露的模具将引入严重的封装翘曲问题，并可能导致潜在的低SMT良率问题。因此，如何减小铜柱碰撞对ELK层的机械应力，改善外露模的翘曲，已引起半导体业界的广泛关注，尤其是FCCSP和PoP (Package on Package)。在本研究中，通过大量的力学仿真模型和DOE研究来解决如何有效地降低ELK应力，例如增加PI，改变凹凸形状，更换DUAL UBM，或增加一个RDL层。此外，如何选择基板或成型复合材料(如CTE或Tg调整)可以有效地减少封装翘曲，然后最终提高FCCSP SMT和堆叠PoP的产量
{"title":"Cu pillar exposed-die molded FCCSP for mobile devices","authors":"Chang-Yi Lan, C. Hsiao, J. Lau, E. So, B. Ma","doi":"10.1109/ECTC.2012.6248939","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248939","url":null,"abstract":"Due to more build-in functions and smaller form factor requirements, mobile devices are required to have better thermal dissipation performance and thinner IC package profile. In this study, a new package which combines Cu pillar bumps with IC backside exposed-die properties is introduced. Compared with solder bumps, Cu pillar bumps can effectively increase substrate circuit layout density and then reduce substrate layers or shrink package sizes to achieve cost down benefit. Also, compared with traditional over-mold FCCSP, IC backside exposed-die molded FCCSP can effectively eliminate roughly 100μm of package height to achieve thin package requirement. Moreover, exposed-die also can provide better thermal dissipation performance, i.e., Theta JC, when it is attached to an external heat spreader/sink or EMC shielding case. However, compared with solder bumps, Cu pillar bumps (with higher modulus property) will introduce higher mechanical stress to ELK layer and may cause potential ELK cracking issue. Also, compared with traditional over mold package, exposed-die will introduce serious package warpage issue and may cause potential low SMT yield problem. Therefore, the solutions to reduce the mechanical stress from Cu pillar bump to the ELK layer and improve the warpage for exposed-die have aroused lots of attention in semiconductor industry, especially on FCCSP and PoP (Package on Package) recently. In this study, lots of mechanical simulation models and DOE studies used to address how to effectively reduce ELK stress such as adding PI, changing bump shapes, change to DUAL UBM, or adding one RDL layer. Moreover, how substrate or molding compound material selected (such as CTE or Tg adjustment) can effectively reduce package warpage and then eventually improve FCCSP SMT and stacking PoP yields are addressed as well","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90406087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248879
M. Motalab, Z. Cai, J. Suhling, Jiawei Zhang, J. Evans, M. Bozack, P. Lall
It has been demonstrated that isothermal aging leads to large reductions (up to 50%) in several key material properties for lead free solders including stiffness (modulus), yield stress, ultimate strength, and strain to failure. In addition, even more dramatic evolution has been observed in the creep response of aged solders, where up to 10,000X increases have been observed in the steady state (secondary) creep strain rate (creep compliance). Such degradations in the stiffness, strength, and creep compliance of the solder material are expected to be universally detrimental to reliability of solder joints in electronic assemblies. Traditional finite element based predictions for solder joint reliability during thermal cycling accelerated life testing are based on solder constitutive equations (e.g. Anand viscoplastic model) and failure models (e.g. energy dissipation per cycle models) that do not evolve with material aging. Thus, there will be significant errors in the calculations with lead free SAC alloys that illustrate dramatic aging phenomena. In our current research, we are developing new reliability prediction procedures that utilize constitutive relations and failure criteria that incorporate aging effects, and then validating the new approaches through correlation with thermal cycling accelerated life testing experimental data. In this paper, we report on the first step of that development, namely the establishment of a revised set of Anand viscoplastic stress-strain relations for solder that include material parameters that evolve with the thermal history of the solder material. The effects of aging on the nine Anand model parameters have been examined by performing stress strain tests on SAC305 samples that were aged for various durations (0-6 months) at a temperature of 100 C. For each aging time, stress-strain data were measured at three strain rates (0.001, 0.0001, and 0.00001 1/sec) and five temperatures (25, 50, 75, 100, and 125 C). Using the measured stress-strain data, the Anand model material parameters have been determined for various aging conditions. Mathematical expressions were then developed to model the evolution of the Anand model parameter with aging time. Our results show that 2 of the 9 constants remain essentially constant during aging, while the other 6 show large changes (30-70%) with up to 6 months of aging at 100 C. Preliminary finite element simulations have also shown that the use of the modified Anand model leads to a strong dependence of the calculated plastic work dissipated per cycle on the aging conditions prior to thermal cycling.
{"title":"Improved predictions of lead free solder joint reliability that include aging effects","authors":"M. Motalab, Z. Cai, J. Suhling, Jiawei Zhang, J. Evans, M. Bozack, P. Lall","doi":"10.1109/ECTC.2012.6248879","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248879","url":null,"abstract":"It has been demonstrated that isothermal aging leads to large reductions (up to 50%) in several key material properties for lead free solders including stiffness (modulus), yield stress, ultimate strength, and strain to failure. In addition, even more dramatic evolution has been observed in the creep response of aged solders, where up to 10,000X increases have been observed in the steady state (secondary) creep strain rate (creep compliance). Such degradations in the stiffness, strength, and creep compliance of the solder material are expected to be universally detrimental to reliability of solder joints in electronic assemblies. Traditional finite element based predictions for solder joint reliability during thermal cycling accelerated life testing are based on solder constitutive equations (e.g. Anand viscoplastic model) and failure models (e.g. energy dissipation per cycle models) that do not evolve with material aging. Thus, there will be significant errors in the calculations with lead free SAC alloys that illustrate dramatic aging phenomena. In our current research, we are developing new reliability prediction procedures that utilize constitutive relations and failure criteria that incorporate aging effects, and then validating the new approaches through correlation with thermal cycling accelerated life testing experimental data. In this paper, we report on the first step of that development, namely the establishment of a revised set of Anand viscoplastic stress-strain relations for solder that include material parameters that evolve with the thermal history of the solder material. The effects of aging on the nine Anand model parameters have been examined by performing stress strain tests on SAC305 samples that were aged for various durations (0-6 months) at a temperature of 100 C. For each aging time, stress-strain data were measured at three strain rates (0.001, 0.0001, and 0.00001 1/sec) and five temperatures (25, 50, 75, 100, and 125 C). Using the measured stress-strain data, the Anand model material parameters have been determined for various aging conditions. Mathematical expressions were then developed to model the evolution of the Anand model parameter with aging time. Our results show that 2 of the 9 constants remain essentially constant during aging, while the other 6 show large changes (30-70%) with up to 6 months of aging at 100 C. Preliminary finite element simulations have also shown that the use of the modified Anand model leads to a strong dependence of the calculated plastic work dissipated per cycle on the aging conditions prior to thermal cycling.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89411005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249114
Weiwei Zhao, T. Santaniello, P. Webb, C. Lenardi, Changqing Liu
We present a compression based packaging technique which can be applied to reversibly seal hydrogel based materials' thin films and micro-fabricated thermoplastic components for hybrid materials stacking microfluidic cells-based chips design. A multilayer microdevice has been realized for liquid leakage tests at the thermoplastic/hydrogel interface nearby the fluidic circuits machined on the plastic layer; biocompatible Poly-hydroxyethylmethacrylate (PHEMA) hydrogel membranes with different thickness (Ranging from 100 to 200 μm) and micro-milled Polymethylmethacrylate components were chosen to realize the chip. By promoting continuous perfusion of the system pumping aqueous coloured dye solutions in the microchannels, the sealing between the two materials resulted guaranteed for tested flow rate values, ranging from 100nL/min to 10mL/min. Furthermore, to take the hydrogel into operation, a representative case study of a micro-bioreactor based on joint hybrid materials and employing PHEMA thin film as a cell culture substrate has been analyzed and modelled by mean of numerical simulation.
{"title":"A new approach towards an optimum design and manufacture of microfluidic devices based on ex situ fabricated hydrogel based thin films' integration","authors":"Weiwei Zhao, T. Santaniello, P. Webb, C. Lenardi, Changqing Liu","doi":"10.1109/ECTC.2012.6249114","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249114","url":null,"abstract":"We present a compression based packaging technique which can be applied to reversibly seal hydrogel based materials' thin films and micro-fabricated thermoplastic components for hybrid materials stacking microfluidic cells-based chips design. A multilayer microdevice has been realized for liquid leakage tests at the thermoplastic/hydrogel interface nearby the fluidic circuits machined on the plastic layer; biocompatible Poly-hydroxyethylmethacrylate (PHEMA) hydrogel membranes with different thickness (Ranging from 100 to 200 μm) and micro-milled Polymethylmethacrylate components were chosen to realize the chip. By promoting continuous perfusion of the system pumping aqueous coloured dye solutions in the microchannels, the sealing between the two materials resulted guaranteed for tested flow rate values, ranging from 100nL/min to 10mL/min. Furthermore, to take the hydrogel into operation, a representative case study of a micro-bioreactor based on joint hybrid materials and employing PHEMA thin film as a cell culture substrate has been analyzed and modelled by mean of numerical simulation.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78411444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249058
Yue Zhang, A. Dembla, Y. Joshi, Muhannad S. Bakir
Cooling is a significant challenge for high-performance high-power 3D ICs. hi this paper, we describe the experimental evaluation of 3D ICs with embedded microfluidic cooling. Different architectures are experimentally evaluated ine hiding: 1) a memory-on-processor stack. 2) a processor-on-processor stack with equal power dissipation, and 3) a processor-on-processor stack with different power dissipation, hi all cases, embedded microfluidic cooling shows significant junction temperature reduction compared to air-cooling.
{"title":"3D stacked microfluidic cooling for high-performance 3D ICs","authors":"Yue Zhang, A. Dembla, Y. Joshi, Muhannad S. Bakir","doi":"10.1109/ECTC.2012.6249058","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249058","url":null,"abstract":"Cooling is a significant challenge for high-performance high-power 3D ICs. hi this paper, we describe the experimental evaluation of 3D ICs with embedded microfluidic cooling. Different architectures are experimentally evaluated ine hiding: 1) a memory-on-processor stack. 2) a processor-on-processor stack with equal power dissipation, and 3) a processor-on-processor stack with different power dissipation, hi all cases, embedded microfluidic cooling shows significant junction temperature reduction compared to air-cooling.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77937811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248953
Hongbin Shi, Daquan Yu, T. Ueda
Lead-free (LF) solder joints of portable devices are frequently subjected to unintentional drop, bend, shear and thermal cycling loading during transportation, handling, and usage. Various underfills are widely used in the electronics industry to deal with these challenges, however, the above approaches have some intrinsic shortcomings such as high material costs, low manufacturing assembly rate, poor reworkability and so on. To reduce the cycle time and cost of conventional underfill process, two promising polymeric reinforcement technologies for the next generation array-based package (ABP) application, the so-called edge and corner bond adhesives, have been developed. In this paper, the second level interconnection (SLI) reliability of edge and corner bonded LF package stackable very thin fine pitch ball grid arrays (PSvfBGAs) was systematic studied using package to board interconnection shear, monotonic 4-point bend, 90° free-drop, and thermal cycling tests. Three materials used in this study were a UV-cured acrylic edge bond adhesive (EBA), and thermal-cured epoxy EBA, and a thermal-cured epoxy corner bond adhesive (CBA). Moreover, the PSvfBGAs without bonding were also tested for comparison. The test results indicate that all the bonding materials increase the mechanical performance of SLIs, especially for drop reliability. On the contrary, the thermal fatigue lives of PSvfBGAs with edge bond acrylic and epoxy are reduced by 38.42% and 8.34%, respectively. In addition to the comparison of maximum shear and bend forces, crosshead displacement, principle strain, drops and thermal cycles to failure between the four test groups, the failure modes and mechanisms of SLIs under various test conditions were analyzed as well.
{"title":"Systematic studies of second level interconnection reliability of edge and corner bonded lead-free array-based packages under mechanical and thermal loading","authors":"Hongbin Shi, Daquan Yu, T. Ueda","doi":"10.1109/ECTC.2012.6248953","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248953","url":null,"abstract":"Lead-free (LF) solder joints of portable devices are frequently subjected to unintentional drop, bend, shear and thermal cycling loading during transportation, handling, and usage. Various underfills are widely used in the electronics industry to deal with these challenges, however, the above approaches have some intrinsic shortcomings such as high material costs, low manufacturing assembly rate, poor reworkability and so on. To reduce the cycle time and cost of conventional underfill process, two promising polymeric reinforcement technologies for the next generation array-based package (ABP) application, the so-called edge and corner bond adhesives, have been developed. In this paper, the second level interconnection (SLI) reliability of edge and corner bonded LF package stackable very thin fine pitch ball grid arrays (PSvfBGAs) was systematic studied using package to board interconnection shear, monotonic 4-point bend, 90° free-drop, and thermal cycling tests. Three materials used in this study were a UV-cured acrylic edge bond adhesive (EBA), and thermal-cured epoxy EBA, and a thermal-cured epoxy corner bond adhesive (CBA). Moreover, the PSvfBGAs without bonding were also tested for comparison. The test results indicate that all the bonding materials increase the mechanical performance of SLIs, especially for drop reliability. On the contrary, the thermal fatigue lives of PSvfBGAs with edge bond acrylic and epoxy are reduced by 38.42% and 8.34%, respectively. In addition to the comparison of maximum shear and bend forces, crosshead displacement, principle strain, drops and thermal cycles to failure between the four test groups, the failure modes and mechanisms of SLIs under various test conditions were analyzed as well.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74227208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249102
Il Kim, Seunghwan Kim, Inseong You, Haeshin Lee, K. Paik
Immersion of substrates in a dilute aqueous solution of bio-inspired building blocks resulted a deposition of polydopamine thin film on the substrate. The Self-polymerization speed measured by ellipsometry was 1.6 nm/hr. Strong catalyst was added in order to enhance the speed. The resulting speed was increased from 1.6 nm/hr to 30 nm/hr. Bio-inspired surface treated PET and ITO-PET substrates with various treatment times were assembled with FPC using commercial acrylic ACF. As a result, adhesion strength between PET substrates and FPC was enhanced dramatically from below 10 gf/cm to over 500 gf/cm even when the treatment time was 5 min. Electrical contact resistance did not show any notable changes. It was presumably due to the sufficiently low thickness (2.5 nm) of bio-inspired thin film on the electrode.
{"title":"Bio-inspired surface treatment on touch screen panels (TSPs) for adhesion enhancement","authors":"Il Kim, Seunghwan Kim, Inseong You, Haeshin Lee, K. Paik","doi":"10.1109/ECTC.2012.6249102","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249102","url":null,"abstract":"Immersion of substrates in a dilute aqueous solution of bio-inspired building blocks resulted a deposition of polydopamine thin film on the substrate. The Self-polymerization speed measured by ellipsometry was 1.6 nm/hr. Strong catalyst was added in order to enhance the speed. The resulting speed was increased from 1.6 nm/hr to 30 nm/hr. Bio-inspired surface treated PET and ITO-PET substrates with various treatment times were assembled with FPC using commercial acrylic ACF. As a result, adhesion strength between PET substrates and FPC was enhanced dramatically from below 10 gf/cm to over 500 gf/cm even when the treatment time was 5 min. Electrical contact resistance did not show any notable changes. It was presumably due to the sufficiently low thickness (2.5 nm) of bio-inspired thin film on the electrode.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74529314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248838
I. Shubin, E. Chow, A. Chow, H. Thacker, D. Debruyker, K. Fujimoto, K. Raj, A. Krishnamoorthy, J. Mitchell, J. Cunningham
A novel packaging module is described that is based on co-integration of flexible micro-spring interconnects with through silicon copper vias (TSVs) into a passive large area silicon interposer. We report on the packaging test vehicles based on such interposers that are designed to demonstrate a wafer scale integration process to form TSV+spring interconnects with high yield and low resistance. Our goal is to develop a scalable, large area die or MCM packaging platform to enable stress-free, readily reworkable packaging of chips and components with different functionality and technology. We show interposer layouts, share process details and characterization methods.
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