Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248922
N. Kumar, S. Ramaswami, J. Dukovic, J. Tseng, R. Ding, N. Rajagopalan, B. Eaton, R. Mishra, R. Yalamanchili, Zhihong Wang, S. Xia, K. Sapre, J. Hua, A. Chan, G. Mori, B. Linke
An overview is given of developments in unit-process and process-integration technology enabling the realization of through-silicon vias (TSVs) for 3D chip stacking. TSVs are expected to increase interconnect bandwidth, reduce wire delay due to shorter vertical signal path, and improve power efficiency [1-3]. The fabrication sequences for forming TSVs in the middle of the line (via-middle approach) and for revealing them from the backside in the far back end of the line are described with detailed attention to major unit processes of etch, dielectric deposition, barrier and seed deposition, electrochemical deposition, and chemical-mechanical planarization. Unit-process advances are described in relation to the structural and functional requirements of the TSVs, and examples are given of co-optimization among the interdependent steps of the integrated sequence. Emphasis is given to copper vias of diameter 4 to 10μm with aspect ratio between 8 and 12. For both the viaformation and via-reveal sequence, it is shown how integration problems were overcome by a comprehensive approach.
{"title":"Robust TSV via-middle and via-reveal process integration accomplished through characterization and management of sources of variation","authors":"N. Kumar, S. Ramaswami, J. Dukovic, J. Tseng, R. Ding, N. Rajagopalan, B. Eaton, R. Mishra, R. Yalamanchili, Zhihong Wang, S. Xia, K. Sapre, J. Hua, A. Chan, G. Mori, B. Linke","doi":"10.1109/ECTC.2012.6248922","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248922","url":null,"abstract":"An overview is given of developments in unit-process and process-integration technology enabling the realization of through-silicon vias (TSVs) for 3D chip stacking. TSVs are expected to increase interconnect bandwidth, reduce wire delay due to shorter vertical signal path, and improve power efficiency [1-3]. The fabrication sequences for forming TSVs in the middle of the line (via-middle approach) and for revealing them from the backside in the far back end of the line are described with detailed attention to major unit processes of etch, dielectric deposition, barrier and seed deposition, electrochemical deposition, and chemical-mechanical planarization. Unit-process advances are described in relation to the structural and functional requirements of the TSVs, and examples are given of co-optimization among the interdependent steps of the integrated sequence. Emphasis is given to copper vias of diameter 4 to 10μm with aspect ratio between 8 and 12. For both the viaformation and via-reveal sequence, it is shown how integration problems were overcome by a comprehensive approach.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74875833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248878
C. Burke, J. Punch, M. Collins
This study investigates the creep behavior of joint-scale Sn1.0Ag0.5Cu (SAC105) solder samples under shear loading. The objective of the work is to determine the Anand viscoplastic constitutive model parameters for this low silver content ternary SAC solder alloy. A series of monotonic constant shear stress (5-15MPa) and constant shear strain rate (1E-6-1E-2 (1/s)) tests was conducted at temperatures of 20°C, 50°C, 75°C and 100°C in order to provide data to extract the constitutive model parameters. The predictions of the Anand model are compared graphically with the experimental data in order to illustrate goodness-of-fit. SAC105 was found to be more creep resistant at higher strain rates than at lower strain rates for all temperatures and test conditions. The derived Anand parameters are shown to capture the creep performance of the SAC105 solder under shear loading very well, with the experimental data being tightly bound to the Anand predictions. In addition to the quantification of mechanical characteristics, a preliminary Electron Backscatter Diffraction (EBSD) investigation was conducted to investigate the effect of preconditioning on the grain structure of SAC105 solder joints. Results indicate that the misorientaion of the solder grains increased during preconditioning, signaling grain coarsening due to ageing.
{"title":"Creep behavior of joint-scale Sn1.0Ag0.5Cu solder shear samples","authors":"C. Burke, J. Punch, M. Collins","doi":"10.1109/ECTC.2012.6248878","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248878","url":null,"abstract":"This study investigates the creep behavior of joint-scale Sn1.0Ag0.5Cu (SAC105) solder samples under shear loading. The objective of the work is to determine the Anand viscoplastic constitutive model parameters for this low silver content ternary SAC solder alloy. A series of monotonic constant shear stress (5-15MPa) and constant shear strain rate (1E-6-1E-2 (1/s)) tests was conducted at temperatures of 20°C, 50°C, 75°C and 100°C in order to provide data to extract the constitutive model parameters. The predictions of the Anand model are compared graphically with the experimental data in order to illustrate goodness-of-fit. SAC105 was found to be more creep resistant at higher strain rates than at lower strain rates for all temperatures and test conditions. The derived Anand parameters are shown to capture the creep performance of the SAC105 solder under shear loading very well, with the experimental data being tightly bound to the Anand predictions. In addition to the quantification of mechanical characteristics, a preliminary Electron Backscatter Diffraction (EBSD) investigation was conducted to investigate the effect of preconditioning on the grain structure of SAC105 solder joints. Results indicate that the misorientaion of the solder grains increased during preconditioning, signaling grain coarsening due to ageing.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73000317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249051
T. Chua, S. Babikian, Liang L. Wu, G. Li, M. Bachman
Modern semiconductor chips are reaching higher power densities, requiring cooling capacities in excess of 100 W/cm2. Liquid cooling is widely seen as the appropriate technology to provide cooling for these devices, however, convenient, integrated cooling techniques are not available. We report the use of a chip cooling package designed to interface directly with an embedded fluidic system that routes cooling liquid on a printed circuit board. The package is designed as a “package-on-package” construction so that it can be packaged over an existing electronic chip to provide fluid-based cooling to a variety of components. This paper presents package design and construction, fluidic integration, and flow/thermal performance of this package.
{"title":"Package-on-package for chip cooling with embedded fluidics","authors":"T. Chua, S. Babikian, Liang L. Wu, G. Li, M. Bachman","doi":"10.1109/ECTC.2012.6249051","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249051","url":null,"abstract":"Modern semiconductor chips are reaching higher power densities, requiring cooling capacities in excess of 100 W/cm2. Liquid cooling is widely seen as the appropriate technology to provide cooling for these devices, however, convenient, integrated cooling techniques are not available. We report the use of a chip cooling package designed to interface directly with an embedded fluidic system that routes cooling liquid on a printed circuit board. The package is designed as a “package-on-package” construction so that it can be packaged over an existing electronic chip to provide fluid-based cooling to a variety of components. This paper presents package design and construction, fluidic integration, and flow/thermal performance of this package.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75678573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249099
M. Taklo, A. Larsson, A. B. Vardoy, H. Kristiansen, L. Hoff, K. Waaler
The transition to lead free solders has accentuated the inherent reliability problem in electronic packaging caused by thermo mechanical mismatch between different parts of an assembled system. To mitigate this problem, polymer core solder balls (PCSBs) have been proposed as a mechanically more flexible and therefore more reliable alternative to solid solder balls normally used for such applications. In this paper we report results from testing of PCSBs used for connecting and attaching a low temperature co-fired ceramic (LTCC) Ball Grid Array (BGA) carrier to an FR-4 board. The results appear to be strongly dependent on the assembly process. However, the results also indicate that with a properly executed assembly process, these balls represent an alternative to traditional solder balls with remarkable resistance to thermal cycling.
{"title":"Compliant interconnects for reduced cost of a ceramic ball grid array carrier","authors":"M. Taklo, A. Larsson, A. B. Vardoy, H. Kristiansen, L. Hoff, K. Waaler","doi":"10.1109/ECTC.2012.6249099","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249099","url":null,"abstract":"The transition to lead free solders has accentuated the inherent reliability problem in electronic packaging caused by thermo mechanical mismatch between different parts of an assembled system. To mitigate this problem, polymer core solder balls (PCSBs) have been proposed as a mechanically more flexible and therefore more reliable alternative to solid solder balls normally used for such applications. In this paper we report results from testing of PCSBs used for connecting and attaching a low temperature co-fired ceramic (LTCC) Ball Grid Array (BGA) carrier to an FR-4 board. The results appear to be strongly dependent on the assembly process. However, the results also indicate that with a properly executed assembly process, these balls represent an alternative to traditional solder balls with remarkable resistance to thermal cycling.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80052080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248978
S. Hsu, Chu-Hsuan Sha, C. C. Lee
The high thermal conductivity and light weight properties of aluminum (Al) make it a promising material in high power device packaging and automotive design applications. A primary challenge is its high coefficient of thermal expansion (CTE) of 23 ppm/°C. In this research, we investigated the possibility of surmounting this challenge by bonding large Si chips to Al substrates using fluxless tin (Sn). Si versus Al pair probably has the largest CTE mismatch among all bonded structures in electronic packaging. In experiments, 0.1μm Cr layer and 0.2 μm Cu layer were deposited on Al substrates, followed by an electroplated thicker 25 μm copper (Cu) layer. The Sn solder layer was then electroplated over the Cu followed immediately by thin (0.1 μm) silver (Ag) layer. The bonding process is entirely fluxless. The joint thickness was controlled either by bonding pressure or by Cu spacers. Microstructure and composition of the joints were studied under scanning electron microscopy (SEM) and energy dispersive X-ray spectroscopy (EDX). Despite the large CTE mismatch, the bonded structures did not break. This preliminary result suggests potential adaption of Al substrates in electronic packaging where Al is avoided because of its high CTE.
{"title":"Fluxless tin bonding of silicon chips to aluminum substrates","authors":"S. Hsu, Chu-Hsuan Sha, C. C. Lee","doi":"10.1109/ECTC.2012.6248978","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248978","url":null,"abstract":"The high thermal conductivity and light weight properties of aluminum (Al) make it a promising material in high power device packaging and automotive design applications. A primary challenge is its high coefficient of thermal expansion (CTE) of 23 ppm/°C. In this research, we investigated the possibility of surmounting this challenge by bonding large Si chips to Al substrates using fluxless tin (Sn). Si versus Al pair probably has the largest CTE mismatch among all bonded structures in electronic packaging. In experiments, 0.1μm Cr layer and 0.2 μm Cu layer were deposited on Al substrates, followed by an electroplated thicker 25 μm copper (Cu) layer. The Sn solder layer was then electroplated over the Cu followed immediately by thin (0.1 μm) silver (Ag) layer. The bonding process is entirely fluxless. The joint thickness was controlled either by bonding pressure or by Cu spacers. Microstructure and composition of the joints were studied under scanning electron microscopy (SEM) and energy dispersive X-ray spectroscopy (EDX). Despite the large CTE mismatch, the bonded structures did not break. This preliminary result suggests potential adaption of Al substrates in electronic packaging where Al is avoided because of its high CTE.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80073246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249077
Seunghwan Kim, Youngjae Kim, H. Park, K. Paik
In this study, bonding time for touch screen panel (TSP) assemblies were reduced by two third using an ultrasonic (U/S) horn which fits the shape of the entire TSP bonding area. Most TSPs have at least two bonding areas on the substrates with different heights due to structural design of touch sensing. Using conventional thermo-compression anisotropic conductive film (ACF) bonding, each bonding area should be separately bonded to perform suitable interconnections with uniform pressure and a temperature due to the step height among the bonding areas. However, in U/S bonding, the bonding area could be bonded all at the same time using the U/S horn which fits the bonding area. The test vehicles were capacitive TSPs which consist of three layers of polyethylene terephthalate (PET) substrates. The TSP had three separated bonding areas. Two of them were on the double layer PET substrate. The other one located in the middle of the whole bonding area was on the single layer PET substrate. Therefore, the middle bonding area was 210 μm lower than the other two bonding areas. This complicated TSP structure requires three separate ACF bonding using conventional ACF bonding method. When using a fitted U/S horn, the in-situ ACF temperatures for all bonding areas showed negligible deviation less than 5°C. After U/S bonding for 15 seconds at 2 MPa bonding pressure and 150°C ACF temperature, the adhesion strength of the ACF joint was higher than 650 gf/cm. No damage was observed on the electrode and the substrate. Also, the ACF joints had stable electrical continuities. In conclusion, U/S ACF bonding with fitted horn was successfully demonstrated for high productivity TSP assemblies.
{"title":"High productivity and damage-free ultrasonic anisotropic conductive film (ACF) bonding for touch screen panel (TSP) assemblies","authors":"Seunghwan Kim, Youngjae Kim, H. Park, K. Paik","doi":"10.1109/ECTC.2012.6249077","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249077","url":null,"abstract":"In this study, bonding time for touch screen panel (TSP) assemblies were reduced by two third using an ultrasonic (U/S) horn which fits the shape of the entire TSP bonding area. Most TSPs have at least two bonding areas on the substrates with different heights due to structural design of touch sensing. Using conventional thermo-compression anisotropic conductive film (ACF) bonding, each bonding area should be separately bonded to perform suitable interconnections with uniform pressure and a temperature due to the step height among the bonding areas. However, in U/S bonding, the bonding area could be bonded all at the same time using the U/S horn which fits the bonding area. The test vehicles were capacitive TSPs which consist of three layers of polyethylene terephthalate (PET) substrates. The TSP had three separated bonding areas. Two of them were on the double layer PET substrate. The other one located in the middle of the whole bonding area was on the single layer PET substrate. Therefore, the middle bonding area was 210 μm lower than the other two bonding areas. This complicated TSP structure requires three separate ACF bonding using conventional ACF bonding method. When using a fitted U/S horn, the in-situ ACF temperatures for all bonding areas showed negligible deviation less than 5°C. After U/S bonding for 15 seconds at 2 MPa bonding pressure and 150°C ACF temperature, the adhesion strength of the ACF joint was higher than 650 gf/cm. No damage was observed on the electrode and the substrate. Also, the ACF joints had stable electrical continuities. In conclusion, U/S ACF bonding with fitted horn was successfully demonstrated for high productivity TSP assemblies.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79001168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248851
I. De Wolf, V. Simons, V. Cherman, R. Labie, B. Vandevelde, E. Beyne
This paper discusses mechanical stress measured with micro-Raman spectroscopy in the silicon substrate near Cu-Through Silicon Vias (TSV). A discussion of the relation between the observed Raman shift and the various stress tensor components is given, showing that this relation is often wrongly applied, and that in many cases the compressive stress along the vertical axis of the TSV, dominates the Raman results and hides the tensile axial component which is of most relevance for its impact on CMOS devices. The effect of measurement depth, TSV depth and density, and an oxide cap is shown. Both surface and cross-sectional results are discussed. Also a direct correlation between results from Raman measurements and electrical results from FET-arrays near a TSV is given.
{"title":"In-depth Raman spectroscopy analysis of various parameters affecting the mechanical stress near the surface and bulk of Cu-TSVs","authors":"I. De Wolf, V. Simons, V. Cherman, R. Labie, B. Vandevelde, E. Beyne","doi":"10.1109/ECTC.2012.6248851","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248851","url":null,"abstract":"This paper discusses mechanical stress measured with micro-Raman spectroscopy in the silicon substrate near Cu-Through Silicon Vias (TSV). A discussion of the relation between the observed Raman shift and the various stress tensor components is given, showing that this relation is often wrongly applied, and that in many cases the compressive stress along the vertical axis of the TSV, dominates the Raman results and hides the tensile axial component which is of most relevance for its impact on CMOS devices. The effect of measurement depth, TSV depth and density, and an oxide cap is shown. Both surface and cross-sectional results are discussed. Also a direct correlation between results from Raman measurements and electrical results from FET-arrays near a TSV is given.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79152313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249005
P. Lall, S. Shantaram, J. Suhling, David Locker
Electronics may experience high strain rates when subjected to high g-loads of shock and vibration. Material and damage behavior of electronic materials at high strain rates typical of shock and vibration is scarce. Previously studies have shown that second-level interconnects have a high propensity for failure under shock and vibration loads in fine pitch electronics. Exposure to shock and vibration is common in a variety of consumer environments such as automotive and portable electronics. The low strain-rate properties of commonly used SnAgCu solders, including Sn1Ag0.5Cu and Sn3Ag0.5Cu, have been found to evolve with time after prolonged exposure to high temperatures. High strain rate properties of leadfree solder alloys in the strain-rate range of 1-100 sec-1 are scarce. Previous attempts at characterizing the high strain rates properties have focused on the use of the Split Hopkinson Pressure Bar (SHPB), which enables measurements of strain rates in the neighborhood of 1000 per sec. In this paper, a new test-technique developed by the authors has been presented for measurement of material constitutive behavior. The instrument enables attaining strain rates in the neighborhood of 1 to 100 per sec. Tests are conducted at strain rates 10, 35 and 50 per sec. High speed cameras operating at 75,000 fps have been used in conjunction with digital image correlation for the measurement of full-field strain during the test. Constancy of cross-head velocity has been demonstrated during the test from the unloaded state to the specimen failure. Solder alloy constitutive behavior has been measured for SAC105, SAC305 solders. Non-linear Ramberg-Osgood model has been used to fit the material data. The Ramberg-Osgood model available in Abaqus has been used for tensile test simulation and to correlate with DIC based experimental strain data.
{"title":"Effect of high strain-rate on mechanical properties of SAC105 and SAC305 leadfree alloys","authors":"P. Lall, S. Shantaram, J. Suhling, David Locker","doi":"10.1109/ECTC.2012.6249005","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249005","url":null,"abstract":"Electronics may experience high strain rates when subjected to high g-loads of shock and vibration. Material and damage behavior of electronic materials at high strain rates typical of shock and vibration is scarce. Previously studies have shown that second-level interconnects have a high propensity for failure under shock and vibration loads in fine pitch electronics. Exposure to shock and vibration is common in a variety of consumer environments such as automotive and portable electronics. The low strain-rate properties of commonly used SnAgCu solders, including Sn1Ag0.5Cu and Sn3Ag0.5Cu, have been found to evolve with time after prolonged exposure to high temperatures. High strain rate properties of leadfree solder alloys in the strain-rate range of 1-100 sec-1 are scarce. Previous attempts at characterizing the high strain rates properties have focused on the use of the Split Hopkinson Pressure Bar (SHPB), which enables measurements of strain rates in the neighborhood of 1000 per sec. In this paper, a new test-technique developed by the authors has been presented for measurement of material constitutive behavior. The instrument enables attaining strain rates in the neighborhood of 1 to 100 per sec. Tests are conducted at strain rates 10, 35 and 50 per sec. High speed cameras operating at 75,000 fps have been used in conjunction with digital image correlation for the measurement of full-field strain during the test. Constancy of cross-head velocity has been demonstrated during the test from the unloaded state to the specimen failure. Solder alloy constitutive behavior has been measured for SAC105, SAC305 solders. Non-linear Ramberg-Osgood model has been used to fit the material data. The Ramberg-Osgood model available in Abaqus has been used for tensile test simulation and to correlate with DIC based experimental strain data.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79334910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249038
Y. Ito, S. Terada, M. Singh, S. Arai, K. Choki
We developed a novel flexible optoelectronic (O/E) transceiver module designed for high-bandwidth and low loss data transmission for board level interconnects. In the O/E module, integrated circuits (ICs) and two 12 channel O/E devices including 850 nm vertical-cavity surface-emitting laser diodes (VCSELs) and photodiodes (PDs) were flip-chip assembled on flexible printed circuit (FPC). O/E modules and a sheet of 24-channel polynorbornene (PNB) waveguides were fabricated separately by using cost-effective and standard packaging processes. At the end of the O/E module fabrication process, the PNB waveguide sheet was integrated on completed FPCs with ICs and O/E devices using bonding sheets. Micro-mirrors formed in PNB waveguides were passively aligned toward the corresponding active areas of O/E devices respectively. The PNB waveguide sheet (120 mm long) was bi-directionally linked between O/E modules. We successfully demonstrated data transmission up to 16 Gbps/channel using an optical linked O/E transceiver module with low-loss and low-crosstalk PNB waveguides.
{"title":"Demonstration of high-bandwidth data transmission above 240 Gbps for optoelectronic module with low-loss and low-crosstalk polynorbornene waveguides","authors":"Y. Ito, S. Terada, M. Singh, S. Arai, K. Choki","doi":"10.1109/ECTC.2012.6249038","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249038","url":null,"abstract":"We developed a novel flexible optoelectronic (O/E) transceiver module designed for high-bandwidth and low loss data transmission for board level interconnects. In the O/E module, integrated circuits (ICs) and two 12 channel O/E devices including 850 nm vertical-cavity surface-emitting laser diodes (VCSELs) and photodiodes (PDs) were flip-chip assembled on flexible printed circuit (FPC). O/E modules and a sheet of 24-channel polynorbornene (PNB) waveguides were fabricated separately by using cost-effective and standard packaging processes. At the end of the O/E module fabrication process, the PNB waveguide sheet was integrated on completed FPCs with ICs and O/E devices using bonding sheets. Micro-mirrors formed in PNB waveguides were passively aligned toward the corresponding active areas of O/E devices respectively. The PNB waveguide sheet (120 mm long) was bi-directionally linked between O/E modules. We successfully demonstrated data transmission up to 16 Gbps/channel using an optical linked O/E transceiver module with low-loss and low-crosstalk PNB waveguides.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81567732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249119
H. Yang, H. Thacker, I. Shubin, J. Cunningham, J. Mitchell
A MCM enabled by Proximity Communication (P×C) includes a two-dimensional array of facing chips, including island chips and bridge chips that communicate with each other using P×C I/Os placed in the overlapping regions. In order to maintain the relative vertical spacing of these P×C I/O pads as well as to allow Ball-in-Pit self-alignment technology to work, elastomeric bump interposers are placed in cavities in a substrate, which house the bridge chips, to provide a compressive force on the back surfaces of the bridge chips. These interposers contain compressible structures which are precisely placed to make sure that sufficient and symmetric amount of force is applied to the bridge chip to ensure that facing surfaces of the island chips and the bridge chips, as well as connectors on these surfaces, are held securely and reliably and are approximately coplanar without bending the bridge chips. At the same time, the interposer must also allow the bridge chip to be lowered sufficiently to disengage the ball-pit sites during the reflow process of the island chips. In this paper, the design and fabrication of such compliant mechanical interposers are discussed.
{"title":"Assembly and alignment of Proximity Communication enabled multi-chip packages using elastomeric bump interposers","authors":"H. Yang, H. Thacker, I. Shubin, J. Cunningham, J. Mitchell","doi":"10.1109/ECTC.2012.6249119","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249119","url":null,"abstract":"A MCM enabled by Proximity Communication (P×C) includes a two-dimensional array of facing chips, including island chips and bridge chips that communicate with each other using P×C I/Os placed in the overlapping regions. In order to maintain the relative vertical spacing of these P×C I/O pads as well as to allow Ball-in-Pit self-alignment technology to work, elastomeric bump interposers are placed in cavities in a substrate, which house the bridge chips, to provide a compressive force on the back surfaces of the bridge chips. These interposers contain compressible structures which are precisely placed to make sure that sufficient and symmetric amount of force is applied to the bridge chip to ensure that facing surfaces of the island chips and the bridge chips, as well as connectors on these surfaces, are held securely and reliably and are approximately coplanar without bending the bridge chips. At the same time, the interposer must also allow the bridge chip to be lowered sufficiently to disengage the ball-pit sites during the reflow process of the island chips. In this paper, the design and fabrication of such compliant mechanical interposers are discussed.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85990788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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