Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248966
K. Zoschke, T. Fischer, M. Topper, T. Fritzsch, O. Ehrmann, T. Itabashi, M. Zussman, M. Souter, H. Oppermann, K. Lang
Temporary wafer bonding for thin wafer processing is one of the key technologies of 3D system integration. In this context we introduce the polyimide material HD3007 which is suitable for temporary bonding of silicon wafers to carrier wafers by using a thermo compression process. Coating and bonding processes for 200 mm and 150 mm wafers with and without topography as well as two de-bonding concepts which are based on laser assisted and solvent assisted release processes are presented. Based on tests with temporary bonded 200 mm wafers, we found a very high compatibility of the bonded compound wafers with standard WLP process equipment and work flows suitable for backside processing of “via first” TSV wafers. Processes like silicon back grinding to a remaining thickness of 60 μm, dry etching, wet etching, CMP, PVD, spin coating of resists and polymers, lithography, electro plating and polymer curing were evaluated and are described in detail. Even at high temperatures up to 300°C and vacuum levels up to 10-4 mbar, the temporary bond layer was stable and no delamination occurred. 60 μm thin wafers could be processed and de-bonded without any problems using both release methods. De-bonding times of less than a couple minutes can be realized with laser assisted de-bonding and several minutes with a solvent based release. Compared to glues of other temporary handling systems, the proposed material offers the highest temperature budget for thin wafer backside processing as well as fast and easy de-bonding at room temperature.
{"title":"Polyimide based temporary wafer bonding technology for high temperature compliant TSV backside processing and thin device handling","authors":"K. Zoschke, T. Fischer, M. Topper, T. Fritzsch, O. Ehrmann, T. Itabashi, M. Zussman, M. Souter, H. Oppermann, K. Lang","doi":"10.1109/ECTC.2012.6248966","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248966","url":null,"abstract":"Temporary wafer bonding for thin wafer processing is one of the key technologies of 3D system integration. In this context we introduce the polyimide material HD3007 which is suitable for temporary bonding of silicon wafers to carrier wafers by using a thermo compression process. Coating and bonding processes for 200 mm and 150 mm wafers with and without topography as well as two de-bonding concepts which are based on laser assisted and solvent assisted release processes are presented. Based on tests with temporary bonded 200 mm wafers, we found a very high compatibility of the bonded compound wafers with standard WLP process equipment and work flows suitable for backside processing of “via first” TSV wafers. Processes like silicon back grinding to a remaining thickness of 60 μm, dry etching, wet etching, CMP, PVD, spin coating of resists and polymers, lithography, electro plating and polymer curing were evaluated and are described in detail. Even at high temperatures up to 300°C and vacuum levels up to 10-4 mbar, the temporary bond layer was stable and no delamination occurred. 60 μm thin wafers could be processed and de-bonded without any problems using both release methods. De-bonding times of less than a couple minutes can be realized with laser assisted de-bonding and several minutes with a solvent based release. Compared to glues of other temporary handling systems, the proposed material offers the highest temperature budget for thin wafer backside processing as well as fast and easy de-bonding at room temperature.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"25 1","pages":"1054-1061"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82307850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248914
A. Novikov, M. Nowottnick
A new concept based on the usage of ultra thin films as solder material will be presented here. For this purpose nanoscaled solder films of pure tin with the maximal thickness 100 nm were synthesized through physical vapor deposition method and then characterized with high resolution methods of scanning electron microscopy and atomic force microscopy. For the protection from oxidation during phase change analysis and also during storage and soldering process silicon nitride and carbon were sputtered in the same process chamber. The function of these coatings was tested through x-ray diffraction. The crystalline film under protective layer after cooling down is a sign for impermeability of oxygen. The thermodynamic properties like melting point and undercooling were researched with the sophisticated method of chip calorimetry that allows the measurements at very fast heating and cooling rates and therefore very small amounts of material can be studied. In the first soldering experiments passivation coatings were also tested on their convenience to produce a stable solder joint. Very promising solution for the production of stable solder joints was seen on the system consisting of alternating nanoscaled metal layers, which react during soldering process by building of an alloy. One of the components of such reactive solder systems has to serve for passivation at the same time. Carrier foil with the sputtered solder structures on its both sides can noticeably improve the stability of solder joint. After assembling at low temperature the solder structures transform into diffusion zone and the main physical properties like electrical and thermal conductivity and mechanical strength of the final solder joint are determined by the properties of the carrier foil. In this work such system consisting of silver carrier foil with nanoscaled solder layers of tin and gold was successfully tested.
{"title":"Synthesis and characterization of nanoscaled solder material","authors":"A. Novikov, M. Nowottnick","doi":"10.1109/ECTC.2012.6248914","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248914","url":null,"abstract":"A new concept based on the usage of ultra thin films as solder material will be presented here. For this purpose nanoscaled solder films of pure tin with the maximal thickness 100 nm were synthesized through physical vapor deposition method and then characterized with high resolution methods of scanning electron microscopy and atomic force microscopy. For the protection from oxidation during phase change analysis and also during storage and soldering process silicon nitride and carbon were sputtered in the same process chamber. The function of these coatings was tested through x-ray diffraction. The crystalline film under protective layer after cooling down is a sign for impermeability of oxygen. The thermodynamic properties like melting point and undercooling were researched with the sophisticated method of chip calorimetry that allows the measurements at very fast heating and cooling rates and therefore very small amounts of material can be studied. In the first soldering experiments passivation coatings were also tested on their convenience to produce a stable solder joint. Very promising solution for the production of stable solder joints was seen on the system consisting of alternating nanoscaled metal layers, which react during soldering process by building of an alloy. One of the components of such reactive solder systems has to serve for passivation at the same time. Carrier foil with the sputtered solder structures on its both sides can noticeably improve the stability of solder joint. After assembling at low temperature the solder structures transform into diffusion zone and the main physical properties like electrical and thermal conductivity and mechanical strength of the final solder joint are determined by the properties of the carrier foil. In this work such system consisting of silver carrier foil with nanoscaled solder layers of tin and gold was successfully tested.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"142 1","pages":"736-740"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80613592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249012
P. Damberg, I. Mohammed, R. Co
Today, memory plus logic stacking is being provided to smartphones and tablet computers by means of Package-on-Package (PoP). However, current PoP top-to-bottom interconnect technologies do not efficiently scale to provide the memory bandwidth required for new generations of multi-core applications processors. The current interconnect technologies such as stacking with smaller sized solder balls, using solder filled laser drilled vias in the mold cap or using PCB interposers are not cost effectively achieving required aspect ratios for fine pitch while overcoming package warp during soldering. To address the gap in PoP interconnect density, a wire bond based package stacking interconnect technology is studied that enables reduced pitch and a higher number of interconnects in the PoP perimeter stacking arrangement. The main technological challenges are identified and the research results explained. It is shown that the there are multiple methods for forming the wire-bonds, exposing the wires above the molded package body and connecting the top package to these wires. These results show that wire-bond interconnect technology is promising for the very high density and fine pitch required for wide IO implementations.
{"title":"Fine pitch copper PoP for mobile applications","authors":"P. Damberg, I. Mohammed, R. Co","doi":"10.1109/ECTC.2012.6249012","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249012","url":null,"abstract":"Today, memory plus logic stacking is being provided to smartphones and tablet computers by means of Package-on-Package (PoP). However, current PoP top-to-bottom interconnect technologies do not efficiently scale to provide the memory bandwidth required for new generations of multi-core applications processors. The current interconnect technologies such as stacking with smaller sized solder balls, using solder filled laser drilled vias in the mold cap or using PCB interposers are not cost effectively achieving required aspect ratios for fine pitch while overcoming package warp during soldering. To address the gap in PoP interconnect density, a wire bond based package stacking interconnect technology is studied that enables reduced pitch and a higher number of interconnects in the PoP perimeter stacking arrangement. The main technological challenges are identified and the research results explained. It is shown that the there are multiple methods for forming the wire-bonds, exposing the wires above the molded package body and connecting the top package to these wires. These results show that wire-bond interconnect technology is promising for the very high density and fine pitch required for wide IO implementations.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"182 1","pages":"1361-1367"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80355643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248868
Yanggyoo Jung, Minjae Lee, Sunwoo Park, Do-Hyun Ryu, Youshin Jung, Chanha Hwang, Choonheung Lee, Sungsoon Park, M. Jimarez, Myung-June Lee
Recently, technologies related to Fine Pitch Flip Chip or FPFC have been great achievements for various next generation devices, allowing a significant increase in the number of signal I/O and achieving low form factor packages. Consequently, fine pitch Cu pillar flip chip Chip Scale Package (CSP) with small sized die, with package dimension of less than 16×16mm, is already under high volume production using the Thermal-Compression Bonding with Non-conductive Paste (TCNCP) technology [1-2]. In the case of Flip Chip Ball Grid Array (FCBGA), there is a growing need for FPFC technology with Cu pillar in supporting next generation silicon node. However, there will be a high possibility of yield drop issue in conventional mass-reflow process and potential reliability due to the highly concerned tensile stress between low k die and substrate by CTE mismatch especially at the edge of the die. This can be a critical quality issue for fine pitch devices compared to normal pitch (i.e., 150um) flip chip BGA. Therefore, TCNCP bonding as an alternative should be studied on fine pitch Cu pillar flip chip BGA. This paper will discuss fine pitch flip chip assembly technology for large sized flip chip BGA. Two kinds of assembly method, mass reflow bonding versus thermal compression bonding, for the flip chip bonding will be compared for the large FPFCBGA package. Meanwhile, the advantage of TC bonding with pre-applied underfill process will be described. For robust interconnection between die and substrate for large FPFCBGA, the result of the bonding test will be described with several surface finishes such as ENEPIG, Direct Immersion Gold (DIG), Immersion Tin (IT), and Solder Coating on substrate. Interestingly, one of selected surface finishes has shown excellent reliability test results. Finally, this paper will discuss an effective approach for fine pitch devices from an assembly perspective.
{"title":"Development of large die fine pitch flip chip BGA using TCNCP technology","authors":"Yanggyoo Jung, Minjae Lee, Sunwoo Park, Do-Hyun Ryu, Youshin Jung, Chanha Hwang, Choonheung Lee, Sungsoon Park, M. Jimarez, Myung-June Lee","doi":"10.1109/ECTC.2012.6248868","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248868","url":null,"abstract":"Recently, technologies related to Fine Pitch Flip Chip or FPFC have been great achievements for various next generation devices, allowing a significant increase in the number of signal I/O and achieving low form factor packages. Consequently, fine pitch Cu pillar flip chip Chip Scale Package (CSP) with small sized die, with package dimension of less than 16×16mm, is already under high volume production using the Thermal-Compression Bonding with Non-conductive Paste (TCNCP) technology [1-2]. In the case of Flip Chip Ball Grid Array (FCBGA), there is a growing need for FPFC technology with Cu pillar in supporting next generation silicon node. However, there will be a high possibility of yield drop issue in conventional mass-reflow process and potential reliability due to the highly concerned tensile stress between low k die and substrate by CTE mismatch especially at the edge of the die. This can be a critical quality issue for fine pitch devices compared to normal pitch (i.e., 150um) flip chip BGA. Therefore, TCNCP bonding as an alternative should be studied on fine pitch Cu pillar flip chip BGA. This paper will discuss fine pitch flip chip assembly technology for large sized flip chip BGA. Two kinds of assembly method, mass reflow bonding versus thermal compression bonding, for the flip chip bonding will be compared for the large FPFCBGA package. Meanwhile, the advantage of TC bonding with pre-applied underfill process will be described. For robust interconnection between die and substrate for large FPFCBGA, the result of the bonding test will be described with several surface finishes such as ENEPIG, Direct Immersion Gold (DIG), Immersion Tin (IT), and Solder Coating on substrate. Interestingly, one of selected surface finishes has shown excellent reliability test results. Finally, this paper will discuss an effective approach for fine pitch devices from an assembly perspective.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"83 1","pages":"439-443"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80424970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248819
R. Murugan, S. Mukherjee, M. Mi, L. Pauc, C. Girardi, D. Gope, D. de Araujo, S. Chakraborty, V. Jandhyala
As System-on-Chip (SoC) designs migrate to 28nm process node and beyond, the electromagnetic (EM) co-interactions of the Chip-Package-Printed Circuit Board (PCB) becomes critical and require accurate and efficient characterization and verification. In this paper a fast, scalable, and parallelized boundary element based integral EM solutions to Maxwell equations is presented. The accuracy of the full-wave formulation, for complete EM characterization, has been validated on both canonical structures and real-world 3-D system (viz. Chip + Package + PCB). Good correlation between numerical simulation and measurement has been achieved. A few examples of the applicability of the formulation to high speed digital and analog serial interfaces on a 45nm SoC are also presented.
{"title":"System-level SoC near-field (NF) emissions: Simulation to measurement correlation","authors":"R. Murugan, S. Mukherjee, M. Mi, L. Pauc, C. Girardi, D. Gope, D. de Araujo, S. Chakraborty, V. Jandhyala","doi":"10.1109/ECTC.2012.6248819","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248819","url":null,"abstract":"As System-on-Chip (SoC) designs migrate to 28nm process node and beyond, the electromagnetic (EM) co-interactions of the Chip-Package-Printed Circuit Board (PCB) becomes critical and require accurate and efficient characterization and verification. In this paper a fast, scalable, and parallelized boundary element based integral EM solutions to Maxwell equations is presented. The accuracy of the full-wave formulation, for complete EM characterization, has been validated on both canonical structures and real-world 3-D system (viz. Chip + Package + PCB). Good correlation between numerical simulation and measurement has been achieved. A few examples of the applicability of the formulation to high speed digital and analog serial interfaces on a 45nm SoC are also presented.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"6 1","pages":"140-146"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83153327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248861
S. Kawamoto, M. Yoshida, S. Teraki, H. Iida
Recently, design of Flip Chip (FC) Package is changing with the higher density of the Package. Conventional process with Capillary Underfill (CUF) is not applicable to PKGs such as 3D and chip stacked types. To solve these problems, other processes are being developed in which an encapsulant is applied on a substrate before bonding IC. One of those is the process with Non Conductive Film (NCF). In this process, after NCF is applied, IC is bonded. Interconnection and NCF cure are done at the same time. Therefore, the design of NCF has great influences to FC assembly in terms of void, interconnectability and reliability. Thus, in this paper, we are mainly discussing the optimization of NCF design. At first, we looked at the aspect of voids. One of the causes of voids is captured air which generates when an IC connects to NCF. This relates to the flow of resin. Regarding this flow, we looked into what encapsulant's behavior is effective in controlling voids by measuring temperature and viscosity with a rheometer. As a result, we could decrease the voids by optimizing the minimum melting viscosity. As another type, the void from volatilization gas may occur from an organic substrate. We looked at the quantity of substrate using TG-DTA, and found that it decreased by 0.4% till the temperature reached 260°C. Then we found that the higher minimum melting viscosity is, the more effectively this type of voids can be controlled. Moreover we tried to optimize minimum melting viscosity, curability and flux-ability for good interconnection. Regarding the minimum melting viscosity, when it is too high, the connection will be poor. Regarding curability, when cure speed is too high, solder melting will be blocked. We also attempted to optimize flux activity, and found that gelling time, minimum melting viscosity and oxidation-reduction power need to be controlled. Based on these approaches, it became possible to design the NCF which is voidless, has good connection, and can pass the reliability test (JEDECL3, TC1000cyc).
{"title":"Effect of NCF design for the assembly of Flip Chip and reliability","authors":"S. Kawamoto, M. Yoshida, S. Teraki, H. Iida","doi":"10.1109/ECTC.2012.6248861","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248861","url":null,"abstract":"Recently, design of Flip Chip (FC) Package is changing with the higher density of the Package. Conventional process with Capillary Underfill (CUF) is not applicable to PKGs such as 3D and chip stacked types. To solve these problems, other processes are being developed in which an encapsulant is applied on a substrate before bonding IC. One of those is the process with Non Conductive Film (NCF). In this process, after NCF is applied, IC is bonded. Interconnection and NCF cure are done at the same time. Therefore, the design of NCF has great influences to FC assembly in terms of void, interconnectability and reliability. Thus, in this paper, we are mainly discussing the optimization of NCF design. At first, we looked at the aspect of voids. One of the causes of voids is captured air which generates when an IC connects to NCF. This relates to the flow of resin. Regarding this flow, we looked into what encapsulant's behavior is effective in controlling voids by measuring temperature and viscosity with a rheometer. As a result, we could decrease the voids by optimizing the minimum melting viscosity. As another type, the void from volatilization gas may occur from an organic substrate. We looked at the quantity of substrate using TG-DTA, and found that it decreased by 0.4% till the temperature reached 260°C. Then we found that the higher minimum melting viscosity is, the more effectively this type of voids can be controlled. Moreover we tried to optimize minimum melting viscosity, curability and flux-ability for good interconnection. Regarding the minimum melting viscosity, when it is too high, the connection will be poor. Regarding curability, when cure speed is too high, solder melting will be blocked. We also attempted to optimize flux activity, and found that gelling time, minimum melting viscosity and oxidation-reduction power need to be controlled. Based on these approaches, it became possible to design the NCF which is voidless, has good connection, and can pass the reliability test (JEDECL3, TC1000cyc).","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"7 4 1","pages":"399-405"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83419607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248960
G. Kumar, S. Sitaraman, V. Sridharan, N. Sankaran, Fuhan Liu, N. Kumbhat, V. Nair, T. Kamgaing, F. Juskey, V. Sundaram, R. Tummala
System integration by die-embedding within electronic packages offers significant advantages in miniaturization, cost and performance for mobile devices. This paper presents the functional design and analysis of ultra-thin packages that combine embedded actives (GaAs Power Amplifier and a baseband digital IC) with embedded passives (band-pass filters), leading to an ultra-miniaturized WLAN sub-system. This chip-last design routes embedded dies in the outer build-up layer, using Embedded MEMS Actives and Passives (EMAP) technology being developed in the Georgia Tech PRC's industry consortium, as an alternative, lower cost approach over current chip-first and chip-middle methods. Electromagnetic (EM) simulations were performed in order to tune the electrical performance of interconnections based on die specifications and package configuration. The digital package was designed with multiple power-ground pair islands to enhance noise isolation, while improving overall signal and power integrity. The embedded module designs for RF transmitter and the baseband IC measure at 2.8mm × 3.2mm × 0.25mm and 10mm × 10mm × 0.25mm respectively, achieving over 4.5× volume reduction compared to existing wire-bond packages.
{"title":"Modeling and design of an ultra-miniaturized WLAN sub-system with chip-last embedded PA and digital dies","authors":"G. Kumar, S. Sitaraman, V. Sridharan, N. Sankaran, Fuhan Liu, N. Kumbhat, V. Nair, T. Kamgaing, F. Juskey, V. Sundaram, R. Tummala","doi":"10.1109/ECTC.2012.6248960","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248960","url":null,"abstract":"System integration by die-embedding within electronic packages offers significant advantages in miniaturization, cost and performance for mobile devices. This paper presents the functional design and analysis of ultra-thin packages that combine embedded actives (GaAs Power Amplifier and a baseband digital IC) with embedded passives (band-pass filters), leading to an ultra-miniaturized WLAN sub-system. This chip-last design routes embedded dies in the outer build-up layer, using Embedded MEMS Actives and Passives (EMAP) technology being developed in the Georgia Tech PRC's industry consortium, as an alternative, lower cost approach over current chip-first and chip-middle methods. Electromagnetic (EM) simulations were performed in order to tune the electrical performance of interconnections based on die specifications and package configuration. The digital package was designed with multiple power-ground pair islands to enhance noise isolation, while improving overall signal and power integrity. The embedded module designs for RF transmitter and the baseband IC measure at 2.8mm × 3.2mm × 0.25mm and 10mm × 10mm × 0.25mm respectively, achieving over 4.5× volume reduction compared to existing wire-bond packages.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"71 1","pages":"1015-1022"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83338769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249113
Sae-Kyoung Kang, J. Lee, J. Huh, J. Lee, Kwangjoon Kim
In this paper, we present the implemented a 28-Gb/s a receiver optical sub-assembly (ROSA) module by employing the proposed TO-CAN package and flexible printed circuit board (FPCB). We have proposed that signal path between the TO-CAN package and the FPCB have straight-line path and the FPCB incorporate signal line with open stub in order to alleviate signal distortion due to impedance mismatch. The 3-dB optical-to-electrical (O-E) bandwidth and receiver sensitivity of the ROSA module were measured as over 17 GHz and below -14 dBm at extinction ratio of 12 dB and bit error rate of 10-12.
{"title":"A cost-effective and compact 28-Gb/s ROSA module using a novel TO-CAN package","authors":"Sae-Kyoung Kang, J. Lee, J. Huh, J. Lee, Kwangjoon Kim","doi":"10.1109/ECTC.2012.6249113","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249113","url":null,"abstract":"In this paper, we present the implemented a 28-Gb/s a receiver optical sub-assembly (ROSA) module by employing the proposed TO-CAN package and flexible printed circuit board (FPCB). We have proposed that signal path between the TO-CAN package and the FPCB have straight-line path and the FPCB incorporate signal line with open stub in order to alleviate signal distortion due to impedance mismatch. The 3-dB optical-to-electrical (O-E) bandwidth and receiver sensitivity of the ROSA module were measured as over 17 GHz and below -14 dBm at extinction ratio of 12 dB and bit error rate of 10-12.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"15 1","pages":"1992-1996"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88016143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248964
Li Li, P. Su, J. Xue, M. Brillhart, J. Lau, P. Tzeng, C. K. Lee, C. Zhan, M. Dai, H. Chien, S. Wu
The bandwidth for high performance networking switches and routers increases two to ten times in every new generation. This in turn drives the bandwidth requirements for the Application Specific Integrated Circuits (ASICs) and their external memory devices designed for the high performance network systems. 3D IC integration with its low power, high density and high bandwidth advantages is proposed to address the bandwidth challenges between the ASIC and its external memory. This paper presents a novel 3D IC architecture that includes a silicon interposer with Through-Silicon-Vias (TSV) and interconnect wiring layers on both sides of the silicon interposer. An ASIC chip measured at 22 mm × 18 mm × 0.4 mm is attached on top of the silicon interposer while two smaller memory chips with a size of 10 mm × 10 mm × 0.4 mm are attached to the bottom of the silicon interposer with micro-bump interconnections. A unique, double-sided Chip to Chip (C2C) joining process is developed to enable the ASIC and memory integration in true 3D System-in-Package (SiP) format. This 3D IC architecture will help to overcome the size limitation of the current silicon interposers due to the reticle size used in the lithographic wafer processing. The 3D IC stack is assembled on an organic package substrate with conventional solder bumps. Communications between the top ASIC die and the bottom memory dice are made through the TSVs and the wiring layers of the silicon interposer. Thermal and thermo-mechanical analysis of the 3D IC stack are used to evaluate the package thermal performance and for optimizing material selection and package reliability. Both the modeling and experimental characterization results are used to gain insights into the 3D IC technology for addressing the ASIC and memory bandwidth challenges and to develop the best practice for ASIC and memory integration for next generation high performance network systems.
高性能网络交换机和路由器的带宽每一代增加2到10倍。这反过来又推动了为高性能网络系统设计的专用集成电路(asic)及其外部存储设备的带宽要求。提出了低功耗、高密度和高带宽的3D集成电路，以解决ASIC与外部存储器之间的带宽挑战。本文提出了一种新颖的3D集成电路架构，该架构包括具有通硅过孔(TSV)的硅中间层和硅中间层两侧的互连布线层。在硅中间层的顶部安装了尺寸为22 mm × 18 mm × 0.4 mm的ASIC芯片，在硅中间层的底部安装了两个尺寸为10 mm × 10 mm × 0.4 mm的较小的存储芯片，并通过微碰撞互连。开发了一种独特的双面芯片到芯片(C2C)连接工艺，使ASIC和存储器能够以真正的3D系统级封装(SiP)格式集成。这种3D集成电路架构将有助于克服目前由于光刻晶圆加工中使用的光栅尺寸而导致的硅中间层的尺寸限制。3D集成电路堆栈组装在具有传统焊料凸起的有机封装基板上。顶部ASIC芯片和底部存储芯片之间的通信是通过tsv和硅中间层的布线层进行的。三维集成电路堆栈的热学和热力学分析用于评估封装热性能，优化材料选择和封装可靠性。建模和实验表征结果都用于深入了解3D IC技术，以解决ASIC和内存带宽挑战，并为下一代高性能网络系统开发ASIC和内存集成的最佳实践。
{"title":"Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration","authors":"Li Li, P. Su, J. Xue, M. Brillhart, J. Lau, P. Tzeng, C. K. Lee, C. Zhan, M. Dai, H. Chien, S. Wu","doi":"10.1109/ECTC.2012.6248964","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248964","url":null,"abstract":"The bandwidth for high performance networking switches and routers increases two to ten times in every new generation. This in turn drives the bandwidth requirements for the Application Specific Integrated Circuits (ASICs) and their external memory devices designed for the high performance network systems. 3D IC integration with its low power, high density and high bandwidth advantages is proposed to address the bandwidth challenges between the ASIC and its external memory. This paper presents a novel 3D IC architecture that includes a silicon interposer with Through-Silicon-Vias (TSV) and interconnect wiring layers on both sides of the silicon interposer. An ASIC chip measured at 22 mm × 18 mm × 0.4 mm is attached on top of the silicon interposer while two smaller memory chips with a size of 10 mm × 10 mm × 0.4 mm are attached to the bottom of the silicon interposer with micro-bump interconnections. A unique, double-sided Chip to Chip (C2C) joining process is developed to enable the ASIC and memory integration in true 3D System-in-Package (SiP) format. This 3D IC architecture will help to overcome the size limitation of the current silicon interposers due to the reticle size used in the lithographic wafer processing. The 3D IC stack is assembled on an organic package substrate with conventional solder bumps. Communications between the top ASIC die and the bottom memory dice are made through the TSVs and the wiring layers of the silicon interposer. Thermal and thermo-mechanical analysis of the 3D IC stack are used to evaluate the package thermal performance and for optimizing material selection and package reliability. Both the modeling and experimental characterization results are used to gain insights into the 3D IC technology for addressing the ASIC and memory bandwidth challenges and to develop the best practice for ASIC and memory integration for next generation high performance network systems.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"43 1","pages":"1040-1046"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87437317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248893
K. Murayama, M. Higashi, T. Sakai, Nobuaki Imaizumi
In this report, we investigated electro-migration behavior of two types of low temperature bonding. One was Sn-57 Bi using conventional C4 process. The other was Au-In Transient Liquid Phase bonding (TLP). Electron flow to induce the electro-migration was from substrate side (Ni pad) to chip side (Cu post) with current density of 40000A/cm2 at 150 degree C. In the case of Sn-57 Bi conventional C4 process, Bi quickly migrated to accumulate on the anode side (Cu post) and Sn migrated to the cathode side (substrate Ni pad). And the interconnect resistance increased until about 150 hours. Although this temperature was higher than the melting point of Sn57 Bi solder, there was no electrically break failure and the resistance was stabilized at 80% increase of initial resistance for more than 2800 hours, that was 10 times longer life of the Sn3.0wt%Ag0.5wt%Cu (SAC305) solder joint. From the cross-sectional analyses of Sn-57 Bi solder joints after the test, it was found that Bi layer and intermetallic compound (IMC) behaved as the barriers of the Cu atom migration into Sn solder. In the case of Au-In TLP bonding, remarkable change was not observed in metallic structure. And resistance was stabilized at 0.5% increase of initial for more than 1300 hours. Sn57 Bi solder joining and Au-In TLP bonding are promising candidates for the bonding technique of high density Flip Chip packages and 3D packages.
{"title":"Electro-migration behavior in low temperature flip chip bonding","authors":"K. Murayama, M. Higashi, T. Sakai, Nobuaki Imaizumi","doi":"10.1109/ECTC.2012.6248893","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248893","url":null,"abstract":"In this report, we investigated electro-migration behavior of two types of low temperature bonding. One was Sn-57 Bi using conventional C4 process. The other was Au-In Transient Liquid Phase bonding (TLP). Electron flow to induce the electro-migration was from substrate side (Ni pad) to chip side (Cu post) with current density of 40000A/cm2 at 150 degree C. In the case of Sn-57 Bi conventional C4 process, Bi quickly migrated to accumulate on the anode side (Cu post) and Sn migrated to the cathode side (substrate Ni pad). And the interconnect resistance increased until about 150 hours. Although this temperature was higher than the melting point of Sn57 Bi solder, there was no electrically break failure and the resistance was stabilized at 80% increase of initial resistance for more than 2800 hours, that was 10 times longer life of the Sn3.0wt%Ag0.5wt%Cu (SAC305) solder joint. From the cross-sectional analyses of Sn-57 Bi solder joints after the test, it was found that Bi layer and intermetallic compound (IMC) behaved as the barriers of the Cu atom migration into Sn solder. In the case of Au-In TLP bonding, remarkable change was not observed in metallic structure. And resistance was stabilized at 0.5% increase of initial for more than 1300 hours. Sn57 Bi solder joining and Au-In TLP bonding are promising candidates for the bonding technique of high density Flip Chip packages and 3D packages.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"1 1","pages":"608-614"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89099336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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