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2012 IEEE 62nd Electronic Components and Technology Conference最新文献

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Polyimide based temporary wafer bonding technology for high temperature compliant TSV backside processing and thin device handling 基于聚酰亚胺的临时晶圆键合技术,用于高温兼容TSV背面加工和薄器件处理
Pub Date : 2012-07-30 DOI: 10.1109/ECTC.2012.6248966
K. Zoschke, T. Fischer, M. Topper, T. Fritzsch, O. Ehrmann, T. Itabashi, M. Zussman, M. Souter, H. Oppermann, K. Lang
Temporary wafer bonding for thin wafer processing is one of the key technologies of 3D system integration. In this context we introduce the polyimide material HD3007 which is suitable for temporary bonding of silicon wafers to carrier wafers by using a thermo compression process. Coating and bonding processes for 200 mm and 150 mm wafers with and without topography as well as two de-bonding concepts which are based on laser assisted and solvent assisted release processes are presented. Based on tests with temporary bonded 200 mm wafers, we found a very high compatibility of the bonded compound wafers with standard WLP process equipment and work flows suitable for backside processing of “via first” TSV wafers. Processes like silicon back grinding to a remaining thickness of 60 μm, dry etching, wet etching, CMP, PVD, spin coating of resists and polymers, lithography, electro plating and polymer curing were evaluated and are described in detail. Even at high temperatures up to 300°C and vacuum levels up to 10-4 mbar, the temporary bond layer was stable and no delamination occurred. 60 μm thin wafers could be processed and de-bonded without any problems using both release methods. De-bonding times of less than a couple minutes can be realized with laser assisted de-bonding and several minutes with a solvent based release. Compared to glues of other temporary handling systems, the proposed material offers the highest temperature budget for thin wafer backside processing as well as fast and easy de-bonding at room temperature.
用于薄晶片加工的临时晶圆键合是三维系统集成的关键技术之一。在这种情况下,我们介绍了聚酰亚胺材料HD3007,它适用于硅晶片和载流子晶片的临时粘接,采用热压缩工艺。介绍了200 mm和150 mm硅片的涂覆和键合工艺,以及基于激光辅助和溶剂辅助释放工艺的两种脱键概念。通过对临时粘接的200mm晶圆的测试,我们发现粘接的复合晶圆与标准的WLP工艺设备和工作流程具有非常高的兼容性,适用于“通孔优先”TSV晶圆的背面加工。对硅背磨至剩余厚度60 μm、干法蚀刻、湿法蚀刻、CMP、PVD、抗蚀剂和聚合物自旋镀膜、光刻、电镀和聚合物固化等工艺进行了评价和详细描述。即使在高达300°C的高温和高达10-4 mbar的真空度下,临时粘结层也很稳定,不会发生分层。使用这两种释放方法都可以对60 μm薄晶圆进行加工和脱粘。用激光辅助脱键可以实现不到几分钟的脱键时间,用溶剂基释放可以实现几分钟的脱键时间。与其他临时处理系统的胶水相比,该材料提供了薄晶片背面处理的最高温度预算,以及在室温下快速简便的脱粘。
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引用次数: 31
Synthesis and characterization of nanoscaled solder material 纳米钎料的合成与表征
Pub Date : 2012-07-30 DOI: 10.1109/ECTC.2012.6248914
A. Novikov, M. Nowottnick
A new concept based on the usage of ultra thin films as solder material will be presented here. For this purpose nanoscaled solder films of pure tin with the maximal thickness 100 nm were synthesized through physical vapor deposition method and then characterized with high resolution methods of scanning electron microscopy and atomic force microscopy. For the protection from oxidation during phase change analysis and also during storage and soldering process silicon nitride and carbon were sputtered in the same process chamber. The function of these coatings was tested through x-ray diffraction. The crystalline film under protective layer after cooling down is a sign for impermeability of oxygen. The thermodynamic properties like melting point and undercooling were researched with the sophisticated method of chip calorimetry that allows the measurements at very fast heating and cooling rates and therefore very small amounts of material can be studied. In the first soldering experiments passivation coatings were also tested on their convenience to produce a stable solder joint. Very promising solution for the production of stable solder joints was seen on the system consisting of alternating nanoscaled metal layers, which react during soldering process by building of an alloy. One of the components of such reactive solder systems has to serve for passivation at the same time. Carrier foil with the sputtered solder structures on its both sides can noticeably improve the stability of solder joint. After assembling at low temperature the solder structures transform into diffusion zone and the main physical properties like electrical and thermal conductivity and mechanical strength of the final solder joint are determined by the properties of the carrier foil. In this work such system consisting of silver carrier foil with nanoscaled solder layers of tin and gold was successfully tested.
本文将介绍一种基于超薄薄膜作为焊料的新概念。为此,采用物理气相沉积法合成了最大厚度为100 nm的纯锡纳米焊料膜,并用高分辨率扫描电镜和原子力显微镜对其进行了表征。为了在相变分析、储存和焊接过程中防止氧化,氮化硅和碳在同一个工艺室中溅射。通过x射线衍射测试了这些涂层的性能。冷却后保护层下的结晶膜是氧气不渗透的标志。热力学性质,如熔点和过冷用芯片量热法的复杂方法进行了研究,允许测量在非常快的加热和冷却速度,因此非常少量的材料可以研究。在第一次焊接实验中,还测试了钝化涂层是否易于产生稳定的焊点。在由交替的纳米级金属层组成的系统上,可以看到生产稳定焊点的非常有前途的解决方案,这些金属层在焊接过程中通过构建合金发生反应。这种反应性焊料系统的一个组成部分必须同时起到钝化作用。两侧有溅射焊料结构的载体箔可以明显提高焊点的稳定性。在低温下组装后,焊料结构转变为扩散区,最终焊点的电导率、导热率和机械强度等主要物理性能由载体箔的性能决定。本文成功地测试了这种由银载体箔和纳米锡金焊料层组成的系统。
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引用次数: 0
Fine pitch copper PoP for mobile applications 用于移动应用程序的细间距铜PoP
Pub Date : 2012-07-30 DOI: 10.1109/ECTC.2012.6249012
P. Damberg, I. Mohammed, R. Co
Today, memory plus logic stacking is being provided to smartphones and tablet computers by means of Package-on-Package (PoP). However, current PoP top-to-bottom interconnect technologies do not efficiently scale to provide the memory bandwidth required for new generations of multi-core applications processors. The current interconnect technologies such as stacking with smaller sized solder balls, using solder filled laser drilled vias in the mold cap or using PCB interposers are not cost effectively achieving required aspect ratios for fine pitch while overcoming package warp during soldering. To address the gap in PoP interconnect density, a wire bond based package stacking interconnect technology is studied that enables reduced pitch and a higher number of interconnects in the PoP perimeter stacking arrangement. The main technological challenges are identified and the research results explained. It is shown that the there are multiple methods for forming the wire-bonds, exposing the wires above the molded package body and connecting the top package to these wires. These results show that wire-bond interconnect technology is promising for the very high density and fine pitch required for wide IO implementations.
如今,智能手机和平板电脑通过PoP (Package-on-Package)的方式提供内存和逻辑堆叠。然而,目前的PoP自上而下互连技术不能有效地扩展到提供新一代多核应用处理器所需的内存带宽。目前的互连技术,如用较小尺寸的焊料球堆叠,在模盖中使用焊料填充的激光钻孔过孔或使用PCB中间层,在克服焊接过程中封装翘曲的同时,无法经济有效地实现所需的细间距长宽比。为了解决PoP互连密度的差距,研究了一种基于线键的封装堆叠互连技术,该技术可以在PoP周长堆叠布置中减小间距和增加互连数量。确定了主要的技术挑战,并解释了研究结果。结果表明,有多种方法可以形成线键,将成型包体上方的电线暴露出来,并将顶部的包连接到这些电线上。这些结果表明,线键互连技术有望实现宽IO实现所需的高密度和细间距。
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引用次数: 17
Development of large die fine pitch flip chip BGA using TCNCP technology 采用TCNCP技术开发大模小间距倒装芯片BGA
Pub Date : 2012-07-30 DOI: 10.1109/ECTC.2012.6248868
Yanggyoo Jung, Minjae Lee, Sunwoo Park, Do-Hyun Ryu, Youshin Jung, Chanha Hwang, Choonheung Lee, Sungsoon Park, M. Jimarez, Myung-June Lee
Recently, technologies related to Fine Pitch Flip Chip or FPFC have been great achievements for various next generation devices, allowing a significant increase in the number of signal I/O and achieving low form factor packages. Consequently, fine pitch Cu pillar flip chip Chip Scale Package (CSP) with small sized die, with package dimension of less than 16×16mm, is already under high volume production using the Thermal-Compression Bonding with Non-conductive Paste (TCNCP) technology [1-2]. In the case of Flip Chip Ball Grid Array (FCBGA), there is a growing need for FPFC technology with Cu pillar in supporting next generation silicon node. However, there will be a high possibility of yield drop issue in conventional mass-reflow process and potential reliability due to the highly concerned tensile stress between low k die and substrate by CTE mismatch especially at the edge of the die. This can be a critical quality issue for fine pitch devices compared to normal pitch (i.e., 150um) flip chip BGA. Therefore, TCNCP bonding as an alternative should be studied on fine pitch Cu pillar flip chip BGA. This paper will discuss fine pitch flip chip assembly technology for large sized flip chip BGA. Two kinds of assembly method, mass reflow bonding versus thermal compression bonding, for the flip chip bonding will be compared for the large FPFCBGA package. Meanwhile, the advantage of TC bonding with pre-applied underfill process will be described. For robust interconnection between die and substrate for large FPFCBGA, the result of the bonding test will be described with several surface finishes such as ENEPIG, Direct Immersion Gold (DIG), Immersion Tin (IT), and Solder Coating on substrate. Interestingly, one of selected surface finishes has shown excellent reliability test results. Finally, this paper will discuss an effective approach for fine pitch devices from an assembly perspective.
最近,与细间距倒装芯片或FPFC相关的技术在各种下一代设备中取得了巨大成就,可以显着增加信号I/O数量并实现低尺寸封装。因此,采用小尺寸芯片、封装尺寸小于16×16mm的细间距铜柱倒装芯片芯片规模封装(CSP)已经采用非导电浆料热压缩键合(TCNCP)技术进行了大批量生产[1-2]。以倒装芯片球栅阵列(FCBGA)为例,对铜柱FPFC技术的需求日益增长,以支持下一代硅节点。然而,在传统的质量回流工艺中,由于CTE不匹配引起的低k模具和基板之间的高度关注的拉伸应力,特别是在模具边缘,将有很高的可能性出现良率下降问题和潜在的可靠性。与正常间距(即150um)倒装芯片BGA相比,这可能是细间距器件的关键质量问题。因此,在细间距铜柱倒装芯片BGA上研究TCNCP键合作为替代方案。本文将讨论用于大尺寸倒装芯片BGA的小间距倒装芯片组装技术。对于大型FPFCBGA封装,将比较两种用于倒装芯片键合的组装方法,质量回流键合和热压缩键合。同时,介绍了预加底填工艺的TC粘接的优点。为了在大型FPFCBGA的芯片和基板之间实现坚固的互连,结合测试的结果将通过几种表面处理来描述,例如ENEPIG,直接浸金(DIG),浸锡(IT)和基板上的焊料涂层。有趣的是,其中一种表面处理显示出优异的可靠性测试结果。最后,本文将从装配的角度讨论一种有效的方法。
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引用次数: 21
System-level SoC near-field (NF) emissions: Simulation to measurement correlation 系统级SoC近场(NF)排放:模拟与测量的相关性
Pub Date : 2012-07-30 DOI: 10.1109/ECTC.2012.6248819
R. Murugan, S. Mukherjee, M. Mi, L. Pauc, C. Girardi, D. Gope, D. de Araujo, S. Chakraborty, V. Jandhyala
As System-on-Chip (SoC) designs migrate to 28nm process node and beyond, the electromagnetic (EM) co-interactions of the Chip-Package-Printed Circuit Board (PCB) becomes critical and require accurate and efficient characterization and verification. In this paper a fast, scalable, and parallelized boundary element based integral EM solutions to Maxwell equations is presented. The accuracy of the full-wave formulation, for complete EM characterization, has been validated on both canonical structures and real-world 3-D system (viz. Chip + Package + PCB). Good correlation between numerical simulation and measurement has been achieved. A few examples of the applicability of the formulation to high speed digital and analog serial interfaces on a 45nm SoC are also presented.
随着片上系统(SoC)设计迁移到28nm及以上工艺节点,芯片封装印刷电路板(PCB)的电磁(EM)协同作用变得至关重要,需要准确高效的表征和验证。本文提出了一种基于边界元的麦克斯韦方程组的快速、可扩展、并行化的积分EM解。对于完整的EM表征,全波公式的准确性已在规范结构和现实世界的3-D系统(即芯片+封装+ PCB)上得到验证。数值模拟结果与实测结果具有良好的相关性。还给出了该公式在45nm SoC上的高速数字和模拟串行接口适用性的几个示例。
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引用次数: 5
Effect of NCF design for the assembly of Flip Chip and reliability NCF设计对倒装芯片组装及可靠性的影响
Pub Date : 2012-07-30 DOI: 10.1109/ECTC.2012.6248861
S. Kawamoto, M. Yoshida, S. Teraki, H. Iida
Recently, design of Flip Chip (FC) Package is changing with the higher density of the Package. Conventional process with Capillary Underfill (CUF) is not applicable to PKGs such as 3D and chip stacked types. To solve these problems, other processes are being developed in which an encapsulant is applied on a substrate before bonding IC. One of those is the process with Non Conductive Film (NCF). In this process, after NCF is applied, IC is bonded. Interconnection and NCF cure are done at the same time. Therefore, the design of NCF has great influences to FC assembly in terms of void, interconnectability and reliability. Thus, in this paper, we are mainly discussing the optimization of NCF design. At first, we looked at the aspect of voids. One of the causes of voids is captured air which generates when an IC connects to NCF. This relates to the flow of resin. Regarding this flow, we looked into what encapsulant's behavior is effective in controlling voids by measuring temperature and viscosity with a rheometer. As a result, we could decrease the voids by optimizing the minimum melting viscosity. As another type, the void from volatilization gas may occur from an organic substrate. We looked at the quantity of substrate using TG-DTA, and found that it decreased by 0.4% till the temperature reached 260°C. Then we found that the higher minimum melting viscosity is, the more effectively this type of voids can be controlled. Moreover we tried to optimize minimum melting viscosity, curability and flux-ability for good interconnection. Regarding the minimum melting viscosity, when it is too high, the connection will be poor. Regarding curability, when cure speed is too high, solder melting will be blocked. We also attempted to optimize flux activity, and found that gelling time, minimum melting viscosity and oxidation-reduction power need to be controlled. Based on these approaches, it became possible to design the NCF which is voidless, has good connection, and can pass the reliability test (JEDECL3, TC1000cyc).
近年来,随着封装密度的提高,倒装芯片(FC)封装的设计也在发生变化。传统的毛细管下填充(CUF)工艺不适用于3D和芯片堆叠型pkg。为了解决这些问题,人们正在开发其他工艺,在粘合IC之前在基板上涂上封装剂。其中一种是使用非导电膜(NCF)的工艺。在这个过程中,应用NCF后,IC被粘合。互连和NCF固化同时进行。因此,NCF的设计对FC组件的空隙性、互连性和可靠性有很大的影响。因此,本文主要讨论NCF设计的优化问题。首先,我们从空洞的角度出发。产生空洞的原因之一是当IC连接到NCF时产生的捕获空气。这与树脂的流动有关。对于这种流动,我们通过流变仪测量温度和粘度,研究了密封剂在控制空隙方面的有效行为。因此,我们可以通过优化最小熔融粘度来减少空隙。作为另一种类型,挥发气体产生的空洞可能来自有机基质。我们使用TG-DTA观察底物的数量,发现在温度达到260°C时,底物的数量减少了0.4%。结果表明,最小熔点粘度越高,对此类空洞的控制效果越好。此外,我们试图优化最小熔融粘度,固化性和助熔性,以实现良好的互连。对于最小熔融粘度,当它太高时,连接会很差。关于固化性,当固化速度过高时,焊料熔化会受阻。我们还尝试优化助熔剂活性,发现需要控制胶凝时间、最小熔融粘度和氧化还原功率。在此基础上,设计出无空隙、连接良好、能通过可靠性试验(JEDECL3、TC1000cyc)的NCF成为可能。
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引用次数: 11
Modeling and design of an ultra-miniaturized WLAN sub-system with chip-last embedded PA and digital dies 基于片末嵌入式PA和数字芯片的超小型WLAN子系统的建模与设计
Pub Date : 2012-07-30 DOI: 10.1109/ECTC.2012.6248960
G. Kumar, S. Sitaraman, V. Sridharan, N. Sankaran, Fuhan Liu, N. Kumbhat, V. Nair, T. Kamgaing, F. Juskey, V. Sundaram, R. Tummala
System integration by die-embedding within electronic packages offers significant advantages in miniaturization, cost and performance for mobile devices. This paper presents the functional design and analysis of ultra-thin packages that combine embedded actives (GaAs Power Amplifier and a baseband digital IC) with embedded passives (band-pass filters), leading to an ultra-miniaturized WLAN sub-system. This chip-last design routes embedded dies in the outer build-up layer, using Embedded MEMS Actives and Passives (EMAP) technology being developed in the Georgia Tech PRC's industry consortium, as an alternative, lower cost approach over current chip-first and chip-middle methods. Electromagnetic (EM) simulations were performed in order to tune the electrical performance of interconnections based on die specifications and package configuration. The digital package was designed with multiple power-ground pair islands to enhance noise isolation, while improving overall signal and power integrity. The embedded module designs for RF transmitter and the baseband IC measure at 2.8mm × 3.2mm × 0.25mm and 10mm × 10mm × 0.25mm respectively, achieving over 4.5× volume reduction compared to existing wire-bond packages.
电子封装内嵌模的系统集成为移动设备提供了小型化、成本和性能方面的显著优势。本文介绍了超薄封装的功能设计和分析,该封装结合了嵌入式有源(GaAs功率放大器和基带数字IC)和嵌入式无源(带通滤波器),从而实现了超小型化的WLAN子系统。这种芯片最后的设计路线嵌入封装层的芯片,使用嵌入式MEMS有源和无源(EMAP)技术正在开发的佐治亚理工学院中国的行业联盟,作为替代方案,比目前的芯片第一和芯片中间的方法成本更低。为了根据模具规格和封装配置调整互连的电性能,进行了电磁(EM)仿真。数字封装设计了多个电源-地对岛,以增强噪声隔离,同时提高整体信号和电源完整性。射频发射器的嵌入式模块设计和基带IC的尺寸分别为2.8mm × 3.2mm × 0.25mm和10mm × 10mm × 0.25mm,与现有的线键封装相比,体积缩小了4.5倍以上。
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引用次数: 4
A cost-effective and compact 28-Gb/s ROSA module using a novel TO-CAN package 采用新型TO-CAN封装的经济高效、紧凑的28 gb /s ROSA模块
Pub Date : 2012-07-30 DOI: 10.1109/ECTC.2012.6249113
Sae-Kyoung Kang, J. Lee, J. Huh, J. Lee, Kwangjoon Kim
In this paper, we present the implemented a 28-Gb/s a receiver optical sub-assembly (ROSA) module by employing the proposed TO-CAN package and flexible printed circuit board (FPCB). We have proposed that signal path between the TO-CAN package and the FPCB have straight-line path and the FPCB incorporate signal line with open stub in order to alleviate signal distortion due to impedance mismatch. The 3-dB optical-to-electrical (O-E) bandwidth and receiver sensitivity of the ROSA module were measured as over 17 GHz and below -14 dBm at extinction ratio of 12 dB and bit error rate of 10-12.
在本文中,我们提出了一个28 gb /s的接收器光学子组件(ROSA)模块,采用所提出的TO-CAN封装和柔性印刷电路板(FPCB)。我们建议在to - can封装和FPCB之间的信号路径具有直线路径,FPCB将信号线与开存根合并,以减轻由于阻抗不匹配引起的信号失真。在消光比为12 dB、误码率为10-12的条件下,ROSA模块的3db光电(O-E)带宽和接收灵敏度分别在17 GHz以上和-14 dBm以下。
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引用次数: 2
Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration 通过3D集成电路解决下一代高性能网络系统中的带宽挑战
Pub Date : 2012-07-30 DOI: 10.1109/ECTC.2012.6248964
Li Li, P. Su, J. Xue, M. Brillhart, J. Lau, P. Tzeng, C. K. Lee, C. Zhan, M. Dai, H. Chien, S. Wu
The bandwidth for high performance networking switches and routers increases two to ten times in every new generation. This in turn drives the bandwidth requirements for the Application Specific Integrated Circuits (ASICs) and their external memory devices designed for the high performance network systems. 3D IC integration with its low power, high density and high bandwidth advantages is proposed to address the bandwidth challenges between the ASIC and its external memory. This paper presents a novel 3D IC architecture that includes a silicon interposer with Through-Silicon-Vias (TSV) and interconnect wiring layers on both sides of the silicon interposer. An ASIC chip measured at 22 mm × 18 mm × 0.4 mm is attached on top of the silicon interposer while two smaller memory chips with a size of 10 mm × 10 mm × 0.4 mm are attached to the bottom of the silicon interposer with micro-bump interconnections. A unique, double-sided Chip to Chip (C2C) joining process is developed to enable the ASIC and memory integration in true 3D System-in-Package (SiP) format. This 3D IC architecture will help to overcome the size limitation of the current silicon interposers due to the reticle size used in the lithographic wafer processing. The 3D IC stack is assembled on an organic package substrate with conventional solder bumps. Communications between the top ASIC die and the bottom memory dice are made through the TSVs and the wiring layers of the silicon interposer. Thermal and thermo-mechanical analysis of the 3D IC stack are used to evaluate the package thermal performance and for optimizing material selection and package reliability. Both the modeling and experimental characterization results are used to gain insights into the 3D IC technology for addressing the ASIC and memory bandwidth challenges and to develop the best practice for ASIC and memory integration for next generation high performance network systems.
高性能网络交换机和路由器的带宽每一代增加2到10倍。这反过来又推动了为高性能网络系统设计的专用集成电路(asic)及其外部存储设备的带宽要求。提出了低功耗、高密度和高带宽的3D集成电路,以解决ASIC与外部存储器之间的带宽挑战。本文提出了一种新颖的3D集成电路架构,该架构包括具有通硅过孔(TSV)的硅中间层和硅中间层两侧的互连布线层。在硅中间层的顶部安装了尺寸为22 mm × 18 mm × 0.4 mm的ASIC芯片,在硅中间层的底部安装了两个尺寸为10 mm × 10 mm × 0.4 mm的较小的存储芯片,并通过微碰撞互连。开发了一种独特的双面芯片到芯片(C2C)连接工艺,使ASIC和存储器能够以真正的3D系统级封装(SiP)格式集成。这种3D集成电路架构将有助于克服目前由于光刻晶圆加工中使用的光栅尺寸而导致的硅中间层的尺寸限制。3D集成电路堆栈组装在具有传统焊料凸起的有机封装基板上。顶部ASIC芯片和底部存储芯片之间的通信是通过tsv和硅中间层的布线层进行的。三维集成电路堆栈的热学和热力学分析用于评估封装热性能,优化材料选择和封装可靠性。建模和实验表征结果都用于深入了解3D IC技术,以解决ASIC和内存带宽挑战,并为下一代高性能网络系统开发ASIC和内存集成的最佳实践。
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引用次数: 37
Electro-migration behavior in low temperature flip chip bonding 低温倒装芯片键合中的电迁移行为
Pub Date : 2012-07-30 DOI: 10.1109/ECTC.2012.6248893
K. Murayama, M. Higashi, T. Sakai, Nobuaki Imaizumi
In this report, we investigated electro-migration behavior of two types of low temperature bonding. One was Sn-57 Bi using conventional C4 process. The other was Au-In Transient Liquid Phase bonding (TLP). Electron flow to induce the electro-migration was from substrate side (Ni pad) to chip side (Cu post) with current density of 40000A/cm2 at 150 degree C. In the case of Sn-57 Bi conventional C4 process, Bi quickly migrated to accumulate on the anode side (Cu post) and Sn migrated to the cathode side (substrate Ni pad). And the interconnect resistance increased until about 150 hours. Although this temperature was higher than the melting point of Sn57 Bi solder, there was no electrically break failure and the resistance was stabilized at 80% increase of initial resistance for more than 2800 hours, that was 10 times longer life of the Sn3.0wt%Ag0.5wt%Cu (SAC305) solder joint. From the cross-sectional analyses of Sn-57 Bi solder joints after the test, it was found that Bi layer and intermetallic compound (IMC) behaved as the barriers of the Cu atom migration into Sn solder. In the case of Au-In TLP bonding, remarkable change was not observed in metallic structure. And resistance was stabilized at 0.5% increase of initial for more than 1300 hours. Sn57 Bi solder joining and Au-In TLP bonding are promising candidates for the bonding technique of high density Flip Chip packages and 3D packages.
在本报告中,我们研究了两种低温键合的电迁移行为。一种是采用常规C4工艺的sn - 57bi。另一种是Au-In瞬态液相键合(TLP)。在150℃下,诱导电迁移的电子流从衬底侧(Ni垫)流向芯片侧(Cu垫),电流密度为40000A/cm2。在Sn- 57bi常规C4工艺中,Bi快速迁移到阳极侧(Cu柱)积累,Sn迁移到阴极侧(衬底Ni垫)。互连电阻增加到150小时左右。虽然该温度高于Sn57 Bi焊料的熔点,但未发生电断失效,且电阻稳定在初始电阻增加80%以上,使用时间超过2800小时,是Sn3.0wt%Ag0.5wt%Cu (SAC305)焊点寿命的10倍。从试验后Sn-57 Bi焊点的截面分析中发现,Bi层和金属间化合物(IMC)是Cu原子向Sn焊点迁移的障碍。在Au-In TLP键合的情况下,金属结构没有明显变化。1300小时以上,电阻稳定在初始值增加0.5%的水平。Sn57 Bi焊料连接和Au-In TLP键合是高密度倒装芯片和3D封装的有前途的键合技术。
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引用次数: 11
期刊
2012 IEEE 62nd Electronic Components and Technology Conference
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