Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248925
M. Wilke, M. Topper, Hue Quoc Huynh, K. Lang
One of the key technologies for 3D packaging is forming the Through Silicon Vias (TSV) using plasma etching. For the 3D packaging of active devices such as CMOS sensors, which exhibit low to moderate I/O counts, it was shown in recent years, that costs for TSV interconnects can be reduced by producing tapered via features, which ease subsequent process steps such as deposition of dielectrics, metal layers and photo resists. For different applications the adjustment of dedicated via profiles is desirable. For the practical use the process engineer is confronted with a variety of different process parameters, which exhibit strong interactions between each other and therefore make an extensive testing necessary when a new process needs to be developed. The knowledge of these interactions is therefore needed. The etching of tapered TSVs using fluorine based chemistry is discussed in this paper. The influence of the governing process parameters such as pressure, gas flow ratio and power is discussed in order to produce profiles with continuous tangent and minimal surface roughness of the structures. Emerging structures with etching effects such as micro masking or the appearance of profiles with gradient taper are shown in order to reveal guidelines in which direction the process needs to be adjusted to stay in the process window. A model is presented and discussed which is able to predict the profile angle as a function of the process parameters. This gives the ability to produce tapered profiles from 65° to 85° without the burden of an enormous experimental effort. Interrelated etching performance such as photoresist selectivity, etching rate and the occurrence of lateral under etching is presented as well so that design rules can be derived for the specific process.
{"title":"Process modeling of dry etching for the 3D-integration with tapered TSVs","authors":"M. Wilke, M. Topper, Hue Quoc Huynh, K. Lang","doi":"10.1109/ECTC.2012.6248925","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248925","url":null,"abstract":"One of the key technologies for 3D packaging is forming the Through Silicon Vias (TSV) using plasma etching. For the 3D packaging of active devices such as CMOS sensors, which exhibit low to moderate I/O counts, it was shown in recent years, that costs for TSV interconnects can be reduced by producing tapered via features, which ease subsequent process steps such as deposition of dielectrics, metal layers and photo resists. For different applications the adjustment of dedicated via profiles is desirable. For the practical use the process engineer is confronted with a variety of different process parameters, which exhibit strong interactions between each other and therefore make an extensive testing necessary when a new process needs to be developed. The knowledge of these interactions is therefore needed. The etching of tapered TSVs using fluorine based chemistry is discussed in this paper. The influence of the governing process parameters such as pressure, gas flow ratio and power is discussed in order to produce profiles with continuous tangent and minimal surface roughness of the structures. Emerging structures with etching effects such as micro masking or the appearance of profiles with gradient taper are shown in order to reveal guidelines in which direction the process needs to be adjusted to stay in the process window. A model is presented and discussed which is able to predict the profile angle as a function of the process parameters. This gives the ability to produce tapered profiles from 65° to 85° without the burden of an enormous experimental effort. Interrelated etching performance such as photoresist selectivity, etching rate and the occurrence of lateral under etching is presented as well so that design rules can be derived for the specific process.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"46 1","pages":"803-809"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86723996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248985
Y. Liu, Qiuxiao Qian, M. Ring, Jihwan Kim, D. Kinzer
Comprehensive finite element analysis (FEA) modeling is carried out to improve the performance of critical designs of wafer level chip scale package (WLCSP). First, a design with one layer redistribution layout (RDL) copper with etched pocket in the non-covered UBM area and one layer polyimide structure (1Cu1Pi design) is investigated. Different polyimide layouts, copper thicknesses, pocket parameters and non-covered UBM diameters are studied through finite element modeling. Then, a stacked metal design with the sputtered copper UBM stacked on the RDL copper layer, with one polyimide layer between them (2Cu1Pi) for the WLCSP is examined. Parameter study of different UBM diameters with the same solder volume and different UBM diameters with the same solder joint height is conducted by the simulation. Finally the correlation and comparison of the failure mechanism between the modeling and the test are presented and discussed.
{"title":"Modeling for critical design and performance of wafer level chip scale package","authors":"Y. Liu, Qiuxiao Qian, M. Ring, Jihwan Kim, D. Kinzer","doi":"10.1109/ECTC.2012.6248985","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248985","url":null,"abstract":"Comprehensive finite element analysis (FEA) modeling is carried out to improve the performance of critical designs of wafer level chip scale package (WLCSP). First, a design with one layer redistribution layout (RDL) copper with etched pocket in the non-covered UBM area and one layer polyimide structure (1Cu1Pi design) is investigated. Different polyimide layouts, copper thicknesses, pocket parameters and non-covered UBM diameters are studied through finite element modeling. Then, a stacked metal design with the sputtered copper UBM stacked on the RDL copper layer, with one polyimide layer between them (2Cu1Pi) for the WLCSP is examined. Parameter study of different UBM diameters with the same solder volume and different UBM diameters with the same solder joint height is conducted by the simulation. Finally the correlation and comparison of the failure mechanism between the modeling and the test are presented and discussed.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"24 1","pages":"1174-1182"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88210269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249010
A. Ghannam, D. Bourrier, L. Ourak, C. Viallon, T. Parra
This work presents a new and low cost multi-level 3D copper interconnect process for RF and microwave applications. This process extends 3D interconnect integration technologies from silicon to above-IC polymer. Therefore, 3D passive devices and multi-level interconnects can be integrated using a single electroplating step making the process suitable for 3D-MMIC integration. 3D interconnects are realized by patterning the SU-8 to specific locations to create the desired 3D shape. A 3D seed layer is deposited above the SU-8 and the substrate to insure 3D electroplating current flow. The BPN is used as a thick mold for copper electroplating with an aspect ratio as high as 16:1. An optimized electroplating process is later used to grow copper in a 3D technique, insuring transition between all metallic layers. Finally, high-Q (60 @ 6 GHz) power inductors have been designed and integrated above a 50 W RF power LDMOS device, using this process.
本文提出了一种新的、低成本的、用于射频和微波应用的多层三维铜互连工艺。该工艺将3D互连集成技术从硅扩展到ic以上聚合物。因此，3D无源器件和多层次互连可以使用单个电镀步骤集成，使该工艺适合3D- mmic集成。3D互连是通过将SU-8图案化到特定位置以创建所需的3D形状来实现的。3D种子层沉积在SU-8和基板之上，以确保3D电镀电流的流动。BPN是电镀铜用的厚模，宽高比高达16:1。优化的电镀工艺随后用于在3D技术中生长铜，确保所有金属层之间的过渡。最后，采用该工艺设计了高q (60 @ 6 GHz)功率电感器，并将其集成在50 W RF功率LDMOS器件上。
{"title":"Low cost 3D multilevel interconnect integration for RF and microwave applications","authors":"A. Ghannam, D. Bourrier, L. Ourak, C. Viallon, T. Parra","doi":"10.1109/ECTC.2012.6249010","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249010","url":null,"abstract":"This work presents a new and low cost multi-level 3D copper interconnect process for RF and microwave applications. This process extends 3D interconnect integration technologies from silicon to above-IC polymer. Therefore, 3D passive devices and multi-level interconnects can be integrated using a single electroplating step making the process suitable for 3D-MMIC integration. 3D interconnects are realized by patterning the SU-8 to specific locations to create the desired 3D shape. A 3D seed layer is deposited above the SU-8 and the substrate to insure 3D electroplating current flow. The BPN is used as a thick mold for copper electroplating with an aspect ratio as high as 16:1. An optimized electroplating process is later used to grow copper in a 3D technique, insuring transition between all metallic layers. Finally, high-Q (60 @ 6 GHz) power inductors have been designed and integrated above a 50 W RF power LDMOS device, using this process.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"17 1","pages":"1351-1355"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87484836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248799
E. Morinaga, Y. Oka, H. Nishimori, H. Miyagawa, R. Satoh, Y. Iwata, R. Kanezaki
The three dimensional system in package (3D-SiP) has been regarded as a promising solution to the scaling limit problem in the semiconductor industry. Practical realization of the 3D-SiP needs establishing a standard bonding technology for chip stacking. This research focuses on a low temperature and high heat-resistant fluxless bonding method, which can overcome the bump height variation problem in a chip/wafer, using high-boiling alcohol, an indium-tin (InSn) thin film and its transformation into high-melting intermetallic compound (IMC). Experimental studies showed high-rate deposition of InSn alloy and successive deposition of silver achieve successful bonding where the joint has high melting point (higher than 673K).
{"title":"Study of low temperature and high heat-resistant fluxless bonding via nanoscale thin film control toward wafer-level multiple chip stacking for 3D LSI","authors":"E. Morinaga, Y. Oka, H. Nishimori, H. Miyagawa, R. Satoh, Y. Iwata, R. Kanezaki","doi":"10.1109/ECTC.2012.6248799","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248799","url":null,"abstract":"The three dimensional system in package (3D-SiP) has been regarded as a promising solution to the scaling limit problem in the semiconductor industry. Practical realization of the 3D-SiP needs establishing a standard bonding technology for chip stacking. This research focuses on a low temperature and high heat-resistant fluxless bonding method, which can overcome the bump height variation problem in a chip/wafer, using high-boiling alcohol, an indium-tin (InSn) thin film and its transformation into high-melting intermetallic compound (IMC). Experimental studies showed high-rate deposition of InSn alloy and successive deposition of silver achieve successful bonding where the joint has high melting point (higher than 673K).","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"4 1","pages":"14-19"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80675154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248967
R. Dunne, Yoshimi Takahashi, Kazuaki Mawatari, Masamitsu Matsuura, Tom Bonifield, Philipp Steinmann, D. Stepniak
To enable the miniaturization, electrical performance and heterogeneous functionality needs for emerging Analog applications, a stacked Wafer-level Chip Scale Package (WCSP) package platform has been developed using Through-Silicon Via (TSV) technology. This allows stacking of ICs, MEMS, passives and other components in the vertical direction onto active or passive TSV wafers, to create innovative System-in-Package (SiP) product solutions. Since Analog devices are small in size and cost is a key care about, a careful selection of the integration flow is required to achieve a low cost packaging solution. In this work, an integration flow for the stacked WCSP package is presented, along with development details for the Chip-on-Wafer (CoW) bonding and wafer overmolding unit processes. The test vehicle was 3mm × 3mm in size and used 25u diameter Cu TSVs in a 200mm diameter wafer. Interconnect reliability evaluations were done with different micro-bump Under Bump Metallurgy (UBM) and TSV tip surface finish metallization combinations. Wafer ovemolding development included warpage, saw and adhesion evaluations with multiple mold materials. A back-end assembly flow was established with a mass reflow bonding process and an overmold material with low CTE and intermediate Tg and modulus. Samples were prepared with mold-on-die and exposed die package structures. Excellent time-zero yields were obtained, with an average TSV micro-bump interconnect resistance of 25 mohms. Results and failures modes from preliminary reliability testing are included.
{"title":"Development of a stacked WCSP package platform using TSV (Through Silicon Via) technology","authors":"R. Dunne, Yoshimi Takahashi, Kazuaki Mawatari, Masamitsu Matsuura, Tom Bonifield, Philipp Steinmann, D. Stepniak","doi":"10.1109/ECTC.2012.6248967","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248967","url":null,"abstract":"To enable the miniaturization, electrical performance and heterogeneous functionality needs for emerging Analog applications, a stacked Wafer-level Chip Scale Package (WCSP) package platform has been developed using Through-Silicon Via (TSV) technology. This allows stacking of ICs, MEMS, passives and other components in the vertical direction onto active or passive TSV wafers, to create innovative System-in-Package (SiP) product solutions. Since Analog devices are small in size and cost is a key care about, a careful selection of the integration flow is required to achieve a low cost packaging solution. In this work, an integration flow for the stacked WCSP package is presented, along with development details for the Chip-on-Wafer (CoW) bonding and wafer overmolding unit processes. The test vehicle was 3mm × 3mm in size and used 25u diameter Cu TSVs in a 200mm diameter wafer. Interconnect reliability evaluations were done with different micro-bump Under Bump Metallurgy (UBM) and TSV tip surface finish metallization combinations. Wafer ovemolding development included warpage, saw and adhesion evaluations with multiple mold materials. A back-end assembly flow was established with a mass reflow bonding process and an overmold material with low CTE and intermediate Tg and modulus. Samples were prepared with mold-on-die and exposed die package structures. Excellent time-zero yields were obtained, with an average TSV micro-bump interconnect resistance of 25 mohms. Results and failures modes from preliminary reliability testing are included.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"19 1","pages":"1062-1067"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78231569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249084
J. Lo, S. Lee, Rong Zhang, Mei Li
Solid state lighting is a good alternative light source with reduced energy consumption. Light-emitting diode (LED) is very efficient in turning electrical energy into light. LED has a number of advantages over the traditional light sources. The optical performance of the LED component is very critical. In general, white light can be obtained by applying phosphor on a blue LED chip. The blue light from the LED excites the phosphor to emit yellow light. The blue and yellow light mixes together to give white light. In order to obtain a good optical performance, it is necessary to apply phosphor properly. It is challenging to distribute a right amount of phosphor on the LED die. Besides, phosphor dispensing is usually the slowest process when compared with die bonding and wire bonding. This controls the overall throughput of the LED packaging process. There are different methods to apply the phosphor. The phosphor is mixed with epoxy or silicone to form slurry and is then dispensed onto the chip. However, the spatial color distribution is poor if phosphor slurry is used. Conformal phosphor coating can be used to improve the spatial color distribution. In this paper, an innovative phosphor stencil printing method is proposed. This paper demonstrates the feasibility of the phosphor stencil printing process for wafer-level LED packaging. LEDs are first mounted on a wafer submount. Wire bonds are used as interconnect. The phosphor is stencil printed on the chip surface after wire bond. The minimum phosphor layer thickness is controlled by the wire bond loop height. In order to achieve a low loop height, reverse wire bonding is used. The first bond is on the wafer submount and the second bond is on the LED chip. The reverse wire bond has a very low profile which allows a thin layer of phosphor to be printed on the chip surface. Prototypes are successfully fabricated. A uniform layer of phosphor is stencil printed on the LED chip on the wafer submount. Experimental result shows that the proposed phosphor printing method is very effective in distributing the right amount of phosphor on the chip surface.
{"title":"Reverse wire bonding and phosphor printing for LED wafer level packaging","authors":"J. Lo, S. Lee, Rong Zhang, Mei Li","doi":"10.1109/ECTC.2012.6249084","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249084","url":null,"abstract":"Solid state lighting is a good alternative light source with reduced energy consumption. Light-emitting diode (LED) is very efficient in turning electrical energy into light. LED has a number of advantages over the traditional light sources. The optical performance of the LED component is very critical. In general, white light can be obtained by applying phosphor on a blue LED chip. The blue light from the LED excites the phosphor to emit yellow light. The blue and yellow light mixes together to give white light. In order to obtain a good optical performance, it is necessary to apply phosphor properly. It is challenging to distribute a right amount of phosphor on the LED die. Besides, phosphor dispensing is usually the slowest process when compared with die bonding and wire bonding. This controls the overall throughput of the LED packaging process. There are different methods to apply the phosphor. The phosphor is mixed with epoxy or silicone to form slurry and is then dispensed onto the chip. However, the spatial color distribution is poor if phosphor slurry is used. Conformal phosphor coating can be used to improve the spatial color distribution. In this paper, an innovative phosphor stencil printing method is proposed. This paper demonstrates the feasibility of the phosphor stencil printing process for wafer-level LED packaging. LEDs are first mounted on a wafer submount. Wire bonds are used as interconnect. The phosphor is stencil printed on the chip surface after wire bond. The minimum phosphor layer thickness is controlled by the wire bond loop height. In order to achieve a low loop height, reverse wire bonding is used. The first bond is on the wafer submount and the second bond is on the LED chip. The reverse wire bond has a very low profile which allows a thin layer of phosphor to be printed on the chip surface. Prototypes are successfully fabricated. A uniform layer of phosphor is stencil printed on the LED chip on the wafer submount. Experimental result shows that the proposed phosphor printing method is very effective in distributing the right amount of phosphor on the chip surface.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"34 1","pages":"1814-1818"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85448884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248798
J. Roullard, A. Farcy, S. Capraro, T. Lacrevaz, C. Bermond, G. Houzet, J. Charbonnier, C. Fuchs, C. Ferrandon, P. Leduc, B. Fléchet
3D stacking technologies are electrically studied to predict high speed data transmission for memory on logic applications. Maximal frequency of bandwidth for memory-processor and processor-BGA channels are extracted and compared for Face to Face and Face to Back 3D stacking and between an interposer technology. Using expected electrical specifications of Wide IO applications in terms of data rates, a roadmap is proposed in accordance to the integration density, carried out by the TSV density.
对三维堆叠技术进行了电学研究，以预测存储在逻辑应用中的高速数据传输。提取了存储器-处理器和处理器- bga通道的最大带宽频率，并对Face to Face和Face to Back 3D叠加以及中间体技术进行了比较。根据数据速率方面宽IO应用的预期电气规范，根据TSV密度执行的集成密度提出了路线图。
{"title":"Evaluation of 3D interconnect routing and stacking strategy to optimize high speed signal transmission for memory on logic","authors":"J. Roullard, A. Farcy, S. Capraro, T. Lacrevaz, C. Bermond, G. Houzet, J. Charbonnier, C. Fuchs, C. Ferrandon, P. Leduc, B. Fléchet","doi":"10.1109/ECTC.2012.6248798","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248798","url":null,"abstract":"3D stacking technologies are electrically studied to predict high speed data transmission for memory on logic applications. Maximal frequency of bandwidth for memory-processor and processor-BGA channels are extracted and compared for Face to Face and Face to Back 3D stacking and between an interposer technology. Using expected electrical specifications of Wide IO applications in terms of data rates, a roadmap is proposed in accordance to the integration density, carried out by the TSV density.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"36 1","pages":"8-13"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85451585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249130
Xiaoyu Cheng, E. David, Y. Yoon
A compact frequency equalizer based on distributed passive circuits is designed, analyzed and implemented for the front end circuit of a portable spectrum analyzer working between 100MHz to 7 GHz. The equalizer is based on a T-shape passive attenuator consisting of multiple distributed inductive and capacitive elements. As a test vehicle, a 3-stage broadband amplifier has been implemented, connected to the designed equalizer, and characterized in the targeted frequency range. Without the equalizer, the measured gain of the implemented amplifier varies from 34.7 dB to 46.97 dB showing a 12.27 dB roll off in the frequency range. After connecting the equalizer, overall gain variation is reduced to ± 1.1dB. Compared with other preexisting frequency equalizers, the implemented one features a small footprint of 6×8 mm2 and a wide frequency bandwidth of 100MHz to 7GHz. Detail description on the equivalent circuit model and general design guidelines are given, and parametric analysis is performed. The implemented equalizer is suitable for the front end circuits of compact broadband test and measurement instruments, such as a portable spectrum analyzer and vector network analyzer.
{"title":"A compact 100 MHz to 7 GHz frequency equalizer based on distributed passive circuits","authors":"Xiaoyu Cheng, E. David, Y. Yoon","doi":"10.1109/ECTC.2012.6249130","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249130","url":null,"abstract":"A compact frequency equalizer based on distributed passive circuits is designed, analyzed and implemented for the front end circuit of a portable spectrum analyzer working between 100MHz to 7 GHz. The equalizer is based on a T-shape passive attenuator consisting of multiple distributed inductive and capacitive elements. As a test vehicle, a 3-stage broadband amplifier has been implemented, connected to the designed equalizer, and characterized in the targeted frequency range. Without the equalizer, the measured gain of the implemented amplifier varies from 34.7 dB to 46.97 dB showing a 12.27 dB roll off in the frequency range. After connecting the equalizer, overall gain variation is reduced to ± 1.1dB. Compared with other preexisting frequency equalizers, the implemented one features a small footprint of 6×8 mm2 and a wide frequency bandwidth of 100MHz to 7GHz. Detail description on the equivalent circuit model and general design guidelines are given, and parametric analysis is performed. The implemented equalizer is suitable for the front end circuits of compact broadband test and measurement instruments, such as a portable spectrum analyzer and vector network analyzer.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"37 1","pages":"2091-2097"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87292004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248883
C. Zhan, P. Tzeng, J. Lau, M. Dai, H. Chien, Ching-Kuan Lee, Shang-Tsai Wu, K. Kao, Shin-Yi Huang, Chia-Wen Fan, Su-Ching Chung, Yu-wei Huang, Yu-Min Lin, Jing-Yao Chang, Tsung-Fu Yang, Tai-Hung Chen, R. Lo, M. Kao
In this study, a 3D IC integration system-in-package (SiP) with TSV/RDL/IPD interposer is designed and developed. Emphasis is placed on the Cu revealing, embedded stress sensors, non-destructive inspection, thermal modeling and measurement, and final assembly and reliability assessments.
{"title":"Assembly process and reliability assessment of TSV/RDL/IPD interposer with multi-chip-stacking for 3D IC integration SiP","authors":"C. Zhan, P. Tzeng, J. Lau, M. Dai, H. Chien, Ching-Kuan Lee, Shang-Tsai Wu, K. Kao, Shin-Yi Huang, Chia-Wen Fan, Su-Ching Chung, Yu-wei Huang, Yu-Min Lin, Jing-Yao Chang, Tsung-Fu Yang, Tai-Hung Chen, R. Lo, M. Kao","doi":"10.1109/ECTC.2012.6248883","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248883","url":null,"abstract":"In this study, a 3D IC integration system-in-package (SiP) with TSV/RDL/IPD interposer is designed and developed. Emphasis is placed on the Cu revealing, embedded stress sensors, non-destructive inspection, thermal modeling and measurement, and final assembly and reliability assessments.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"13 1","pages":"548-554"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88670568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248862
Zhuo Li, Rongwei Zhang, Yan Liu, T. Le, C. Wong
We demonstrated a novel approach to synthesize flexible isotropic conductive adhesives (ICAs) that can not only withstand a high deformation rate but also exhibit superior electrical conductivity and adhesion strength. The ICA is made of polyurethane (PU) filled with silver flakes. It can achieve resistivity as low as 1.1×10-5 Ω.cm at 80 wt.% loadings, which is even better than most solders. The high electrical conductivity results from 1) large shrinkage of the PU matrix during cuing; 2) the in-situ reduction of the silver carboxylate layer present on the surface of silver flakes by the selected curing agent so that direct metallic contact can be formed between silver flakes; 3) the microphase separation that is unique to PU matrix providing more conduction paths. The combination of the three above effects leads to the superior electrical conductivity that can be rarely seen in other ICA materials at equivalent loading level. In terms of adhesion, lap shear test measurements show that the adhesion strength to Cu surfaces at room temperature can reach 0.12 kg/mm2 at 80 wt% loading, equivalent to some epoxy based ICAs reported before. In addition, the developed ICAs have also demonstrated other advantages such as a low curing temperature, which enable them to be printed on low cost and flexible substrates such as paper and fabrics; simple and cost-effective processing, eliminating the usage of Ag nanoparticles to achieve high electrical conductivity; and good bio-compatibility. These superior material properties combined with low cost and simple processing make it very promising for emerging flexible electronics. A wearable antenna fabricated by printing the PU based ICAs on flexible fabrics was also presented as a demonstration of such devices.
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