Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249020
Wei Lin, S. Wen, A. Yoshida, Jeong-Cheol Shin
Thin substrates have been used in more and more package-on-package (PoP) designs to meet the overall package thickness requirement. Low CTE cores are becoming more popular to reduce thin package warpage. On the other hand, substrates used in the same product are often sourced from multiple suppliers. Packages built with thin substrates sourced from different suppliers were found to have different end-of-line (EOL) package warpage. In this paper, 5 legs of substrates from 3 different suppliers were studied and compared with regard to raw substrate warpage, raw substrate modulus and CTE properties, and their reactions to 1× reflow thermal conditioning in order to understand any correlation to end-of-line package warpage. It was found that raw substrates sourced from different suppliers, or different processes in the same supplier, could have different levels of initial bare substrate warpage due to residual stress. Simulation results showed clear correlation between bare substrate warpage and EOL package warpage. However, such correlation was not observed with the limited measurement data collected. It was also found that properties (CTE and modulus) of finished composite substrates from different suppliers and processes could vary significantly, especially in the high temperature range. The difference in properties could be correlated to the difference at end-of-line package warpage in some cases. Further more, the substrates from different suppliers or processes could change their warpage, modulus and CTE properties in different ways after 1× reflow temperature conditioning. The study shows that it becomes more and more important to have better quality control of substrates sourced from different suppliers as substrate becomes thin and low CTE core is used.
{"title":"Evaluation of raw substrate variation from different suppliers and processes and their impact on package warpage","authors":"Wei Lin, S. Wen, A. Yoshida, Jeong-Cheol Shin","doi":"10.1109/ECTC.2012.6249020","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249020","url":null,"abstract":"Thin substrates have been used in more and more package-on-package (PoP) designs to meet the overall package thickness requirement. Low CTE cores are becoming more popular to reduce thin package warpage. On the other hand, substrates used in the same product are often sourced from multiple suppliers. Packages built with thin substrates sourced from different suppliers were found to have different end-of-line (EOL) package warpage. In this paper, 5 legs of substrates from 3 different suppliers were studied and compared with regard to raw substrate warpage, raw substrate modulus and CTE properties, and their reactions to 1× reflow thermal conditioning in order to understand any correlation to end-of-line package warpage. It was found that raw substrates sourced from different suppliers, or different processes in the same supplier, could have different levels of initial bare substrate warpage due to residual stress. Simulation results showed clear correlation between bare substrate warpage and EOL package warpage. However, such correlation was not observed with the limited measurement data collected. It was also found that properties (CTE and modulus) of finished composite substrates from different suppliers and processes could vary significantly, especially in the high temperature range. The difference in properties could be correlated to the difference at end-of-line package warpage in some cases. Further more, the substrates from different suppliers or processes could change their warpage, modulus and CTE properties in different ways after 1× reflow temperature conditioning. The study shows that it becomes more and more important to have better quality control of substrates sourced from different suppliers as substrate becomes thin and low CTE core is used.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78251613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249109
V. Mokkapati, O. Bethge, R. Hainberger, H. Brueckl
Conventional fabrication of microfluidic chips is based on silicon, glass, PDMS and various other polymeric materials (COC, polycarbonate, PMMA etc). Silicon and glass processing technologies are highly developed and the chips can be fabricated with ease. Polymeric microfluidic chips have become very common in recent years due to the demand for the cheap and disposable devices. New entrants in to the field are UV curable adhesives which are gaining recognition as promising players in microfluidics. UV curable adhesives are generally used in various applications ranging from usage in the manufacture of parts of an aircraft to sealing/packaging of microfluidic chips. Unlike any other previously discussed materials UV curable adhesives have the flexibility in alignment and bonding during fabrication process. These adhesives can be applied in between two surfaces which are to be glued and can be left like that for hours to days without bonding them as long as the glue is not exposed to UV light. In this paper we explain the detailed fabrication of microfluidic chips (100μm wide and 3μm (NOA74), 22μm (NOA 68) deep) completely made from UV curable adhesives having better chemical resistance, permeability and flexible surface treatments compared to other known polymeric materials. Firstly the patterns were etched on silicon, followed by PDMS molding and subsequently UV curable adhesives were casted and cured on structured PDMS master. After unmolding the stamps were mounted on a glass substrate and permanent bonding was achieved by further UV treatment and/or oxygen plasma treatment. The final devices were successfully tested for any leakage. These microfluidic chips will be integrated with a sensor and antenna for further biological studies. UV curable adhesives are also used for permanent/temporary sealing of microfluidic channels. These adhesives, which are still new to the fluidics branch can functionally and economically, have a greater impact on microfluidics.
{"title":"Microfluidic chips fabrication from UV curable adhesives for heterogeneous integration","authors":"V. Mokkapati, O. Bethge, R. Hainberger, H. Brueckl","doi":"10.1109/ECTC.2012.6249109","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249109","url":null,"abstract":"Conventional fabrication of microfluidic chips is based on silicon, glass, PDMS and various other polymeric materials (COC, polycarbonate, PMMA etc). Silicon and glass processing technologies are highly developed and the chips can be fabricated with ease. Polymeric microfluidic chips have become very common in recent years due to the demand for the cheap and disposable devices. New entrants in to the field are UV curable adhesives which are gaining recognition as promising players in microfluidics. UV curable adhesives are generally used in various applications ranging from usage in the manufacture of parts of an aircraft to sealing/packaging of microfluidic chips. Unlike any other previously discussed materials UV curable adhesives have the flexibility in alignment and bonding during fabrication process. These adhesives can be applied in between two surfaces which are to be glued and can be left like that for hours to days without bonding them as long as the glue is not exposed to UV light. In this paper we explain the detailed fabrication of microfluidic chips (100μm wide and 3μm (NOA74), 22μm (NOA 68) deep) completely made from UV curable adhesives having better chemical resistance, permeability and flexible surface treatments compared to other known polymeric materials. Firstly the patterns were etched on silicon, followed by PDMS molding and subsequently UV curable adhesives were casted and cured on structured PDMS master. After unmolding the stamps were mounted on a glass substrate and permanent bonding was achieved by further UV treatment and/or oxygen plasma treatment. The final devices were successfully tested for any leakage. These microfluidic chips will be integrated with a sensor and antenna for further biological studies. UV curable adhesives are also used for permanent/temporary sealing of microfluidic channels. These adhesives, which are still new to the fluidics branch can functionally and economically, have a greater impact on microfluidics.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76223806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248967
R. Dunne, Yoshimi Takahashi, Kazuaki Mawatari, Masamitsu Matsuura, Tom Bonifield, Philipp Steinmann, D. Stepniak
To enable the miniaturization, electrical performance and heterogeneous functionality needs for emerging Analog applications, a stacked Wafer-level Chip Scale Package (WCSP) package platform has been developed using Through-Silicon Via (TSV) technology. This allows stacking of ICs, MEMS, passives and other components in the vertical direction onto active or passive TSV wafers, to create innovative System-in-Package (SiP) product solutions. Since Analog devices are small in size and cost is a key care about, a careful selection of the integration flow is required to achieve a low cost packaging solution. In this work, an integration flow for the stacked WCSP package is presented, along with development details for the Chip-on-Wafer (CoW) bonding and wafer overmolding unit processes. The test vehicle was 3mm × 3mm in size and used 25u diameter Cu TSVs in a 200mm diameter wafer. Interconnect reliability evaluations were done with different micro-bump Under Bump Metallurgy (UBM) and TSV tip surface finish metallization combinations. Wafer ovemolding development included warpage, saw and adhesion evaluations with multiple mold materials. A back-end assembly flow was established with a mass reflow bonding process and an overmold material with low CTE and intermediate Tg and modulus. Samples were prepared with mold-on-die and exposed die package structures. Excellent time-zero yields were obtained, with an average TSV micro-bump interconnect resistance of 25 mohms. Results and failures modes from preliminary reliability testing are included.
{"title":"Development of a stacked WCSP package platform using TSV (Through Silicon Via) technology","authors":"R. Dunne, Yoshimi Takahashi, Kazuaki Mawatari, Masamitsu Matsuura, Tom Bonifield, Philipp Steinmann, D. Stepniak","doi":"10.1109/ECTC.2012.6248967","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248967","url":null,"abstract":"To enable the miniaturization, electrical performance and heterogeneous functionality needs for emerging Analog applications, a stacked Wafer-level Chip Scale Package (WCSP) package platform has been developed using Through-Silicon Via (TSV) technology. This allows stacking of ICs, MEMS, passives and other components in the vertical direction onto active or passive TSV wafers, to create innovative System-in-Package (SiP) product solutions. Since Analog devices are small in size and cost is a key care about, a careful selection of the integration flow is required to achieve a low cost packaging solution. In this work, an integration flow for the stacked WCSP package is presented, along with development details for the Chip-on-Wafer (CoW) bonding and wafer overmolding unit processes. The test vehicle was 3mm × 3mm in size and used 25u diameter Cu TSVs in a 200mm diameter wafer. Interconnect reliability evaluations were done with different micro-bump Under Bump Metallurgy (UBM) and TSV tip surface finish metallization combinations. Wafer ovemolding development included warpage, saw and adhesion evaluations with multiple mold materials. A back-end assembly flow was established with a mass reflow bonding process and an overmold material with low CTE and intermediate Tg and modulus. Samples were prepared with mold-on-die and exposed die package structures. Excellent time-zero yields were obtained, with an average TSV micro-bump interconnect resistance of 25 mohms. Results and failures modes from preliminary reliability testing are included.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78231569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248937
L. Yip
With the industry movement towards lead-free solders and advanced silicon process nodes with ultra low-k dielectrics, flip chip packaging is faced with significant assembly and reliability challenges. Since lead-free solder bumps are brittle, they can easily crack without adequate support from the underfill material during thermal stress. Lead-free solder bumps have less solder fatigue resistance compared to tin-lead eutectic or high-lead bumps and require higher Tg underfills for protection. However, the higher Tg underfill and the higher reflow temperature needed for lead-free bump assembly will increase die stress and package warpage. Since lower k dielectric materials have lower mechanical strength and lower adhesion than the dielectric materials used for prior silicon generations, the high stress induced by the lead-free assembly process and material set can cause delamination within the die, especially in devices with large die and large package sizes. In order to develop and qualify a reliable and robust lead-free package, care must be taken in the materials selection and optimization of the package structure. This paper discusses the effect of different factors such as underfill, substrate core, substrate pad structure, and lid design on package reliability of lead-free fine-pitch flip chip devices. It also reviews the assembly process related factors that impact the reliability of the lead-free bump and ultra low-k devices. Our studies show that a highly reliable lead-free package on organic substrate can be achieved for devices with large die and large package sizes. The reliability results for large die with different silicon nodes from 90 nm to 28 nm are presented.
{"title":"Reliability of large die ultra low-k lead-free flip chip packages","authors":"L. Yip","doi":"10.1109/ECTC.2012.6248937","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248937","url":null,"abstract":"With the industry movement towards lead-free solders and advanced silicon process nodes with ultra low-k dielectrics, flip chip packaging is faced with significant assembly and reliability challenges. Since lead-free solder bumps are brittle, they can easily crack without adequate support from the underfill material during thermal stress. Lead-free solder bumps have less solder fatigue resistance compared to tin-lead eutectic or high-lead bumps and require higher Tg underfills for protection. However, the higher Tg underfill and the higher reflow temperature needed for lead-free bump assembly will increase die stress and package warpage. Since lower k dielectric materials have lower mechanical strength and lower adhesion than the dielectric materials used for prior silicon generations, the high stress induced by the lead-free assembly process and material set can cause delamination within the die, especially in devices with large die and large package sizes. In order to develop and qualify a reliable and robust lead-free package, care must be taken in the materials selection and optimization of the package structure. This paper discusses the effect of different factors such as underfill, substrate core, substrate pad structure, and lid design on package reliability of lead-free fine-pitch flip chip devices. It also reviews the assembly process related factors that impact the reliability of the lead-free bump and ultra low-k devices. Our studies show that a highly reliable lead-free package on organic substrate can be achieved for devices with large die and large package sizes. The reliability results for large die with different silicon nodes from 90 nm to 28 nm are presented.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77028356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248943
P. Raj, K. Murali, S. Gandhi, R. Tummala, K. Slenes, N. Berg
This paper reports novel material and process technologies for near-zero Temperature-Coefficient Resistors (TCR) and zero temperature coefficient of capacitance (TCC) capacitors and their integration into organic or silicon packages for precision RF components. A new concept of self-compensating resistors, leading to zero TCR was explored and demonstrated for the first time, using heterogeneous resistor stack structures consisting of metal layers with positive TCR and semiconducting oxide layers with negative TCR. Zero TCC capacitors were demonstrated with a film-stack consisting of ceramic nanocomposites of positive TCC and negative TCC. In both cases, the film thickness was designed such that there is internal compensation in temperature deviation, which results in zero temperature-coefficient. Material models were developed for the film-stack to design the films for zero temperature-coefficient.
{"title":"Integration of precision resistors and capacitors with near-zero temperature coefficients in silicon and organic packages","authors":"P. Raj, K. Murali, S. Gandhi, R. Tummala, K. Slenes, N. Berg","doi":"10.1109/ECTC.2012.6248943","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248943","url":null,"abstract":"This paper reports novel material and process technologies for near-zero Temperature-Coefficient Resistors (TCR) and zero temperature coefficient of capacitance (TCC) capacitors and their integration into organic or silicon packages for precision RF components. A new concept of self-compensating resistors, leading to zero TCR was explored and demonstrated for the first time, using heterogeneous resistor stack structures consisting of metal layers with positive TCR and semiconducting oxide layers with negative TCR. Zero TCC capacitors were demonstrated with a film-stack consisting of ceramic nanocomposites of positive TCC and negative TCC. In both cases, the film thickness was designed such that there is internal compensation in temperature deviation, which results in zero temperature-coefficient. Material models were developed for the film-stack to design the films for zero temperature-coefficient.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77762629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249047
S. Babikian, Liang L. Wu, G. Li, M. Bachman
We report the development of a packaged thermal component with integrated sensor for use in integrated microfluidic systems that need to accurately and conveniently control fluid temperature in one or more microfluidic reservoirs. The small surface mounted component can be assembled on a circuit board and encapsulated in biocompatible polymer for use as part of a “lab-on-a-chip” system. Such systems can be readily utilized in miniaturized lab applications that require precision heating, such as cell lysing, polymerase chain reaction (PCR) and sterilization.
{"title":"Microfluidic thermal component for integrated microfluidic systems","authors":"S. Babikian, Liang L. Wu, G. Li, M. Bachman","doi":"10.1109/ECTC.2012.6249047","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249047","url":null,"abstract":"We report the development of a packaged thermal component with integrated sensor for use in integrated microfluidic systems that need to accurately and conveniently control fluid temperature in one or more microfluidic reservoirs. The small surface mounted component can be assembled on a circuit board and encapsulated in biocompatible polymer for use as part of a “lab-on-a-chip” system. Such systems can be readily utilized in miniaturized lab applications that require precision heating, such as cell lysing, polymerase chain reaction (PCR) and sterilization.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76654826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248933
S. Sheu, Z. H. Lin, C. S. Lin, J. Lau, S. H. Lee, K. Su, T. Ku, S. H. Wu, J. Hung, P. S. Chen, S. Lai, W. Lo, M. Kao
In this study, an on chip bus driver TEG (test element group) has been developed for the data transmission performance at TSVs for 3D IC integration. The on chip bus driver TEG consists of transceiver (TX), receiver (RX) and TSV group which has 2, 4 and 8 TSVs for the analysis of the TSV transmission performance with different load effects which are caused by different number (2, 4, and 8) of chip stack (each chip is with one TSV). This chip has been made by TSMC's 0.18μm process (FEOL) and ITRI's BEOL process. The square chip area is 1.69mm2 and power supply voltage is 1.8V with 30μm diameter TSVs on 30μm pitch and 100μm depth. Finally, a design guide line and a test tool will be proposed with the present on chip bus TEG.
{"title":"Electrical characterization of through silicon vias (TSVs) with an on chip bus driver for 3D IC integration","authors":"S. Sheu, Z. H. Lin, C. S. Lin, J. Lau, S. H. Lee, K. Su, T. Ku, S. H. Wu, J. Hung, P. S. Chen, S. Lai, W. Lo, M. Kao","doi":"10.1109/ECTC.2012.6248933","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248933","url":null,"abstract":"In this study, an on chip bus driver TEG (test element group) has been developed for the data transmission performance at TSVs for 3D IC integration. The on chip bus driver TEG consists of transceiver (TX), receiver (RX) and TSV group which has 2, 4 and 8 TSVs for the analysis of the TSV transmission performance with different load effects which are caused by different number (2, 4, and 8) of chip stack (each chip is with one TSV). This chip has been made by TSMC's 0.18μm process (FEOL) and ITRI's BEOL process. The square chip area is 1.69mm2 and power supply voltage is 1.8V with 30μm diameter TSVs on 30μm pitch and 100μm depth. Finally, a design guide line and a test tool will be proposed with the present on chip bus TEG.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73342849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248945
T. Watanabe, S. Yamamichi
We have developed a U-shaped magnetic shield for packaging perpendicular magnetoresistive random access memories (MRAMs) and have determined that a non-oriented silicon steel is best suited for this shield in terms of fabrication and magnetic properties. Use of this shield material suppressed magnetic flux saturation for an external magnetic field of up to 300[Oe], which exceeds the target of 250[Oe]. A magnetic source can thus be placed as close as 1 cm to a shielded MRAM. An MRAM chip is packaged by separating the shield into two parts and then mounting the lower part, the chip, and the upper part in sequence. If the gap between the parts is 20[μm] and the permeability of the gap is 30, the target performance is still achieved. This shield is thus promising for high-speed, low-power MRAMs.
{"title":"A novel U-shaped magnetic shield for perpendicular MRAM","authors":"T. Watanabe, S. Yamamichi","doi":"10.1109/ECTC.2012.6248945","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248945","url":null,"abstract":"We have developed a U-shaped magnetic shield for packaging perpendicular magnetoresistive random access memories (MRAMs) and have determined that a non-oriented silicon steel is best suited for this shield in terms of fabrication and magnetic properties. Use of this shield material suppressed magnetic flux saturation for an external magnetic field of up to 300[Oe], which exceeds the target of 250[Oe]. A magnetic source can thus be placed as close as 1 cm to a shielded MRAM. An MRAM chip is packaged by separating the shield into two parts and then mounting the lower part, the chip, and the upper part in sequence. If the gap between the parts is 20[μm] and the permeability of the gap is 30, the target performance is still achieved. This shield is thus promising for high-speed, low-power MRAMs.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73883245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248837
M. Nimura, A. Shigetou, K. Sakuma, H. Ogino, T. Enomoto, J. Mizuno, S. Shoji
We developed a novel hybrid bonding technology for Au ultralow-profiled bumps and underfill resin with a modified “lock-and-key structure.” The lock structure interlocks with the key structure. We applied these structures to perform an entire adhesion between the mating surfaces in place of conventional underfilling technique. To fabricate the key structure, we developed a simple process that can remove resin on the bumps. Lock structure was fabricated by photolithography and dry etching. After the bonding was carried out, the bonded interface was observed with a Scanning Electron Microscope (SEM), a transmission electron microscope (TEM) and a Scanning Acoustic Microscope (SAM). The results proved that no significant gap was existed at both Au-Au and resin-resin interface. Furthermore, the shear strength of the bonded sample with resin was ten times stronger than that without resin. The conduction of Au bump connections after hybrid bonding was also confirmed.
{"title":"Hybrid Au-underfill resin bonding with lock-and-key structure","authors":"M. Nimura, A. Shigetou, K. Sakuma, H. Ogino, T. Enomoto, J. Mizuno, S. Shoji","doi":"10.1109/ECTC.2012.6248837","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248837","url":null,"abstract":"We developed a novel hybrid bonding technology for Au ultralow-profiled bumps and underfill resin with a modified “lock-and-key structure.” The lock structure interlocks with the key structure. We applied these structures to perform an entire adhesion between the mating surfaces in place of conventional underfilling technique. To fabricate the key structure, we developed a simple process that can remove resin on the bumps. Lock structure was fabricated by photolithography and dry etching. After the bonding was carried out, the bonded interface was observed with a Scanning Electron Microscope (SEM), a transmission electron microscope (TEM) and a Scanning Acoustic Microscope (SAM). The results proved that no significant gap was existed at both Au-Au and resin-resin interface. Furthermore, the shear strength of the bonded sample with resin was ten times stronger than that without resin. The conduction of Au bump connections after hybrid bonding was also confirmed.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74849052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249036
S. Ura, T. Majima, K. Kintaka, K. Hatanaka, J. Inoue, K. Nishio, Y. Awatsuji
A cavity-resonator-integrated guided-mode-resonance filter (CRIGF) consisting of a grating coupler (GC) and a pair of distributed-Bragg-reflectors (DBRs) on a thin film waveguide has been recently proposed and investigated to provide a narrow-band reflection spectrum for an incident wave of a small beam width from the free space. A CRIGF demonstrated so far shows polarization dependence because propagation constants of guided waves excited by GC are different between TE and TM incident waves. In order to construct a polarization-independent guided-mode resonance filter with small aperture, an integration of two CRIGFs crossed each other was proposed and discussed in this paper. A device was designed for a resonance wavelength of 1550 nm and its reflection and transmission spectra were predicted by a newly developed analysis based on the coupled-mode theory. A reflectance of 96 % with 1 nm bandwidth was expected for an incident beam diameter of 10 μm. A test sample working at 846 nm was fabricated and characterized. A Ge:SiO2 guiding core layer was deposited on a SiO2 glass substrate, and GC and DBRs were formed by the electron-beam direct writing lithography. Measured reflection spectra for TE and TM incident beams were well coincident with each other.
{"title":"Small-aperture guided-mode-resonance filter with cavity resonators","authors":"S. Ura, T. Majima, K. Kintaka, K. Hatanaka, J. Inoue, K. Nishio, Y. Awatsuji","doi":"10.1109/ECTC.2012.6249036","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249036","url":null,"abstract":"A cavity-resonator-integrated guided-mode-resonance filter (CRIGF) consisting of a grating coupler (GC) and a pair of distributed-Bragg-reflectors (DBRs) on a thin film waveguide has been recently proposed and investigated to provide a narrow-band reflection spectrum for an incident wave of a small beam width from the free space. A CRIGF demonstrated so far shows polarization dependence because propagation constants of guided waves excited by GC are different between TE and TM incident waves. In order to construct a polarization-independent guided-mode resonance filter with small aperture, an integration of two CRIGFs crossed each other was proposed and discussed in this paper. A device was designed for a resonance wavelength of 1550 nm and its reflection and transmission spectra were predicted by a newly developed analysis based on the coupled-mode theory. A reflectance of 96 % with 1 nm bandwidth was expected for an incident beam diameter of 10 μm. A test sample working at 846 nm was fabricated and characterized. A Ge:SiO2 guiding core layer was deposited on a SiO2 glass substrate, and GC and DBRs were formed by the electron-beam direct writing lithography. Measured reflection spectra for TE and TM incident beams were well coincident with each other.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80143117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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