Pub Date : 2012-11-12DOI: 10.1109/ECCE.2012.6342762
X. Gong, J. Ferreira
This paper presents the suppression of conducted common mode (CM) Electromagnetic Interference (EMI) in an inverter for motor drive with discrete Silicon Carbide (SiC) JFETs attached on top of the Insulated Metal Substrate (IMS). The EMC performance of the IMS inverter is compared with a heat sink inverter in a similar circuit layout. Both are under the same influence of parasitic couplings between the SiC JFET drains and substrate base plate. It is found that although the application of conventional CM filters effectively suppresses the emitted noise in the low frequency (LF) range, the capacitive coupling influence results in slight or no improvement in the middle frequency (MF) and high frequency (HF) range. To deal with this problem, a system CM equivalent circuit model with extracted parasitic parameters is proposed. The model is able to evaluate the filter insertion losses over a broad conducted EMI frequency band, which is essential to achieve an optimized filter design balanced between performance and cost. The presented experimental and calculated results form the step-by-step guideline that effectively suppresses the generated EMI to comply with the standard prescribed by IEC61800-3 C2: Qp.
{"title":"Modeling and reduction of conducted EMI in SiC JFET motor drives with insulated metal substrate","authors":"X. Gong, J. Ferreira","doi":"10.1109/ECCE.2012.6342762","DOIUrl":"https://doi.org/10.1109/ECCE.2012.6342762","url":null,"abstract":"This paper presents the suppression of conducted common mode (CM) Electromagnetic Interference (EMI) in an inverter for motor drive with discrete Silicon Carbide (SiC) JFETs attached on top of the Insulated Metal Substrate (IMS). The EMC performance of the IMS inverter is compared with a heat sink inverter in a similar circuit layout. Both are under the same influence of parasitic couplings between the SiC JFET drains and substrate base plate. It is found that although the application of conventional CM filters effectively suppresses the emitted noise in the low frequency (LF) range, the capacitive coupling influence results in slight or no improvement in the middle frequency (MF) and high frequency (HF) range. To deal with this problem, a system CM equivalent circuit model with extracted parasitic parameters is proposed. The model is able to evaluate the filter insertion losses over a broad conducted EMI frequency band, which is essential to achieve an optimized filter design balanced between performance and cost. The presented experimental and calculated results form the step-by-step guideline that effectively suppresses the generated EMI to comply with the standard prescribed by IEC61800-3 C2: Qp.","PeriodicalId":6401,"journal":{"name":"2012 IEEE Energy Conversion Congress and Exposition (ECCE)","volume":"46 1 1","pages":"629-636"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72945603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/ECCE.2012.6342393
J. Xu, Lin Sheng, Xianhui Dong
This paper presents a new high speed Power FET driver with 5A sourcing and sinking current capability and 20V rail-to-rail output range. Due to the 7V gate oxide breakdown limitation of process, a floating ground inside the driver is created to drive the pull-up N-type LDMOS. With this floating ground, the pull-up N-type LDMOS can be driven separately from the pull-down N-type LDMOS and the driver is free of shoot-through current. In order to minimize the rise time during switching, a charge pump circuit is implemented to bring the gate voltage of pull-up N-type LDMOS above the supply rail. As a result, the driver's pull-up capability above power FET's miller plateau is improved largely and the rising time is reduced about 65% when VDD is 5V compared to the conventional driver. A 5A dual channel driver with the proposed novel scheme is designed, the die size is only 1mm×1mm and it has the leading edge performance over all the commercial products. The scheme, simulation and silicon test results are included in this paper.
{"title":"A novel high speed and high current FET driver with floating ground and integrated charge pump","authors":"J. Xu, Lin Sheng, Xianhui Dong","doi":"10.1109/ECCE.2012.6342393","DOIUrl":"https://doi.org/10.1109/ECCE.2012.6342393","url":null,"abstract":"This paper presents a new high speed Power FET driver with 5A sourcing and sinking current capability and 20V rail-to-rail output range. Due to the 7V gate oxide breakdown limitation of process, a floating ground inside the driver is created to drive the pull-up N-type LDMOS. With this floating ground, the pull-up N-type LDMOS can be driven separately from the pull-down N-type LDMOS and the driver is free of shoot-through current. In order to minimize the rise time during switching, a charge pump circuit is implemented to bring the gate voltage of pull-up N-type LDMOS above the supply rail. As a result, the driver's pull-up capability above power FET's miller plateau is improved largely and the rising time is reduced about 65% when VDD is 5V compared to the conventional driver. A 5A dual channel driver with the proposed novel scheme is designed, the die size is only 1mm×1mm and it has the leading edge performance over all the commercial products. The scheme, simulation and silicon test results are included in this paper.","PeriodicalId":6401,"journal":{"name":"2012 IEEE Energy Conversion Congress and Exposition (ECCE)","volume":"30 1","pages":"2604-2609"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72970824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/ECCE.2012.6342517
D. Patel, M. Chandorkar
This paper presents a dynamic phasor modeling approach to the small signal transient analysis of induction machines with stator inter-turn faults. An important advantage of dynamic phasor modeling is that it results in time-invariant models of unbalanced three-phase systems. The linearized dynamic phasor model facilitates the analytical studies of transients of unbalanced systems using eigenvalues. The linearized q - d model of a machine with stator inter-turn fault has a system matrix having time periodic entries, and is thus unsuitable for eigenvalue analysis. The dynamic phasor model helps in this case. In this paper, the dynamic phasor model of induction machine with stator inter-turn fault is developed, and this is further used for eigenvalue analysis. The eigenvalue comparison of healthy and faulted machines is presented. This analysis is verified by transient simulations of the dynamic phasor model and experiments. The eigenvalue analysis and the results of experiments and simulations show that the effect of stator inter-turn fault in transients of positive and negative sequence currents is very small. Also the stator inter-turn fault produces coupling between transients of positive and negative sequence currents.
{"title":"Small-signal transient analysis of induction machines with stator inter-turn faults using dynamic phasors","authors":"D. Patel, M. Chandorkar","doi":"10.1109/ECCE.2012.6342517","DOIUrl":"https://doi.org/10.1109/ECCE.2012.6342517","url":null,"abstract":"This paper presents a dynamic phasor modeling approach to the small signal transient analysis of induction machines with stator inter-turn faults. An important advantage of dynamic phasor modeling is that it results in time-invariant models of unbalanced three-phase systems. The linearized dynamic phasor model facilitates the analytical studies of transients of unbalanced systems using eigenvalues. The linearized q - d model of a machine with stator inter-turn fault has a system matrix having time periodic entries, and is thus unsuitable for eigenvalue analysis. The dynamic phasor model helps in this case. In this paper, the dynamic phasor model of induction machine with stator inter-turn fault is developed, and this is further used for eigenvalue analysis. The eigenvalue comparison of healthy and faulted machines is presented. This analysis is verified by transient simulations of the dynamic phasor model and experiments. The eigenvalue analysis and the results of experiments and simulations show that the effect of stator inter-turn fault in transients of positive and negative sequence currents is very small. Also the stator inter-turn fault produces coupling between transients of positive and negative sequence currents.","PeriodicalId":6401,"journal":{"name":"2012 IEEE Energy Conversion Congress and Exposition (ECCE)","volume":"10 1","pages":"3008-3015"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74362446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/ECCE.2012.6342772
R. Meyer, A. Mertens
In this paper an efficient design process of LCL filters for grid-connected converters is described. It is especially developed to design filters for converters with low switching frequency generating harmonics in the entire frequency range. In these special applications, some small parameter variations can cause the given limits, like the allowed voltage harmonics, to be exceeded. In the worst case, the resonance frequency of the filter can be excited to an unacceptable extent. To avoid this, the tolerances of the filter parameters, the grid voltage and the grid frequency are taken into account when designing the filter. This essential consideration of the parameter variations distinguishes this new method from the well-known design processes. As an example, a filter design for a 5 MW wind energy generator with full-scale three-level medium-voltage converter is regarded more detailed. Measurements on a scaled low-voltage laboratory setup validate the theoretical calculations and complete the examination. The discussed design process enables a filter design meeting all grid code requirements concerning the voltage quality for all relevant operating ranges in consideration of various parameter variations. The method is suitable for all converter topologies and modulation schemes generating periodical output voltages.
{"title":"Design of LCL filters in consideration of parameter variations for grid-connected converters","authors":"R. Meyer, A. Mertens","doi":"10.1109/ECCE.2012.6342772","DOIUrl":"https://doi.org/10.1109/ECCE.2012.6342772","url":null,"abstract":"In this paper an efficient design process of LCL filters for grid-connected converters is described. It is especially developed to design filters for converters with low switching frequency generating harmonics in the entire frequency range. In these special applications, some small parameter variations can cause the given limits, like the allowed voltage harmonics, to be exceeded. In the worst case, the resonance frequency of the filter can be excited to an unacceptable extent. To avoid this, the tolerances of the filter parameters, the grid voltage and the grid frequency are taken into account when designing the filter. This essential consideration of the parameter variations distinguishes this new method from the well-known design processes. As an example, a filter design for a 5 MW wind energy generator with full-scale three-level medium-voltage converter is regarded more detailed. Measurements on a scaled low-voltage laboratory setup validate the theoretical calculations and complete the examination. The discussed design process enables a filter design meeting all grid code requirements concerning the voltage quality for all relevant operating ranges in consideration of various parameter variations. The method is suitable for all converter topologies and modulation schemes generating periodical output voltages.","PeriodicalId":6401,"journal":{"name":"2012 IEEE Energy Conversion Congress and Exposition (ECCE)","volume":"22 3","pages":"557-564"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72622093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/ECCE.2012.6342306
Y. Suh, Yonggyun Park, Yuran Go
This paper investigates control algorithms for a doubly fed induction generator with a back-to-back three-level neutral-point clamped voltage source converter in medium voltage wind power system under unbalanced grid conditions. Three different control algorithms to compensate for unbalanced conditions have been investigated with respect to four performance factors; fault ride-through capability, instantaneous active power pulsation, harmonic distortions and torque pulsation. The control algorithm having zero amplitude of torque ripple shows the most cost-effective performance concerning torque pulsation. The least active power pulsation is produced by control algorithm that nullifies the oscillating component of the instantaneous stator active and reactive power. Combination of these two control algorithms depending on the operating requirements and depth of grid unbalance presents most optimized performance factors under the generalized unbalanced operating conditions leading to high performance DFIG wind turbine system.
{"title":"Control algorithm for a doubly fed induction generator in medium voltage wind power system under fault ride through and unbalanced grid conditions","authors":"Y. Suh, Yonggyun Park, Yuran Go","doi":"10.1109/ECCE.2012.6342306","DOIUrl":"https://doi.org/10.1109/ECCE.2012.6342306","url":null,"abstract":"This paper investigates control algorithms for a doubly fed induction generator with a back-to-back three-level neutral-point clamped voltage source converter in medium voltage wind power system under unbalanced grid conditions. Three different control algorithms to compensate for unbalanced conditions have been investigated with respect to four performance factors; fault ride-through capability, instantaneous active power pulsation, harmonic distortions and torque pulsation. The control algorithm having zero amplitude of torque ripple shows the most cost-effective performance concerning torque pulsation. The least active power pulsation is produced by control algorithm that nullifies the oscillating component of the instantaneous stator active and reactive power. Combination of these two control algorithms depending on the operating requirements and depth of grid unbalance presents most optimized performance factors under the generalized unbalanced operating conditions leading to high performance DFIG wind turbine system.","PeriodicalId":6401,"journal":{"name":"2012 IEEE Energy Conversion Congress and Exposition (ECCE)","volume":"33 1","pages":"2396-2403"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73396170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/ECCE.2012.6342797
Zhi Yang, Yichao Tang, Peng Zeng, A. Khaligh
This paper presents a flat linear generator with 11 poles and 12 winding slots for backpack energy harvesting. Analytical method based on magnetic vector potential and Finite Element Analysis (FEA) is carried out to investigate the electromagnetic characteristics. An electro-mechanical model based on the linear generator is built. It has been demonstrated that, under the walking frequency of 1.95 Hz, the backpacker carrying a 25 Kg pack can employ this 1.5 Kg generator to harvest 8 W power. Moreover, 40% of the peak accelerative force is eliminated for the backpacker. Analyses performed demonstrate that the generator is a potential candidate for backpack energy harvesting application.
{"title":"Reducing detent force while harvesting energy from center of gravity: an 11-poles, 12-slots Generator Design","authors":"Zhi Yang, Yichao Tang, Peng Zeng, A. Khaligh","doi":"10.1109/ECCE.2012.6342797","DOIUrl":"https://doi.org/10.1109/ECCE.2012.6342797","url":null,"abstract":"This paper presents a flat linear generator with 11 poles and 12 winding slots for backpack energy harvesting. Analytical method based on magnetic vector potential and Finite Element Analysis (FEA) is carried out to investigate the electromagnetic characteristics. An electro-mechanical model based on the linear generator is built. It has been demonstrated that, under the walking frequency of 1.95 Hz, the backpacker carrying a 25 Kg pack can employ this 1.5 Kg generator to harvest 8 W power. Moreover, 40% of the peak accelerative force is eliminated for the backpacker. Analyses performed demonstrate that the generator is a potential candidate for backpack energy harvesting application.","PeriodicalId":6401,"journal":{"name":"2012 IEEE Energy Conversion Congress and Exposition (ECCE)","volume":"42 1","pages":"380-387"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73888758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/ECCE.2012.6342614
Xuehua Wang, X. Ruan, Chenlei Bao, Donghua Pan, Lin Xu
The LCL filter is widely used in grid-connected inverter due to its powerful ability of attenuating the switching-frequency harmonics. However, the frequency response of the LCL filter has a resonance peak, which would amplify the harmonics around the resonant frequency or even cause the inverter to be unstable. Active damping based on the feedback of capacitor current is an effective solution to damp the resonance oscillation. Since the one-timestep delay of the digital signal processor (DSP) can hardly be avoided, the stable margin of the inverter will be weakened. Besides, the optional range of the capacitor-current feedback coefficient will be shrunk. This paper discusses the effect of the one-timestep delay firstly, and proposes a step-by-step design method to choose the parameters of the PI-based current regulator and the capacitor-current feedback coefficient. Based on Jury stability criterion, the selectable 3D region surrounded by the parameters of PI-based regulator and capacitor-current feedback coefficient can be plotted. Further, some specific constraints such as steady-state error and phase margin etc. will decide the suitable values of PI regulator and capacitor-current feedback coefficient. A 6-kW single-phase grid-connected inverter is built to verify the proposed design method.
{"title":"Design of the PI regulator and feedback coefficient of capacitor current for grid-connected inverter with an LCL filter in discrete-time domain","authors":"Xuehua Wang, X. Ruan, Chenlei Bao, Donghua Pan, Lin Xu","doi":"10.1109/ECCE.2012.6342614","DOIUrl":"https://doi.org/10.1109/ECCE.2012.6342614","url":null,"abstract":"The LCL filter is widely used in grid-connected inverter due to its powerful ability of attenuating the switching-frequency harmonics. However, the frequency response of the LCL filter has a resonance peak, which would amplify the harmonics around the resonant frequency or even cause the inverter to be unstable. Active damping based on the feedback of capacitor current is an effective solution to damp the resonance oscillation. Since the one-timestep delay of the digital signal processor (DSP) can hardly be avoided, the stable margin of the inverter will be weakened. Besides, the optional range of the capacitor-current feedback coefficient will be shrunk. This paper discusses the effect of the one-timestep delay firstly, and proposes a step-by-step design method to choose the parameters of the PI-based current regulator and the capacitor-current feedback coefficient. Based on Jury stability criterion, the selectable 3D region surrounded by the parameters of PI-based regulator and capacitor-current feedback coefficient can be plotted. Further, some specific constraints such as steady-state error and phase margin etc. will decide the suitable values of PI regulator and capacitor-current feedback coefficient. A 6-kW single-phase grid-connected inverter is built to verify the proposed design method.","PeriodicalId":6401,"journal":{"name":"2012 IEEE Energy Conversion Congress and Exposition (ECCE)","volume":"5 1","pages":"1657-1662"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73890938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/ECCE.2012.6342652
Ming Li, M. Shen, Lei Xing, W. Said
In this paper, a current feedback based hybrid common-mode EMI filter is presented for grid-tied inverter application, which employs passive filter with parallel damping branch. A current transformer is used to sense the target common-mode (CM) current, and the active circuit injects cancelation CM current via coupling capacitor. In particular, the proposed hybrid EMI filter with 2nd order high pass filter characteristic equivalently enhances the filter capacitance at high frequency range. Standalone and offline experimental results based on grid tied three-phase inverter system show that the proposed hybrid filter can improve the EMI attenuation by 10~20 dB beyond 150 kHz.
{"title":"Current feedback based hybrid common-mode EMI filter for grid-tied inverter application","authors":"Ming Li, M. Shen, Lei Xing, W. Said","doi":"10.1109/ECCE.2012.6342652","DOIUrl":"https://doi.org/10.1109/ECCE.2012.6342652","url":null,"abstract":"In this paper, a current feedback based hybrid common-mode EMI filter is presented for grid-tied inverter application, which employs passive filter with parallel damping branch. A current transformer is used to sense the target common-mode (CM) current, and the active circuit injects cancelation CM current via coupling capacitor. In particular, the proposed hybrid EMI filter with 2nd order high pass filter characteristic equivalently enhances the filter capacitance at high frequency range. Standalone and offline experimental results based on grid tied three-phase inverter system show that the proposed hybrid filter can improve the EMI attenuation by 10~20 dB beyond 150 kHz.","PeriodicalId":6401,"journal":{"name":"2012 IEEE Energy Conversion Congress and Exposition (ECCE)","volume":"45 1","pages":"1394-1398"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79306325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/ECCE.2012.6342311
S. Ryu, C. Capell, Lin Cheng, C. Jonas, A. Gupta, M. Donofrio, J. Clayton, M. O'loughlin, A. Burk, D. Grider, A. Agarwal, J. Palmour, A. Hefner, S. Bhattacharya
We present our latest developments in ultra high voltage 4H-SiC IGBTs. A 4H-SiC P-IGBT, with a chip size of 6.7 mm × 6.7 mm and an active area of 0.16 cm2 exhibited a record high blocking voltage of 15 kV, while showing a room temperature differential specific on-resistance of 24 mΩ-cm2 with a gate bias of -20 V. A 4H-SiC N-IGBT with the same area showed a blocking voltage of 12.5 kV, and demonstrated a room temperature differential specific on-resistance of 5.3 mΩ-cm2 with a gate bias of 20 V. Buffer layer design, which includes controlling the doping concentration and the thickness of the field-stop buffer layers, was used to control the charge injection from the backside. Effects on buffer layer design on static characteristics and switching behavior are reported.
{"title":"High performance, ultra high voltage 4H-SiC IGBTs","authors":"S. Ryu, C. Capell, Lin Cheng, C. Jonas, A. Gupta, M. Donofrio, J. Clayton, M. O'loughlin, A. Burk, D. Grider, A. Agarwal, J. Palmour, A. Hefner, S. Bhattacharya","doi":"10.1109/ECCE.2012.6342311","DOIUrl":"https://doi.org/10.1109/ECCE.2012.6342311","url":null,"abstract":"We present our latest developments in ultra high voltage 4H-SiC IGBTs. A 4H-SiC P-IGBT, with a chip size of 6.7 mm × 6.7 mm and an active area of 0.16 cm2 exhibited a record high blocking voltage of 15 kV, while showing a room temperature differential specific on-resistance of 24 mΩ-cm2 with a gate bias of -20 V. A 4H-SiC N-IGBT with the same area showed a blocking voltage of 12.5 kV, and demonstrated a room temperature differential specific on-resistance of 5.3 mΩ-cm2 with a gate bias of 20 V. Buffer layer design, which includes controlling the doping concentration and the thickness of the field-stop buffer layers, was used to control the charge injection from the backside. Effects on buffer layer design on static characteristics and switching behavior are reported.","PeriodicalId":6401,"journal":{"name":"2012 IEEE Energy Conversion Congress and Exposition (ECCE)","volume":"19 1","pages":"3603-3608"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84484799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/ECCE.2012.6342417
T. Modeer, S. Norrga, H. Nee
This paper firstly presents a discussion of the requirements for an auxiliary power supply for high-power modular multilevel converter submodules. Next, some of the most challenging problems in designing a low power high voltage step-down converter are presented. Further, a suitable topology, the tapped-inductor buck converter, that overcomes most of the problems is analyzed. Both analytical expressions describing the operation and circuit simulations are presented. Finally, an experimental evaluation of a 3 kV, 100W prototype converter utilizing an autonomous high-voltage switch is presented.
{"title":"High-voltage tapped-inductor buck converter auxiliary power supply for cascaded converter submodules","authors":"T. Modeer, S. Norrga, H. Nee","doi":"10.1109/ECCE.2012.6342417","DOIUrl":"https://doi.org/10.1109/ECCE.2012.6342417","url":null,"abstract":"This paper firstly presents a discussion of the requirements for an auxiliary power supply for high-power modular multilevel converter submodules. Next, some of the most challenging problems in designing a low power high voltage step-down converter are presented. Further, a suitable topology, the tapped-inductor buck converter, that overcomes most of the problems is analyzed. Both analytical expressions describing the operation and circuit simulations are presented. Finally, an experimental evaluation of a 3 kV, 100W prototype converter utilizing an autonomous high-voltage switch is presented.","PeriodicalId":6401,"journal":{"name":"2012 IEEE Energy Conversion Congress and Exposition (ECCE)","volume":"19 1","pages":"19-25"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84488556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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