Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433999
S. Ibrahim, B. Razavi
In order to reduce the pin count of chips and the complexity of the routing on printed-circuit boards and backplanes, it is desirable to replace a large number of parallel channels with a few serial links. Such a transformation can also potentially save significant power because it lowers the number of output drivers while maintaining the I/O voltage swings and termination impedances relatively constant. It is therefore plausible that data rates approaching 20 Gb/s will become common in the near future. At these speeds, the loss of FR4 boards poses a great challenge, requiring heavy equalization. From circuit design point of view, it is simpler to employ linear equalization (in the transmitter and the receiver), but from system design point of view, two serious issues make this approach unattractive: the amplification of crosstalk and the lack of ability to equalize for impedance discontinuities (sharp notches in the channel frequency response). In an optimum, yet practical system, one would place 4 to 5 dB of linear equalization in the transmitter and a similar amount in the receiver, and perform the remaining equalization by means of a decision-feedback equalizer (DFE), thus alleviating both issues.
{"title":"A 20Gb/s 40mW equalizer in 90nm CMOS technology","authors":"S. Ibrahim, B. Razavi","doi":"10.1109/ISSCC.2010.5433999","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433999","url":null,"abstract":"In order to reduce the pin count of chips and the complexity of the routing on printed-circuit boards and backplanes, it is desirable to replace a large number of parallel channels with a few serial links. Such a transformation can also potentially save significant power because it lowers the number of output drivers while maintaining the I/O voltage swings and termination impedances relatively constant. It is therefore plausible that data rates approaching 20 Gb/s will become common in the near future. At these speeds, the loss of FR4 boards poses a great challenge, requiring heavy equalization. From circuit design point of view, it is simpler to employ linear equalization (in the transmitter and the receiver), but from system design point of view, two serious issues make this approach unattractive: the amplification of crosstalk and the lack of ability to equalize for impedance discontinuities (sharp notches in the channel frequency response). In an optimum, yet practical system, one would place 4 to 5 dB of linear equalization in the transmitter and a similar amount in the receiver, and perform the remaining equalization by means of a decision-feedback equalizer (DFE), thus alleviating both issues.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"22 1","pages":"170-171"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85798328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433847
Jae-Hong Chang, Huijung Kim, Jeong-Hyun Choi, Hangun Chung, Jungwook Heo, Sanghoon Kang, Jong-Dae Bae, Heetae Oh, Youngwoon Kim, T. Kwon, Ryan Kim, Wooseung Choo, D. Rhee, Byeong-ha Park
The mobile TV applications such as DVH-H/T, T-DMB/DAB, ISDB-T are recently emerging all over the world. To support various applications, the multistandard and multiband mobile TV RF tuner is developed as a cost-effective and size-effective solution [1]. The demand for smaller form factor and power consumption reduction of RF and Channel is very high, and SoC technology is being adopted to meet the customer's requirements. As shown in Fig. 25.7.1, an SoC that implements all of the standards and frequency bands of a mobile TV in a 65nm CMOS is presented in this paper. This RF SoC consists of three RF front ends, a dual-mode analog baseband filter supporting lowpass filtering and complex bandpass filtering, a digitally controlled programmable-gain amplifier (PGA), wideband VCO/PLL, DCXO, data converters, demodulator, forward error correction (FEC), hardwired multiprotocl encapsulation forward error correction (MPE-FEC), ARM CPU and SRAM. This mobile TV RF SoC reduces board area and complexity while cutting system design time.
近年来，DVH-H/T、T- dmb /DAB、ISDB-T等移动电视应用在世界范围内不断涌现。为了支持各种应用，开发了多标准多频段移动电视射频调谐器，作为一种成本效益高且尺寸有效的解决方案[1]。RF和Channel对更小的外形尺寸和降低功耗的需求非常高，SoC技术正在被采用以满足客户的要求。如图25.7.1所示，本文提出了一个在65nm CMOS中实现移动电视所有标准和频段的SoC。该射频SoC由三个射频前端组成，一个支持低通滤波和复杂带通滤波的双模模拟基带滤波器，一个数字控制可编程增益放大器(PGA)，宽带VCO/PLL, DCXO，数据转换器，解调器，前向纠错(FEC)，硬接线多协议封装前向纠错(MPE-FEC)， ARM CPU和SRAM。这种移动电视射频SoC减少了电路板面积和复杂性，同时缩短了系统设计时间。
{"title":"A multistandard multiband mobile TV RF SoC in 65nm CMOS","authors":"Jae-Hong Chang, Huijung Kim, Jeong-Hyun Choi, Hangun Chung, Jungwook Heo, Sanghoon Kang, Jong-Dae Bae, Heetae Oh, Youngwoon Kim, T. Kwon, Ryan Kim, Wooseung Choo, D. Rhee, Byeong-ha Park","doi":"10.1109/ISSCC.2010.5433847","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433847","url":null,"abstract":"The mobile TV applications such as DVH-H/T, T-DMB/DAB, ISDB-T are recently emerging all over the world. To support various applications, the multistandard and multiband mobile TV RF tuner is developed as a cost-effective and size-effective solution [1]. The demand for smaller form factor and power consumption reduction of RF and Channel is very high, and SoC technology is being adopted to meet the customer's requirements. As shown in Fig. 25.7.1, an SoC that implements all of the standards and frequency bands of a mobile TV in a 65nm CMOS is presented in this paper. This RF SoC consists of three RF front ends, a dual-mode analog baseband filter supporting lowpass filtering and complex bandpass filtering, a digitally controlled programmable-gain amplifier (PGA), wideband VCO/PLL, DCXO, data converters, demodulator, forward error correction (FEC), hardwired multiprotocl encapsulation forward error correction (MPE-FEC), ARM CPU and SRAM. This mobile TV RF SoC reduces board area and complexity while cutting system design time.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"51 1","pages":"462-463"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72799930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433955
S. Drago, D. Leenaerts, F. Sebastiano, L. Breems, K. Makinwa, B. Nauta
This paper describes a 2.4GHz Wake-up Receiver (WuRx) designed to operate with low-accuracy (≪0.5%) frequency references [1], enabling crystal-less and thus low-cost wireless sensor nodes (WSNs). Robustness to frequency error is achieved by combining non-coherent energy detection with a broadband-IF superheterodyne architecture, and by using a pulse-position-modulated (PPM) impulse radio (IR) modulation scheme [2]. The Rx front-end and the LO generator are duty-cycled at pulse level, thereby reducing the power consumption to less than 420µW, which is more than adequate for use in WSNs [2]. PPM-IR also enables the realization of an interferer-robust receiver without the use of bulky off-chip RF filters [3,4]. This 65nm CMOS fully integrated WuRx employs a duty-cycled LO generator and achieves a sensitivity of −82dBm at a data rate of 500kb/s with an energy efficiency of 830pJ/bit.
{"title":"A 2.4GHz 830pJ/bit duty-cycled wake-up receiver with −82dBm sensitivity for crystal-less wireless sensor nodes","authors":"S. Drago, D. Leenaerts, F. Sebastiano, L. Breems, K. Makinwa, B. Nauta","doi":"10.1109/ISSCC.2010.5433955","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433955","url":null,"abstract":"This paper describes a 2.4GHz Wake-up Receiver (WuRx) designed to operate with low-accuracy (≪0.5%) frequency references [1], enabling crystal-less and thus low-cost wireless sensor nodes (WSNs). Robustness to frequency error is achieved by combining non-coherent energy detection with a broadband-IF superheterodyne architecture, and by using a pulse-position-modulated (PPM) impulse radio (IR) modulation scheme [2]. The Rx front-end and the LO generator are duty-cycled at pulse level, thereby reducing the power consumption to less than 420µW, which is more than adequate for use in WSNs [2]. PPM-IR also enables the realization of an interferer-robust receiver without the use of bulky off-chip RF filters [3,4]. This 65nm CMOS fully integrated WuRx employs a duty-cycled LO generator and achieves a sensitivity of −82dBm at a data rate of 500kb/s with an energy efficiency of 830pJ/bit.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"47 1","pages":"224-225"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73330713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434075
Charles L. Johnson, D. Allen, Jeffrey D. Brown, Steven P. Vanderwiel, R. Hoover, Heather D. Achilles, Chen-Yong Cher, G. May, H. Franke, J. Xenidis, C. Basso
An emerging data-center market merges network and server attributes into a single wire-speed processor SoC. These processors are not network endpoints that consume data, but inline processors that filter or modify data and send it on. Wire-speed processors merge attributes from 1) network processors: many threaded low power cores, accelerators, integrated network and memory I/O, smaller memory line sizes and low total power, and from 2) server processors: full ISA cores, standard programming models, OS and hypervisor support, full virtualization and server RAS & infrastructure. Typical applications are edge-of-network processing, intelligent I/O devices in servers, network attached appliances, distributed computing, and streaming applications.
{"title":"A wire-speed powerTM processor: 2.3GHz 45nm SOI with 16 cores and 64 threads","authors":"Charles L. Johnson, D. Allen, Jeffrey D. Brown, Steven P. Vanderwiel, R. Hoover, Heather D. Achilles, Chen-Yong Cher, G. May, H. Franke, J. Xenidis, C. Basso","doi":"10.1109/ISSCC.2010.5434075","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434075","url":null,"abstract":"An emerging data-center market merges network and server attributes into a single wire-speed processor SoC. These processors are not network endpoints that consume data, but inline processors that filter or modify data and send it on. Wire-speed processors merge attributes from 1) network processors: many threaded low power cores, accelerators, integrated network and memory I/O, smaller memory line sizes and low total power, and from 2) server processors: full ISA cores, standard programming models, OS and hypervisor support, full virtualization and server RAS & infrastructure. Typical applications are edge-of-network processing, intelligent I/O devices in servers, network attached appliances, distributed computing, and streaming applications.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"39 6 1","pages":"104-105"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81403551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433944
S. Farahvash, W. Roberts, Jake Easter, R. Wei, D. Stegmeir, Li Jin
Because of higher performance requirements, infrastructure transceivers have historically employed lower levels of on-chip integration than their handset counterparts. One of the main limiting components preventing on-chip integration is the Local Oscillator (LO). The phase noise performance of the LO and its switching speed are some of the most critical performance metrics for an infrastructure transceiver. The work presented here is a frequency synthesizer IC targeted at wireless infrastructure applications. Previous works on high-performance VCO design either did not address the large tuning bandwidth requirements [1] or lacked the required phase noise performance [2–3].
{"title":"A low-noise frequency synthesizer for infrastructure applications","authors":"S. Farahvash, W. Roberts, Jake Easter, R. Wei, D. Stegmeir, Li Jin","doi":"10.1109/ISSCC.2010.5433944","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433944","url":null,"abstract":"Because of higher performance requirements, infrastructure transceivers have historically employed lower levels of on-chip integration than their handset counterparts. One of the main limiting components preventing on-chip integration is the Local Oscillator (LO). The phase noise performance of the LO and its switching speed are some of the most critical performance metrics for an infrastructure transceiver. The work presented here is a frequency synthesizer IC targeted at wireless infrastructure applications. Previous works on high-performance VCO design either did not address the large tuning bandwidth requirements [1] or lacked the required phase noise performance [2–3].","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"16 1","pages":"250-251"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87769925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433974
Youngcheol Chae, Jimin Cheon, Seung-hyun Lim, Dongmyung Lee, Minho Kwon, Kwi-sung Yoo, Wun-ki Jung, Dong-Hun Lee, S. Ham, G. Han
Over the last few years, the demands for high-density and high-speed imaging have increased drastically. Since CMOS image sensors have the advantages of low power consumption and easy system integration, they have become dominant over CCDs in the consumer market [1–4]. A column-parallel ADC architecture is the most widely used ADC in CMOS image sensors for high-speed and low-power operation [2–6]. The column-parallel architecture can be classified as: successive-approximation register (SAR) [2], cyclic [3], single-slope (SS) [4], and delta-sigma (ΔΣ) [5,6] ADCs. Although SAR ADCs have been utilized for high-speed imaging, such as UDTV, they require a DAC in a column, whose area is unacceptably large for consumer electronics with a fine pixel pitch. Cyclic ADCs have also been reported in high-speed imaging, but they have high power consumption and high noise levels. Since SS ADCs provide relatively high resolution with minimum area, they have been widely used in CMOS image sensors. However, SS ADCs require very fast clock signals leading to high power consumption in the case of high-speed imaging. Although ΔΣ ADCs have been investigated for low-noise imaging, they have only been applied for low-speed imaging with large pixel pitch because of the complexity of ΔΣ modulators and following decimation filters.
{"title":"A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture","authors":"Youngcheol Chae, Jimin Cheon, Seung-hyun Lim, Dongmyung Lee, Minho Kwon, Kwi-sung Yoo, Wun-ki Jung, Dong-Hun Lee, S. Ham, G. Han","doi":"10.1109/ISSCC.2010.5433974","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433974","url":null,"abstract":"Over the last few years, the demands for high-density and high-speed imaging have increased drastically. Since CMOS image sensors have the advantages of low power consumption and easy system integration, they have become dominant over CCDs in the consumer market [1–4]. A column-parallel ADC architecture is the most widely used ADC in CMOS image sensors for high-speed and low-power operation [2–6]. The column-parallel architecture can be classified as: successive-approximation register (SAR) [2], cyclic [3], single-slope (SS) [4], and delta-sigma (ΔΣ) [5,6] ADCs. Although SAR ADCs have been utilized for high-speed imaging, such as UDTV, they require a DAC in a column, whose area is unacceptably large for consumer electronics with a fine pixel pitch. Cyclic ADCs have also been reported in high-speed imaging, but they have high power consumption and high noise levels. Since SS ADCs provide relatively high resolution with minimum area, they have been widely used in CMOS image sensors. However, SS ADCs require very fast clock signals leading to high power consumption in the case of high-speed imaging. Although ΔΣ ADCs have been investigated for low-noise imaging, they have only been applied for low-speed imaging with large pixel pitch because of the complexity of ΔΣ modulators and following decimation filters.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"24 1","pages":"394-395"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86444995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433824
Koji Fukuda, H. Yamashita, G. Ono, R. Nemoto, Eiichi Suzuki, T. Takemoto, F. Yuki, T. Saito
For the people involved with multi-Gb/s chip-to-chip serial links, reducing power dissipation per Gb/s to less than 1mW/(Gb/s) (i.e., 1pJ/b) has been a long-held goal. Several years ago, the power dissipation of these links was in the range of about 10 to 20mW/(Gb/s). In 2007, Poulton et al. developed a 14mW 6.25Gb/s transceiver with power efficiency of 2.2mW/(Gb/s) [1]. Thereafter, there were some efforts aiming to reduce power of each building block in a transceiver [2, 3]. This paper presents a 12.3mW 12.5Gb/s complete transceiver (including CDR, MUX/DEMUX, and global clock distribution)in 65nm CMOS with power efficiency of 0.98mW/(Gb/s). To achieve low power, a resonant-clock distribution with distributed on-chip inductors and a low-swing voltage-mode driver with pulse-current boosting are used in the transmitter, while a symbol-rate comparator/phase detector using 4-stage sense amplifier and phase-rotating PLL with variable delay are used in the receiver.
{"title":"A 12.3mW 12.5Gb/s complete transceiver in 65nm CMOS","authors":"Koji Fukuda, H. Yamashita, G. Ono, R. Nemoto, Eiichi Suzuki, T. Takemoto, F. Yuki, T. Saito","doi":"10.1109/ISSCC.2010.5433824","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433824","url":null,"abstract":"For the people involved with multi-Gb/s chip-to-chip serial links, reducing power dissipation per Gb/s to less than 1mW/(Gb/s) (i.e., 1pJ/b) has been a long-held goal. Several years ago, the power dissipation of these links was in the range of about 10 to 20mW/(Gb/s). In 2007, Poulton et al. developed a 14mW 6.25Gb/s transceiver with power efficiency of 2.2mW/(Gb/s) [1]. Thereafter, there were some efforts aiming to reduce power of each building block in a transceiver [2, 3]. This paper presents a 12.3mW 12.5Gb/s complete transceiver (including CDR, MUX/DEMUX, and global clock distribution)in 65nm CMOS with power efficiency of 0.98mW/(Gb/s). To achieve low power, a resonant-clock distribution with distributed on-chip inductors and a low-swing voltage-mode driver with pulse-current boosting are used in the transmitter, while a symbol-rate comparator/phase detector using 4-stage sense amplifier and phase-rotating PLL with variable delay are used in the receiver.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"24 1","pages":"368-369"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86633938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433820
Jason Tsai, S. Toh, Z. Guo, L. Pang, T. Liu, B. Nikolić
SRAM yield is often characterized through distributions of static read or write margins [1] [2]. These measurements are analog and therefore can be slow and provide a limited dataset. Distributions of per-cell minimum operating voltages can be characterized rapidly, however, and are often taken as a proxy to static noise margins. Both methods have a common limitation in that the characterization is done statically, thus ignoring any possible effects that may affect dynamic operation. Pulsed ring oscillators for evaluating SRAM cell read timing have been previously proposed [3]. In contrast, tunable ring oscillators (RO) for characterizing dynamic cell stability during write and read operations without the need to modify the SRAM array are demonstrated in this work. The performance variation is captured as a spread in RO operating frequencies and therefore can be obtained rapidly.
{"title":"SRAM stability characterization using tunable ring oscillators in 45nm CMOS","authors":"Jason Tsai, S. Toh, Z. Guo, L. Pang, T. Liu, B. Nikolić","doi":"10.1109/ISSCC.2010.5433820","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433820","url":null,"abstract":"SRAM yield is often characterized through distributions of static read or write margins [1] [2]. These measurements are analog and therefore can be slow and provide a limited dataset. Distributions of per-cell minimum operating voltages can be characterized rapidly, however, and are often taken as a proxy to static noise margins. Both methods have a common limitation in that the characterization is done statically, thus ignoring any possible effects that may affect dynamic operation. Pulsed ring oscillators for evaluating SRAM cell read timing have been previously proposed [3]. In contrast, tunable ring oscillators (RO) for characterizing dynamic cell stability during write and read operations without the need to modify the SRAM array are demonstrated in this work. The performance variation is captured as a spread in RO operating frequencies and therefore can be obtained rapidly.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"46 1","pages":"354-355"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90058973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433977
Takeo Azuma, T. Imagawa, Sanzo Ugawa, Yusuke Okada, H. Komobuchi, M. Ishii, S. Kasuga, Y. Kato
The recent trend in ultra-high-density cameras is running from HD to 4K2K, which will further extend to 8K4K / portable 4K2K. With advancements in device fabrication process technologies, there has been a pressing need for the miniaturization as well as high resolution and high sensitivity in image sensors [1].
{"title":"A 2.2/3-inch 4K2K CMOS image sensor based on dual resolution and exposure technique","authors":"Takeo Azuma, T. Imagawa, Sanzo Ugawa, Yusuke Okada, H. Komobuchi, M. Ishii, S. Kasuga, Y. Kato","doi":"10.1109/ISSCC.2010.5433977","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433977","url":null,"abstract":"The recent trend in ultra-high-density cameras is running from HD to 4K2K, which will further extend to 8K4K / portable 4K2K. With advancements in device fabrication process technologies, there has been a pressing need for the miniaturization as well as high resolution and high sensitivity in image sensors [1].","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"116 1","pages":"408-409"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79611443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434074
D. Wendel, R. Kalla, Robert Cargnoni, J. Clabes, J. Friedrich, R. Frech, J. Kahle, B. Sinharoy, William J. Starke, Scott A. Taylor, S. Weitzel, S. Chu, M. S. Islam, V. Zyuban
The next processor of the POWER ™ family, called POWER7™ is introduced. Eight quad-threaded cores are integrated together with two memory controllers and high-speed system links on a 567mm2 die, employing 1.2B transistors in 45nm CMOS SOI technology [4]. High on-chip performance and therefore bandwidth is achieved using 11 layers of low-к copper wiring and devices with enhanced dual-stress liners. The technology features deep trench [DT] capacitors that are used to build the 32MB embedded DRAM L3 based on a 0.067µm2 DRAM cell. DT capacitors are used also to reduce on-chip voltage-island supply noise. Focusing on speed, the dual-supply ripple-domino SRAM concepts follows the schemes described elsewhere.
{"title":"The implementation of POWER7TM: A highly parallel and scalable multi-core high-end server processor","authors":"D. Wendel, R. Kalla, Robert Cargnoni, J. Clabes, J. Friedrich, R. Frech, J. Kahle, B. Sinharoy, William J. Starke, Scott A. Taylor, S. Weitzel, S. Chu, M. S. Islam, V. Zyuban","doi":"10.1109/ISSCC.2010.5434074","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434074","url":null,"abstract":"The next processor of the POWER ™ family, called POWER7™ is introduced. Eight quad-threaded cores are integrated together with two memory controllers and high-speed system links on a 567mm2 die, employing 1.2B transistors in 45nm CMOS SOI technology [4]. High on-chip performance and therefore bandwidth is achieved using 11 layers of low-к copper wiring and devices with enhanced dual-stress liners. The technology features deep trench [DT] capacitors that are used to build the 32MB embedded DRAM L3 based on a 0.067µm2 DRAM cell. DT capacitors are used also to reduce on-chip voltage-island supply noise. Focusing on speed, the dual-supply ripple-domino SRAM concepts follows the schemes described elsewhere.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"1 1","pages":"102-103"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89317099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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