Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434079
Iliana Fujimori-Chen, R. Thewes
Advances in capacitive touch-sensor technology, LED dimming controllers for LCD backlight applications and an electronic compensation method to minimize OLED degradation are highlighted in the first 3 papers of this session.
{"title":"Session 6 overview: displays & biomedical devices","authors":"Iliana Fujimori-Chen, R. Thewes","doi":"10.1109/ISSCC.2010.5434079","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434079","url":null,"abstract":"Advances in capacitive touch-sensor technology, LED dimming controllers for LCD backlight applications and an electronic compensation method to minimize OLED degradation are highlighted in the first 3 papers of this session.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"22 1","pages":"112-113"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87408818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434054
S. Levantino, Marco Zanuso, C. Samori, A. Lacaita
Flicker noise up-conversion into close-in 1/f3 phase noise is still one of the major issues in the design of CMOS oscillators. Suppression techniques have been recently presented suggesting (i) adoption of a resonant network [1], (ii) reduction of transistor size [2] or (iii) insertion of source degeneration [3]. However, resonant solutions do not guarantee suppression over a wide frequency range, while the other options affect the oscillator start-up margin and degrade the “white” 1/f2 phase noise. This work presents an alternative technique that does not rely on resonant elements and does not affect both start-up margin and 1/f2 phase noise. Demonstration of the technique is described in a 65nm CMOS VCO design.
{"title":"Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band","authors":"S. Levantino, Marco Zanuso, C. Samori, A. Lacaita","doi":"10.1109/ISSCC.2010.5434054","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434054","url":null,"abstract":"Flicker noise up-conversion into close-in 1/f3 phase noise is still one of the major issues in the design of CMOS oscillators. Suppression techniques have been recently presented suggesting (i) adoption of a resonant network [1], (ii) reduction of transistor size [2] or (iii) insertion of source degeneration [3]. However, resonant solutions do not guarantee suppression over a wide frequency range, while the other options affect the oscillator start-up margin and degrade the “white” 1/f2 phase noise. This work presents an alternative technique that does not rely on resonant elements and does not affect both start-up margin and 1/f2 phase noise. Demonstration of the technique is described in a 65nm CMOS VCO design.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"59 1","pages":"50-51"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90583558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433813
Y. Fujimura, O. Hirabayashi, T. Sasaki, A. Suzuki, A. Kawasumi, Y. Takeyama, K. Kushida, G. Fukano, A. Katayama, Y. Niki, T. Yabe
This paper presents a configurable SRAM for low-voltage operation with constant-negative-level write buffer (CNL-WB) and level programmable wordline driver for single supply (LPWD-SS) operation. CNL-WB is suitable for compilable SRAMs and it improves write margin by featuring an automatic BL-level adjustment for configuration range of four to 512 cells/BL using a replica-BL technique. LPWD-SS optimizes the tradeoff between disturb and write margin of a memory cell, allowing a 60% shorter WL rise time than that of the conventional design [1] at 0.7V. A test-chip is fabricated in a 32nm high-k metal-gate CMOS technology with a 0.149µm2 6T-SRAM cell. Measurement results demonstrate a cell-failure rate improvement of two orders of magnitude for an array-configuration range of 64 to 256 rows by 64 to 256 columns.
{"title":"A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm2 cell in 32nm high-k metal-gate CMOS","authors":"Y. Fujimura, O. Hirabayashi, T. Sasaki, A. Suzuki, A. Kawasumi, Y. Takeyama, K. Kushida, G. Fukano, A. Katayama, Y. Niki, T. Yabe","doi":"10.1109/ISSCC.2010.5433813","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433813","url":null,"abstract":"This paper presents a configurable SRAM for low-voltage operation with constant-negative-level write buffer (CNL-WB) and level programmable wordline driver for single supply (LPWD-SS) operation. CNL-WB is suitable for compilable SRAMs and it improves write margin by featuring an automatic BL-level adjustment for configuration range of four to 512 cells/BL using a replica-BL technique. LPWD-SS optimizes the tradeoff between disturb and write margin of a memory cell, allowing a 60% shorter WL rise time than that of the conventional design [1] at 0.7V. A test-chip is fabricated in a 32nm high-k metal-gate CMOS technology with a 0.149µm2 6T-SRAM cell. Measurement results demonstrate a cell-failure rate improvement of two orders of magnitude for an array-configuration range of 64 to 256 rows by 64 to 256 columns.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"1 1","pages":"348-349"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88129963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434057
Luca Fanori, A. Liscidini, Rinaldo Castello
In all-digital phase-locked loops (ADPLLs), the quantization noise introduced by the frequency discretization in the digitally controlled oscillator (DCO) can affect the performance in terms of out-of-band phase noise. In particular, the additional quantization noise has to be kept significantly lower than the intrinsic oscillator phase-noise, mandating a very fine frequency resolution (e.g. less than one kHz in GSM) [1]. Typically, in LC oscillators, the digital tuning is realized using two (or more) capacitor banks for coarse and fine tuning. The first bank is used to compensate process and temperature variation and to select the channel while the second is required for the DCO modulation inside the PLL. Since the coarse tuning range can be several hundred MHz (e.g. 800MHz in GSM [1]), a frequency resolution in the range of kHz can result in unitary elements for the capacitor banks of the order of atto-Farads. Although such values can be achieved by means of capacitive divider networks [2], the sensitivity to mismatches and parasitics of these solutions limit the robustness of the design. Staszewski et al. solved this problem by introducing a dithering of the 3 less significant bits of the DCO frequency control word [1]. This approach reduces considerably the equivalent DCO frequency resolution (from 12kHz to 30Hz) but, as occurs in any ΔΣ data converter, the quantization noise is moved to higher frequencies where generally the phase-noise specifications are more challenging. Due to this problem, the frequency of dithering must be significantly increased (225MHz) to satisfy the emission mask requirements far away from the carrier [1].
{"title":"3.3GHz DCO with a frequency resolution of 150Hz for All-digital PLL","authors":"Luca Fanori, A. Liscidini, Rinaldo Castello","doi":"10.1109/ISSCC.2010.5434057","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434057","url":null,"abstract":"In all-digital phase-locked loops (ADPLLs), the quantization noise introduced by the frequency discretization in the digitally controlled oscillator (DCO) can affect the performance in terms of out-of-band phase noise. In particular, the additional quantization noise has to be kept significantly lower than the intrinsic oscillator phase-noise, mandating a very fine frequency resolution (e.g. less than one kHz in GSM) [1]. Typically, in LC oscillators, the digital tuning is realized using two (or more) capacitor banks for coarse and fine tuning. The first bank is used to compensate process and temperature variation and to select the channel while the second is required for the DCO modulation inside the PLL. Since the coarse tuning range can be several hundred MHz (e.g. 800MHz in GSM [1]), a frequency resolution in the range of kHz can result in unitary elements for the capacitor banks of the order of atto-Farads. Although such values can be achieved by means of capacitive divider networks [2], the sensitivity to mismatches and parasitics of these solutions limit the robustness of the design. Staszewski et al. solved this problem by introducing a dithering of the 3 less significant bits of the DCO frequency control word [1]. This approach reduces considerably the equivalent DCO frequency resolution (from 12kHz to 30Hz) but, as occurs in any ΔΣ data converter, the quantization noise is moved to higher frequencies where generally the phase-noise specifications are more challenging. Due to this problem, the frequency of dithering must be significantly increased (225MHz) to satisfy the emission mask requirements far away from the carrier [1].","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"28 1","pages":"48-49"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85312306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433957
Sanghoon Joo, Wu-Hsin Chen, Tae-Young Choi, M. Oh, Joo-Ho Park, Jae-Young Kim, B. Jung
The 802.15.4a low-rate WPAN standard adopts Impulse-Radio UWB (IR-UWB) to provide a low-power communication system with improved communication range, robustness, and mobility. Furthermore its standardized low-cost and high-accuracy ranging capability encourages many location-aware applications. Propelled by the numerous potential applications, there have been several efforts for its implementation recently [1–3]. However, the design optimization issues including compliance, ranging accuracy and energy-saving techniques remain largely unexplored. This work presents a fully integrated coherent transceiver that supports 3 channels in Band Group 1, 3 to 5GHz, with accurate ranging capability and active power management. The system uses digital root-raised-cosine (RRC) pulse synthesis and RF up/down-conversion, which allows a strict compliance with the standard for both RRC pulse shape and transmit spectrum in the presence of PVT variations.
{"title":"A fully integrated 802.15.4a IR-UWB Transceiver in 0.13µm CMOS with digital RRC synthesis","authors":"Sanghoon Joo, Wu-Hsin Chen, Tae-Young Choi, M. Oh, Joo-Ho Park, Jae-Young Kim, B. Jung","doi":"10.1109/ISSCC.2010.5433957","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433957","url":null,"abstract":"The 802.15.4a low-rate WPAN standard adopts Impulse-Radio UWB (IR-UWB) to provide a low-power communication system with improved communication range, robustness, and mobility. Furthermore its standardized low-cost and high-accuracy ranging capability encourages many location-aware applications. Propelled by the numerous potential applications, there have been several efforts for its implementation recently [1–3]. However, the design optimization issues including compliance, ranging accuracy and energy-saving techniques remain largely unexplored. This work presents a fully integrated coherent transceiver that supports 3 channels in Band Group 1, 3 to 5GHz, with accurate ranging capability and active power management. The system uses digital root-raised-cosine (RRC) pulse synthesis and RF up/down-conversion, which allows a strict compliance with the standard for both RRC pulse shape and transmit spectrum in the presence of PVT variations.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"10 1","pages":"228-229"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91146458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433830
Wenbo Liu, P. Huang, Y. Chiu
CMOS technology scaling has opened a pathway to high-performance analog-to-digital conversion in the nanometer regime, where switching is preferred over amplifying. Successive-approximation-register (SAR) is one of the conversion architectures that rely on the high switching speed of process technology, and is thus distinctively known for its superior energy efficiency, small chip area, and good digital compatibility. When properly implemented, a SAR ADC also benefits from a potential rail-to-rail input swing, 100% capacitance utilization during input sampling (thus low kT/C noise), and insensitivity to comparator offsets during the conversion process. The linearity-limiting factors for SAR ADC are capacitor mismatch, sampling switch non-idealities, as well as the reference voltage settling issue due to the high internal switching speed of the DAC. In this work, a sub-radix-2 SAR ADC is presented, which employs a perturbation-based digital background calibration scheme and a dynamic-threshold-comparison (DTC) technique to overcome some of these performance-limiting factors.
CMOS技术的缩放已经打开了在纳米范围内实现高性能模数转换的途径，其中开关比放大更受欢迎。逐次逼近寄存器(SAR)是一种依赖于工艺技术的高转换速度的转换架构，因此以其优越的能效、小芯片面积和良好的数字兼容性而闻名。如果实现得当，SAR ADC还受益于潜在的轨对轨输入摆幅、输入采样期间100%的电容利用率(因此低kT/C噪声)以及转换过程中对比较器偏移的不敏感性。SAR ADC的线性限制因素包括电容失配、采样开关非理想性，以及由于DAC的高内部开关速度而导致的参考电压沉降问题。在这项工作中，提出了一个次基数2 SAR ADC，它采用基于微扰的数字背景校准方案和动态阈值比较(DTC)技术来克服这些性能限制因素。
{"title":"A 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC achieving over 90dB SFDR","authors":"Wenbo Liu, P. Huang, Y. Chiu","doi":"10.1109/ISSCC.2010.5433830","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433830","url":null,"abstract":"CMOS technology scaling has opened a pathway to high-performance analog-to-digital conversion in the nanometer regime, where switching is preferred over amplifying. Successive-approximation-register (SAR) is one of the conversion architectures that rely on the high switching speed of process technology, and is thus distinctively known for its superior energy efficiency, small chip area, and good digital compatibility. When properly implemented, a SAR ADC also benefits from a potential rail-to-rail input swing, 100% capacitance utilization during input sampling (thus low kT/C noise), and insensitivity to comparator offsets during the conversion process. The linearity-limiting factors for SAR ADC are capacitor mismatch, sampling switch non-idealities, as well as the reference voltage settling issue due to the high internal switching speed of the DAC. In this work, a sub-radix-2 SAR ADC is presented, which employs a perturbation-based digital background calibration scheme and a dynamic-threshold-comparison (DTC) technique to overcome some of these performance-limiting factors.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"6 1","pages":"380-381"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90332004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434011
H. Yamada, Yutaka Onozuka, A. Iida, K. Itaya, H. Funaki
The MEMS-LSI integration technologies that have been reported are mainly implemented for monolithic integrated System on Chip (SoC) by applying the advantages of process compatibility between MEMS and CMOS LSI [1]. However, it has been impossible to integrate them in the case that MEMS and standard CMOS processes are incompatible. Furthermore, many MEMS-LSI integration technologies applying System in Package (SiP) technology with the interposer substrate to realize electronics devices have been reported. However, using SiP technology, it has not been possible to achieve high integration density comparable to that of monolithic integrated SoC because the interposer substrate occupies a large area in SiP. Accordingly, development of an advanced MEMS-LSI integration technology to realizing highly integrated SoC incorporating MEMS devices is required [2].
{"title":"A wafer-level heterogeneous technology integration for flexible pseudo-SoC","authors":"H. Yamada, Yutaka Onozuka, A. Iida, K. Itaya, H. Funaki","doi":"10.1109/ISSCC.2010.5434011","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434011","url":null,"abstract":"The MEMS-LSI integration technologies that have been reported are mainly implemented for monolithic integrated System on Chip (SoC) by applying the advantages of process compatibility between MEMS and CMOS LSI [1]. However, it has been impossible to integrate them in the case that MEMS and standard CMOS processes are incompatible. Furthermore, many MEMS-LSI integration technologies applying System in Package (SiP) technology with the interposer substrate to realize electronics devices have been reported. However, using SiP technology, it has not been possible to achieve high integration density comparable to that of monolithic integrated SoC because the interposer substrate occupies a large area in SiP. Accordingly, development of an advanced MEMS-LSI integration technology to realizing highly integrated SoC incorporating MEMS devices is required [2].","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"37 1","pages":"146-147"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76897951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433989
Ying Wu, P. Mok
Emerging polar transmitters for highly efficient and linear power amplifiers (PAs) demand for high-efficiency, high-bandwidth and low-ripple supply modulators. In [1], a linear regulator is used; however, its efficiency is low at low power levels. A switched-mode power supply (SMPS) is used in [2]; but the high switching loss due to high switching frequency (necessary for high bandwidth) limits the maximum efficiency to ∼76%. A hybrid amplifier (HA) topology combining both linear amplifier (LA) and switching amplifier (SA) is used in some recent work [3, 4]. In this topology, a high-bandwidth LA replicates the input envelope voltage Vin at its output Vo; while the high-efficiency SA supplies most of the load current within its bandwidth. Yet, the tracking bandwidth is finite in [3]; and the LA in [4] needs to supply most of the high-frequency load current due to the exceptionally large inductor (20µH) used for realizing small output ripple; and therefore, limiting the dynamic efficiency. Figure 10.1.1 shows the proposed wideband HA featuring two-phase switching (2PHSW) for reducing ripple and improving static efficiency, and a feedforward bandpass filter (FF-BBF) for enhancing dynamic efficiency.
{"title":"A two-phase switching hybrid supply modulator for polar transmitters with 9% efficiency improvement","authors":"Ying Wu, P. Mok","doi":"10.1109/ISSCC.2010.5433989","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433989","url":null,"abstract":"Emerging polar transmitters for highly efficient and linear power amplifiers (PAs) demand for high-efficiency, high-bandwidth and low-ripple supply modulators. In [1], a linear regulator is used; however, its efficiency is low at low power levels. A switched-mode power supply (SMPS) is used in [2]; but the high switching loss due to high switching frequency (necessary for high bandwidth) limits the maximum efficiency to ∼76%. A hybrid amplifier (HA) topology combining both linear amplifier (LA) and switching amplifier (SA) is used in some recent work [3, 4]. In this topology, a high-bandwidth LA replicates the input envelope voltage Vin at its output Vo; while the high-efficiency SA supplies most of the load current within its bandwidth. Yet, the tracking bandwidth is finite in [3]; and the LA in [4] needs to supply most of the high-frequency load current due to the exceptionally large inductor (20µH) used for realizing small output ripple; and therefore, limiting the dynamic efficiency. Figure 10.1.1 shows the proposed wideband HA featuring two-phase switching (2PHSW) for reducing ripple and improving static efficiency, and a feedforward bandpass filter (FF-BBF) for enhancing dynamic efficiency.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"263 1","pages":"196-197"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75107036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434049
K. Koli, J. Jussila, P. Sivonen, Sami Kallioinen, A. Pärssinen
A 900 MHz direct-conversion receiver with a ΔΣ feedback loop to RF occupies an active area of 1.2 mm2 in 65 nm CMOS. The concept prototype for low-band cellular operations achieves NF of 2.3 and 6.2 dB in conventional and ΔΣ modes, respectively, and out-of-band IIP3 up to ±4 dBm when the ΔΣ loop is active. The chip consumes 80 mW from a 1.2 V supply.
{"title":"A 900MHz direct ΔΣ receiver in 65nm CMOS","authors":"K. Koli, J. Jussila, P. Sivonen, Sami Kallioinen, A. Pärssinen","doi":"10.1109/ISSCC.2010.5434049","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434049","url":null,"abstract":"A 900 MHz direct-conversion receiver with a ΔΣ feedback loop to RF occupies an active area of 1.2 mm<sup>2</sup> in 65 nm CMOS. The concept prototype for low-band cellular operations achieves NF of 2.3 and 6.2 dB in conventional and ΔΣ modes, respectively, and out-of-band IIP3 up to ±4 dBm when the ΔΣ loop is active. The chip consumes 80 mW from a 1.2 V supply.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"22 1","pages":"64-65"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73064668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434008
Source synchronous links are often used in server systems for multi-lane high-speed serial applications such as connecting CPU to CPU, to memory, or to bridge chips due to their inherent tracking of correlated jitter [1]. This paper presents a low-power compact differential source synchronous receiver PHY comprised of 22 data lanes and 1 clock lane. This receiver, plus a corresponding transmitter and impedance calibration macro, support multiple differential and ground terminated link standards at 4.8 to 6.4Gb/s, such as Intel QPI 1.0 and IBM proprietary memory links.
{"title":"A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS","authors":"","doi":"10.1109/ISSCC.2010.5434008","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434008","url":null,"abstract":"Source synchronous links are often used in server systems for multi-lane high-speed serial applications such as connecting CPU to CPU, to memory, or to bridge chips due to their inherent tracking of correlated jitter [1]. This paper presents a low-power compact differential source synchronous receiver PHY comprised of 22 data lanes and 1 clock lane. This receiver, plus a corresponding transmitter and impedance calibration macro, support multiple differential and ground terminated link standards at 4.8 to 6.4Gb/s, such as Intel QPI 1.0 and IBM proprietary memory links.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"67 1","pages":"160-161"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72547315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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