Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434032
S. Rusu, Sonia Leon
Processors have long been the leading edge of integration and process technology and this year's papers emphatically demonstrate that this is still the case. This year's crop of processors exhibit astounding increases in chip integration levels with more cores, special-function units and huge increases in the bandwidth of both on- and off-die interconnect. Emerging markets combine the attributes of network processors (many-threaded low-power cores) and server processors (large cores with virtualization and RAS). Higher levels of memory integration are achieved by using embedded DRAM in these large processors to support the higher-bandwidth demands of throughput computing. The challenges of managing the dramatic growth in dynamic power and leakage (if all integrated components were allowed to activate simultaneously) are addressed with a variety of innovative power management methods such as on-die gating and multiple voltage and frequency domains. Moore's law continues as the first 32nm processors from Intel and AMD are described, together with the latest implementation of the POWER and SPARC architectures.
{"title":"Session 5 overview: Processors","authors":"S. Rusu, Sonia Leon","doi":"10.1109/ISSCC.2010.5434032","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434032","url":null,"abstract":"Processors have long been the leading edge of integration and process technology and this year's papers emphatically demonstrate that this is still the case. This year's crop of processors exhibit astounding increases in chip integration levels with more cores, special-function units and huge increases in the bandwidth of both on- and off-die interconnect. Emerging markets combine the attributes of network processors (many-threaded low-power cores) and server processors (large cores with virtualization and RAS). Higher levels of memory integration are achieved by using embedded DRAM in these large processors to support the higher-bandwidth demands of throughput computing. The challenges of managing the dramatic growth in dynamic power and leakage (if all integrated components were allowed to activate simultaneously) are addressed with a variety of innovative power management methods such as on-die gating and multiple voltage and frequency domains. Moore's law continues as the first 32nm processors from Intel and AMD are described, together with the latest implementation of the POWER and SPARC architectures.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"27 1","pages":"94-95"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74981422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434036
S. Samala, Vineet Mishra, Kalyan Chekuri Chakravarthi
Integrating audio and power management into a system-on-chip (SoC) is of interest due to reduced board area and cost. Integrated Class-D audio drivers need to drive high voltages to deliver high power across small loads; 525mW (5.8Vpp differential) across an 8Ω load working off the battery. Absence of high-voltage transistors along with high device noise (flicker), device mismatch and leakage pose design challenges in 45nm CMOS.
{"title":"45nm CMOS 8Ω Class-D audio driver with 79% efficiency and 100dB SNR","authors":"S. Samala, Vineet Mishra, Kalyan Chekuri Chakravarthi","doi":"10.1109/ISSCC.2010.5434036","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434036","url":null,"abstract":"Integrating audio and power management into a system-on-chip (SoC) is of interest due to reduced board area and cost. Integrated Class-D audio drivers need to drive high voltages to deliver high power across small loads; 525mW (5.8Vpp differential) across an 8Ω load working off the battery. Absence of high-voltage transistors along with high device noise (flicker), device mismatch and leakage pose design challenges in 45nm CMOS.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"126 1","pages":"86-87"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77024909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433915
C. Benkeser, A. Bubenhofer, Qiuting Huang
Recent popularity of smart phones and other mobile broadband devices has given fresh impetus to 3G technology and beyond, which provides a key enabler to the mobile industry's only current growth sector. Despite the high data rates of 3G-enabled devices, good user experience still crucially depends on the availability of a fallback mode such as the GSM/EDGE network. While EDGE provides a respectable substitute where 3G is absent, enhancement is desirable both to lessen the disparity between HSPA and legacy EDGE and to improve 2G-only service in regions where upgrade to 3G is not imminent. Evolved EDGE (E-EDGE) is a recent standard [1] that aims to quintuple the EDGE rate to 1.2Mb/s by phasing in a set of extra technical features, including 32QAM and turbo coding. This contribution explores the challenges posed by higher order modulation and describes an efficient digital receiver that preserves the low-cost/low-power attributes of EDGE-enabled devices.
{"title":"A 4.5mW digital baseband receiver for level-A evolved EDGE","authors":"C. Benkeser, A. Bubenhofer, Qiuting Huang","doi":"10.1109/ISSCC.2010.5433915","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433915","url":null,"abstract":"Recent popularity of smart phones and other mobile broadband devices has given fresh impetus to 3G technology and beyond, which provides a key enabler to the mobile industry's only current growth sector. Despite the high data rates of 3G-enabled devices, good user experience still crucially depends on the availability of a fallback mode such as the GSM/EDGE network. While EDGE provides a respectable substitute where 3G is absent, enhancement is desirable both to lessen the disparity between HSPA and legacy EDGE and to improve 2G-only service in regions where upgrade to 3G is not imminent. Evolved EDGE (E-EDGE) is a recent standard [1] that aims to quintuple the EDGE rate to 1.2Mb/s by phasing in a set of extra technical features, including 32QAM and turbo coding. This contribution explores the challenges posed by higher order modulation and describes an efficient digital receiver that preserves the low-cost/low-power attributes of EDGE-enabled devices.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"112 1","pages":"276-277"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89453018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433978
S. Itoh, Isamu Takai, M. Sarker, M. Hamai, K. Yasutomi, M. Andoh, S. Kawahito
Spatial optical communication has recently been of interest in the mobile local-area communication systems, especially in the automotive applications. It has many advantages over the radio communication such as robustness to jamming, human safety due to lack of electromagnetic waves and sender finding function. The image sensor communication (ISC) technology is useful for the spatial optical communication because to find the light source and to intensify the light energy density at the receiver, the optical receiver has to have signal light source finding and tracking functions. A few approaches for the ISC have been reported. CMOS ISC chips have been used for ID beacon detection [1] [2], where very low data rate is required. In an ISC chip for optical wireless LAN application [3], the data rate of several hundreds of MHz has been demonstrated. In this approach, however, photo-diode current of a 2-D detector array directly flows into external receiver circuits, and because of this, extremely large optical power using laser lights is required. The authors have reported an ISC chip for LED-light communications [4]. In this chip, the bit rate of 1Mb/s and the communication range of a few meters only have been demonstrated. Though the chip claims the function of signal light source tracking, no experimental results have been shown. This paper presents a CMOS ISC chip which demonstrates that the high-speed long-distance spatial optical communication over 10Mb/s and 50meters are realized for the system using LED light sources while attaining signal-light finding and tracking functions. The key techniques to improve the data rate and tracking performance are a new pixel structure using depleted diode, pulse equalizing, and binary flag image readout to find the exact area of light source.
{"title":"A CMOS image sensor for 10Mb/s 70m-range LED-based spatial optical communication","authors":"S. Itoh, Isamu Takai, M. Sarker, M. Hamai, K. Yasutomi, M. Andoh, S. Kawahito","doi":"10.1109/ISSCC.2010.5433978","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433978","url":null,"abstract":"Spatial optical communication has recently been of interest in the mobile local-area communication systems, especially in the automotive applications. It has many advantages over the radio communication such as robustness to jamming, human safety due to lack of electromagnetic waves and sender finding function. The image sensor communication (ISC) technology is useful for the spatial optical communication because to find the light source and to intensify the light energy density at the receiver, the optical receiver has to have signal light source finding and tracking functions. A few approaches for the ISC have been reported. CMOS ISC chips have been used for ID beacon detection [1] [2], where very low data rate is required. In an ISC chip for optical wireless LAN application [3], the data rate of several hundreds of MHz has been demonstrated. In this approach, however, photo-diode current of a 2-D detector array directly flows into external receiver circuits, and because of this, extremely large optical power using laser lights is required. The authors have reported an ISC chip for LED-light communications [4]. In this chip, the bit rate of 1Mb/s and the communication range of a few meters only have been demonstrated. Though the chip claims the function of signal light source tracking, no experimental results have been shown. This paper presents a CMOS ISC chip which demonstrates that the high-speed long-distance spatial optical communication over 10Mb/s and 50meters are realized for the system using LED light sources while attaining signal-light finding and tracking functions. The key techniques to improve the data rate and tracking performance are a new pixel structure using depleted diode, pulse equalizing, and binary flag image readout to find the exact area of light source.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"2 1","pages":"402-403"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84453680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434065
Tomoyuki Suzuki
Due to steady advancements in semiconductor technology, greatly-enhanced memory capacity and high-speed data processing are now available, creating many evolving types of audio and video electronic products. The digital camera represents this trend well, where image sensor evolution has been responsible for enabling strong market growth. CCD image sensors have contributed to the miniaturization of cameras by their continuous march toward smaller pixel size and improved resolution, leading to more megapixels and enhanced image quality. Recently, the image-sensor shift from CCDs to CMOS has enabled faster capture speeds and convenient HD (High Definition). The result of this evolution has been the impressive growth of the digital camera market. This presentation will illustrate the achievements of image-sensor development, and will outline the corresponding advancements in digital cameras. Further, the future of digital cameras will be elaborated, illustrating the way in which image sensors are leading camera growth.
{"title":"Challenges of image-sensor development","authors":"Tomoyuki Suzuki","doi":"10.1109/ISSCC.2010.5434065","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434065","url":null,"abstract":"Due to steady advancements in semiconductor technology, greatly-enhanced memory capacity and high-speed data processing are now available, creating many evolving types of audio and video electronic products. The digital camera represents this trend well, where image sensor evolution has been responsible for enabling strong market growth. CCD image sensors have contributed to the miniaturization of cameras by their continuous march toward smaller pixel size and improved resolution, leading to more megapixels and enhanced image quality. Recently, the image-sensor shift from CCDs to CMOS has enabled faster capture speeds and convenient HD (High Definition). The result of this evolution has been the impressive growth of the digital camera market. This presentation will illustrate the achievements of image-sensor development, and will outline the corresponding advancements in digital cameras. Further, the future of digital cameras will be elaborated, illustrating the way in which image sensors are leading camera growth.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"95 1","pages":"27-30"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83705225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433856
D. Draper, F. Campi, R. Krishnamurthy, T. Miyamori, S. Morton, W. Sansen, V. Stojanović, J. Stonick
This Forum is directed toward researchers and designers working in advanced technologies over the next 3-5 years. They will be required to solve emerging issues of signal and power integrity in large, System-on-Chip applications which will raise issues of increasing difficulty. While struggling for higher performance, the designer must battle escalating noise and cross-talk. Interconnect delay and coupling will require new methods of routing and signal transmission. Supply-grid design will take increasing account of limited package and chip metalization through independent power domains, active and passive supply-noise cancellation, and voltage scaling. Increasingly- sensitive analog and RF circuit blocks must counter digital chip noise. Stringent clock-jitter and skew targets, and power-dissipation limitations will be addressed by independent clock domains, resonant clocking, and frequency scaling.
{"title":"F6: Signal and power integrity for SoCs","authors":"D. Draper, F. Campi, R. Krishnamurthy, T. Miyamori, S. Morton, W. Sansen, V. Stojanović, J. Stonick","doi":"10.1109/ISSCC.2010.5433856","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433856","url":null,"abstract":"This Forum is directed toward researchers and designers working in advanced technologies over the next 3-5 years. They will be required to solve emerging issues of signal and power integrity in large, System-on-Chip applications which will raise issues of increasing difficulty. While struggling for higher performance, the designer must battle escalating noise and cross-talk. Interconnect delay and coupling will require new methods of routing and signal transmission. Supply-grid design will take increasing account of limited package and chip metalization through independent power domains, active and passive supply-noise cancellation, and voltage scaling. Increasingly- sensitive analog and RF circuit blocks must counter digital chip noise. Stringent clock-jitter and skew targets, and power-dissipation limitations will be addressed by independent clock domains, resonant clocking, and frequency scaling.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"13 1","pages":"520-520"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84075320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434004
Oleksiy Tyshchenko, A. Sheikholeslami, H. Tamura, Y. Tomita, H. Yamaguchi, M. Kibune, T. Yamamoto
ADC-based CDRs take digital samples of the received signal to recover the clock and data. Digital representation of the signal allows for extensive channel equalization in the digital domain. Recently-reported ADC-based CDRs sample the signal at 1× or 2× the baud rate. The 1× CDR aligns the sampling clock with the signal using a phase-tracking feedback loop [1–2], which requires a voltage-controlled oscillator or phase interpolator, both analog circuits, to adjust the phase of the sampling clock. To eliminate these analog circuits (and their phase control) in favor of an all-digital implementation, a blind-sampling ADC-based CDR (top of Fig. 8.6.1) samples the received signal at 2× without phase locking to the signal. The CDR then interpolates between the blind samples to obtain a new set of samples in order to recover the phase and data [3–4]. The doubling of the sampling rate, however, increases the ADC power consumption or, equivalently, reduces the maximum baud rate due to the conversion-rate limitations of ADCs.
{"title":"A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS","authors":"Oleksiy Tyshchenko, A. Sheikholeslami, H. Tamura, Y. Tomita, H. Yamaguchi, M. Kibune, T. Yamamoto","doi":"10.1109/ISSCC.2010.5434004","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434004","url":null,"abstract":"ADC-based CDRs take digital samples of the received signal to recover the clock and data. Digital representation of the signal allows for extensive channel equalization in the digital domain. Recently-reported ADC-based CDRs sample the signal at 1× or 2× the baud rate. The 1× CDR aligns the sampling clock with the signal using a phase-tracking feedback loop [1–2], which requires a voltage-controlled oscillator or phase interpolator, both analog circuits, to adjust the phase of the sampling clock. To eliminate these analog circuits (and their phase control) in favor of an all-digital implementation, a blind-sampling ADC-based CDR (top of Fig. 8.6.1) samples the received signal at 2× without phase locking to the signal. The CDR then interpolates between the blind samples to obtain a new set of samples in order to recover the phase and data [3–4]. The doubling of the sampling rate, however, increases the ADC power consumption or, equivalently, reduces the maximum baud rate due to the conversion-rate limitations of ADCs.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"15 1","pages":"166-167"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86745899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433851
Dan Sandström, M. Varonen, M. Kärkkäinen, K. Halonen
A W-band transmitter front-end has been implemented in 65 nm CMOS. The output power is higher than +4 dBm from 77 GHz to 94 GHz with an image rejection ratio from 15 dB to 25 dB. The highest 1 dB output compression point is +2.2 dBm with +6.6 dBm maximum power at 85 GHz. The transmitter draws 100 mA from a 1.2 V supply.
{"title":"A W-band 65nm CMOS transmitter front-end with 8GHz IF bandwidth and 20dB IR-ratio","authors":"Dan Sandström, M. Varonen, M. Kärkkäinen, K. Halonen","doi":"10.1109/ISSCC.2010.5433851","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433851","url":null,"abstract":"A W-band transmitter front-end has been implemented in 65 nm CMOS. The output power is higher than +4 dBm from 77 GHz to 94 GHz with an image rejection ratio from 15 dB to 25 dB. The highest 1 dB output compression point is +2.2 dBm with +6.6 dBm maximum power at 85 GHz. The transmitter draws 100 mA from a 1.2 V supply.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"27 1","pages":"418-419"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84141614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434047
Hyunwon Moon, Sangyoub Lee, Seungchan Heo, Hwayeal Yu, J. Yu, Ji-Soo Chang, S. Choi, Byeong-ha Park
Many mobile devices with personal navigation and location based services (LBS) are rapidly increasing in importance in our life. In particular, smart-phones with embedded GPS receivers are still growing their share and soon they will be the main products in the handset market. Co-existence of a GPS receiver together with cellular phones creates new challenges because leakage signals from the transmitters in 2G/3G systems are harmful interferers, making it difficult for the receiver to detect a weak GPS signal from satellites. In general, an external interstage SAW filter is used for rejecting blocking signals after the LNA. Recently, there have been attempts to remove the inter-stage SAW filter to minimize the number of external components required[1–3]. So, a single pre-select filter is only required to prevent the out-of-band signals from blocking the receiver between the antenna and the IC. Although previous publications utilize tuned LC loads to tolerate a strong interferer signal, the frequency selectivity of the LC resonators will show a limited performance because the center frequency of an LC-tuned structure is very dependent on PVT variations. In this paper, a fully integrated GPS receiver with robust characteristics against the large interferer signals is presented.
{"title":"A 23mW fully integrated GPS receiver with robust interferer rejection in 65nm CMOS","authors":"Hyunwon Moon, Sangyoub Lee, Seungchan Heo, Hwayeal Yu, J. Yu, Ji-Soo Chang, S. Choi, Byeong-ha Park","doi":"10.1109/ISSCC.2010.5434047","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434047","url":null,"abstract":"Many mobile devices with personal navigation and location based services (LBS) are rapidly increasing in importance in our life. In particular, smart-phones with embedded GPS receivers are still growing their share and soon they will be the main products in the handset market. Co-existence of a GPS receiver together with cellular phones creates new challenges because leakage signals from the transmitters in 2G/3G systems are harmful interferers, making it difficult for the receiver to detect a weak GPS signal from satellites. In general, an external interstage SAW filter is used for rejecting blocking signals after the LNA. Recently, there have been attempts to remove the inter-stage SAW filter to minimize the number of external components required[1–3]. So, a single pre-select filter is only required to prevent the out-of-band signals from blocking the receiver between the antenna and the IC. Although previous publications utilize tuned LC loads to tolerate a strong interferer signal, the frequency selectivity of the LC resonators will show a limited performance because the center frequency of an LC-tuned structure is very dependent on PVT variations. In this paper, a fully integrated GPS receiver with robust characteristics against the large interferer signals is presented.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"102 1-3","pages":"68-69"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91479096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433987
E. Soenen, A. Roth, Justin Shi, M. Kinyua, J. Gaither, Elizabeth Ortynska
The growing complexity and small form factors of hand-held consumer electronics are the driving force of more integration. This increases the need for truly embedded DC-DC converters in advanced processes. Traditional analog DC-DC converter architectures do not fit well with low supply voltages. Digital architectures are attractive, but require an analog-to-digital converter (ADC), which can be challenging to design [1–3].
{"title":"A robust digital DC-DC converter with rail-to-rail output range in 40nm CMOS","authors":"E. Soenen, A. Roth, Justin Shi, M. Kinyua, J. Gaither, Elizabeth Ortynska","doi":"10.1109/ISSCC.2010.5433987","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433987","url":null,"abstract":"The growing complexity and small form factors of hand-held consumer electronics are the driving force of more integration. This increases the need for truly embedded DC-DC converters in advanced processes. Traditional analog DC-DC converter architectures do not fit well with low supply voltages. Digital architectures are attractive, but require an analog-to-digital converter (ADC), which can be challenging to design [1–3].","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"3 1","pages":"198-199"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75976463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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