Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433978
S. Itoh, Isamu Takai, M. Sarker, M. Hamai, K. Yasutomi, M. Andoh, S. Kawahito
Spatial optical communication has recently been of interest in the mobile local-area communication systems, especially in the automotive applications. It has many advantages over the radio communication such as robustness to jamming, human safety due to lack of electromagnetic waves and sender finding function. The image sensor communication (ISC) technology is useful for the spatial optical communication because to find the light source and to intensify the light energy density at the receiver, the optical receiver has to have signal light source finding and tracking functions. A few approaches for the ISC have been reported. CMOS ISC chips have been used for ID beacon detection [1] [2], where very low data rate is required. In an ISC chip for optical wireless LAN application [3], the data rate of several hundreds of MHz has been demonstrated. In this approach, however, photo-diode current of a 2-D detector array directly flows into external receiver circuits, and because of this, extremely large optical power using laser lights is required. The authors have reported an ISC chip for LED-light communications [4]. In this chip, the bit rate of 1Mb/s and the communication range of a few meters only have been demonstrated. Though the chip claims the function of signal light source tracking, no experimental results have been shown. This paper presents a CMOS ISC chip which demonstrates that the high-speed long-distance spatial optical communication over 10Mb/s and 50meters are realized for the system using LED light sources while attaining signal-light finding and tracking functions. The key techniques to improve the data rate and tracking performance are a new pixel structure using depleted diode, pulse equalizing, and binary flag image readout to find the exact area of light source.
{"title":"A CMOS image sensor for 10Mb/s 70m-range LED-based spatial optical communication","authors":"S. Itoh, Isamu Takai, M. Sarker, M. Hamai, K. Yasutomi, M. Andoh, S. Kawahito","doi":"10.1109/ISSCC.2010.5433978","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433978","url":null,"abstract":"Spatial optical communication has recently been of interest in the mobile local-area communication systems, especially in the automotive applications. It has many advantages over the radio communication such as robustness to jamming, human safety due to lack of electromagnetic waves and sender finding function. The image sensor communication (ISC) technology is useful for the spatial optical communication because to find the light source and to intensify the light energy density at the receiver, the optical receiver has to have signal light source finding and tracking functions. A few approaches for the ISC have been reported. CMOS ISC chips have been used for ID beacon detection [1] [2], where very low data rate is required. In an ISC chip for optical wireless LAN application [3], the data rate of several hundreds of MHz has been demonstrated. In this approach, however, photo-diode current of a 2-D detector array directly flows into external receiver circuits, and because of this, extremely large optical power using laser lights is required. The authors have reported an ISC chip for LED-light communications [4]. In this chip, the bit rate of 1Mb/s and the communication range of a few meters only have been demonstrated. Though the chip claims the function of signal light source tracking, no experimental results have been shown. This paper presents a CMOS ISC chip which demonstrates that the high-speed long-distance spatial optical communication over 10Mb/s and 50meters are realized for the system using LED light sources while attaining signal-light finding and tracking functions. The key techniques to improve the data rate and tracking performance are a new pixel structure using depleted diode, pulse equalizing, and binary flag image readout to find the exact area of light source.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"2 1","pages":"402-403"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84453680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433915
C. Benkeser, A. Bubenhofer, Qiuting Huang
Recent popularity of smart phones and other mobile broadband devices has given fresh impetus to 3G technology and beyond, which provides a key enabler to the mobile industry's only current growth sector. Despite the high data rates of 3G-enabled devices, good user experience still crucially depends on the availability of a fallback mode such as the GSM/EDGE network. While EDGE provides a respectable substitute where 3G is absent, enhancement is desirable both to lessen the disparity between HSPA and legacy EDGE and to improve 2G-only service in regions where upgrade to 3G is not imminent. Evolved EDGE (E-EDGE) is a recent standard [1] that aims to quintuple the EDGE rate to 1.2Mb/s by phasing in a set of extra technical features, including 32QAM and turbo coding. This contribution explores the challenges posed by higher order modulation and describes an efficient digital receiver that preserves the low-cost/low-power attributes of EDGE-enabled devices.
{"title":"A 4.5mW digital baseband receiver for level-A evolved EDGE","authors":"C. Benkeser, A. Bubenhofer, Qiuting Huang","doi":"10.1109/ISSCC.2010.5433915","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433915","url":null,"abstract":"Recent popularity of smart phones and other mobile broadband devices has given fresh impetus to 3G technology and beyond, which provides a key enabler to the mobile industry's only current growth sector. Despite the high data rates of 3G-enabled devices, good user experience still crucially depends on the availability of a fallback mode such as the GSM/EDGE network. While EDGE provides a respectable substitute where 3G is absent, enhancement is desirable both to lessen the disparity between HSPA and legacy EDGE and to improve 2G-only service in regions where upgrade to 3G is not imminent. Evolved EDGE (E-EDGE) is a recent standard [1] that aims to quintuple the EDGE rate to 1.2Mb/s by phasing in a set of extra technical features, including 32QAM and turbo coding. This contribution explores the challenges posed by higher order modulation and describes an efficient digital receiver that preserves the low-cost/low-power attributes of EDGE-enabled devices.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"112 1","pages":"276-277"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89453018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434047
Hyunwon Moon, Sangyoub Lee, Seungchan Heo, Hwayeal Yu, J. Yu, Ji-Soo Chang, S. Choi, Byeong-ha Park
Many mobile devices with personal navigation and location based services (LBS) are rapidly increasing in importance in our life. In particular, smart-phones with embedded GPS receivers are still growing their share and soon they will be the main products in the handset market. Co-existence of a GPS receiver together with cellular phones creates new challenges because leakage signals from the transmitters in 2G/3G systems are harmful interferers, making it difficult for the receiver to detect a weak GPS signal from satellites. In general, an external interstage SAW filter is used for rejecting blocking signals after the LNA. Recently, there have been attempts to remove the inter-stage SAW filter to minimize the number of external components required[1–3]. So, a single pre-select filter is only required to prevent the out-of-band signals from blocking the receiver between the antenna and the IC. Although previous publications utilize tuned LC loads to tolerate a strong interferer signal, the frequency selectivity of the LC resonators will show a limited performance because the center frequency of an LC-tuned structure is very dependent on PVT variations. In this paper, a fully integrated GPS receiver with robust characteristics against the large interferer signals is presented.
{"title":"A 23mW fully integrated GPS receiver with robust interferer rejection in 65nm CMOS","authors":"Hyunwon Moon, Sangyoub Lee, Seungchan Heo, Hwayeal Yu, J. Yu, Ji-Soo Chang, S. Choi, Byeong-ha Park","doi":"10.1109/ISSCC.2010.5434047","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434047","url":null,"abstract":"Many mobile devices with personal navigation and location based services (LBS) are rapidly increasing in importance in our life. In particular, smart-phones with embedded GPS receivers are still growing their share and soon they will be the main products in the handset market. Co-existence of a GPS receiver together with cellular phones creates new challenges because leakage signals from the transmitters in 2G/3G systems are harmful interferers, making it difficult for the receiver to detect a weak GPS signal from satellites. In general, an external interstage SAW filter is used for rejecting blocking signals after the LNA. Recently, there have been attempts to remove the inter-stage SAW filter to minimize the number of external components required[1–3]. So, a single pre-select filter is only required to prevent the out-of-band signals from blocking the receiver between the antenna and the IC. Although previous publications utilize tuned LC loads to tolerate a strong interferer signal, the frequency selectivity of the LC resonators will show a limited performance because the center frequency of an LC-tuned structure is very dependent on PVT variations. In this paper, a fully integrated GPS receiver with robust characteristics against the large interferer signals is presented.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"102 1-3","pages":"68-69"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91479096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433987
E. Soenen, A. Roth, Justin Shi, M. Kinyua, J. Gaither, Elizabeth Ortynska
The growing complexity and small form factors of hand-held consumer electronics are the driving force of more integration. This increases the need for truly embedded DC-DC converters in advanced processes. Traditional analog DC-DC converter architectures do not fit well with low supply voltages. Digital architectures are attractive, but require an analog-to-digital converter (ADC), which can be challenging to design [1–3].
{"title":"A robust digital DC-DC converter with rail-to-rail output range in 40nm CMOS","authors":"E. Soenen, A. Roth, Justin Shi, M. Kinyua, J. Gaither, Elizabeth Ortynska","doi":"10.1109/ISSCC.2010.5433987","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433987","url":null,"abstract":"The growing complexity and small form factors of hand-held consumer electronics are the driving force of more integration. This increases the need for truly embedded DC-DC converters in advanced processes. Traditional analog DC-DC converter architectures do not fit well with low supply voltages. Digital architectures are attractive, but require an analog-to-digital converter (ADC), which can be challenging to design [1–3].","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"3 1","pages":"198-199"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75976463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433967
P. Harpe, Cui Zhou, Xiaoyang Wang, G. Dolmans, H. D. Groot
Applications like wireless sensor nodes require ultra low-power receivers with power-efficient ADCs. Moreover, the power-efficiency should be maintained for a wide range of sampling rates to enable system-level flexibility. Previously, the use of SAR ADCs has been proposed for low-power applications [1], [2]. This work describes the implementation of an 8bit asynchronous SAR ADC that achieves a 30fJ/Conversion-step power-efficiency for sampling rates between 10kS/s and 10MS/s.
{"title":"A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS","authors":"P. Harpe, Cui Zhou, Xiaoyang Wang, G. Dolmans, H. D. Groot","doi":"10.1109/ISSCC.2010.5433967","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433967","url":null,"abstract":"Applications like wireless sensor nodes require ultra low-power receivers with power-efficient ADCs. Moreover, the power-efficiency should be maintained for a wide range of sampling rates to enable system-level flexibility. Previously, the use of SAR ADCs has been proposed for low-power applications [1], [2]. This work describes the implementation of an 8bit asynchronous SAR ADC that achieves a 30fJ/Conversion-step power-efficiency for sampling rates between 10kS/s and 10MS/s.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"49 3 1","pages":"388-389"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78399957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434036
S. Samala, Vineet Mishra, Kalyan Chekuri Chakravarthi
Integrating audio and power management into a system-on-chip (SoC) is of interest due to reduced board area and cost. Integrated Class-D audio drivers need to drive high voltages to deliver high power across small loads; 525mW (5.8Vpp differential) across an 8Ω load working off the battery. Absence of high-voltage transistors along with high device noise (flicker), device mismatch and leakage pose design challenges in 45nm CMOS.
{"title":"45nm CMOS 8Ω Class-D audio driver with 79% efficiency and 100dB SNR","authors":"S. Samala, Vineet Mishra, Kalyan Chekuri Chakravarthi","doi":"10.1109/ISSCC.2010.5434036","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434036","url":null,"abstract":"Integrating audio and power management into a system-on-chip (SoC) is of interest due to reduced board area and cost. Integrated Class-D audio drivers need to drive high voltages to deliver high power across small loads; 525mW (5.8Vpp differential) across an 8Ω load working off the battery. Absence of high-voltage transistors along with high device noise (flicker), device mismatch and leakage pose design challenges in 45nm CMOS.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"126 1","pages":"86-87"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77024909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433945
C. Chevallier, C. Siau, S. Lim, Srivalli Namala, M. Matsuoka, B. Bateman, D. Rinerson
A number of technologies have been proposed to replace NAND Flash as scaling becomes more difficult [1–2]. One promising area includes resistive memories using the conductive metal oxide (CMOx™) technology where multiple memory layers can be stacked [3]. Earlier attempts have been made with non-rewritable materials [4]. The key concepts for a very high density, multi physical layer nonvolatile, rewritable memory have been developed on a 64Mb, 130 nm test chip.
{"title":"A 0.13µm 64Mb multi-layered conductive metal-oxide memory","authors":"C. Chevallier, C. Siau, S. Lim, Srivalli Namala, M. Matsuoka, B. Bateman, D. Rinerson","doi":"10.1109/ISSCC.2010.5433945","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433945","url":null,"abstract":"A number of technologies have been proposed to replace NAND Flash as scaling becomes more difficult [1–2]. One promising area includes resistive memories using the conductive metal oxide (CMOx™) technology where multiple memory layers can be stacked [3]. Earlier attempts have been made with non-rewritable materials [4]. The key concepts for a very high density, multi physical layer nonvolatile, rewritable memory have been developed on a 64Mb, 130 nm test chip.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"14 1","pages":"260-261"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79179549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434050
EDGE is currently the most widely used standard for data communications in mobile phones. Its proliferation has led to a need for low-cost 2.5G mobile solutions. The implementation of RF circuits in nanoscale digital CMOS with no or minimal process enhancements is one of the key obstacles limiting the complete SoC integration of cellular radio functionality with digital baseband. The key challenges for such RF integration include non-linearity of devices and circuits, device mismatches, process parameter spread, and the increasing potential for self-interference that could be induced by one function in the SoC onto another.
{"title":"A 0.8mm2 all-digital SAW-less polar transmitter in 65nm EDGE SoC","authors":"","doi":"10.1109/ISSCC.2010.5434050","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434050","url":null,"abstract":"EDGE is currently the most widely used standard for data communications in mobile phones. Its proliferation has led to a need for low-cost 2.5G mobile solutions. The implementation of RF circuits in nanoscale digital CMOS with no or minimal process enhancements is one of the key obstacles limiting the complete SoC integration of cellular radio functionality with digital baseband. The key challenges for such RF integration include non-linearity of devices and circuits, device mismatches, process parameter spread, and the increasing potential for self-interference that could be induced by one function in the SoC onto another.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"22 1","pages":"58-59"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73353349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433909
N. Miura, Kazutaka Kasuga, Mitsuko Saito, T. Kuroda
This paper presents an 8Tb/s 1pJ/b 0.8mm2/Tb/s quad data rate (QDR) inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM. The interface consists of 1024-bit parallel inductive-coupling transceivers operating at 8Gb/s/link. In the DRAM transceiver, data are multiplexed and demultiplexed by using a quadrature clock and XOR operation. This circuit technique for QDR compensates for transistor performance gap between the GPU and the DRAM to achieve 8Gb/s bandwidth. The clock for data retiming is recovered from the received data by using an injection-lock VCO. Clock links and clock distribution circuits are not needed, resulting in small layout area of 0.8mm2/Tb/s. Frontend of the transceiver is implemented using NMOS CML circuits with adaptive bias control. The transceiver's sensitivity to PVT variations is small, enabling all the 1024 parallel transceivers to operate at BER≪10{−16}. It also reduces the design margin required of the transceiver, resulting in power reduction to 1pJ/b. Compared to the latest wired 40nm DRAM interface [1], the bandwidth is 32x higher, while the energy consumption is 1/8 and the layout area is 1/22.
{"title":"An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM","authors":"N. Miura, Kazutaka Kasuga, Mitsuko Saito, T. Kuroda","doi":"10.1109/ISSCC.2010.5433909","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433909","url":null,"abstract":"This paper presents an 8Tb/s 1pJ/b 0.8mm2/Tb/s quad data rate (QDR) inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM. The interface consists of 1024-bit parallel inductive-coupling transceivers operating at 8Gb/s/link. In the DRAM transceiver, data are multiplexed and demultiplexed by using a quadrature clock and XOR operation. This circuit technique for QDR compensates for transistor performance gap between the GPU and the DRAM to achieve 8Gb/s bandwidth. The clock for data retiming is recovered from the received data by using an injection-lock VCO. Clock links and clock distribution circuits are not needed, resulting in small layout area of 0.8mm2/Tb/s. Frontend of the transceiver is implemented using NMOS CML circuits with adaptive bias control. The transceiver's sensitivity to PVT variations is small, enabling all the 1024 parallel transceivers to operate at BER≪10{−16}. It also reduces the design margin required of the transceiver, resulting in power reduction to 1pJ/b. Compared to the latest wired 40nm DRAM interface [1], the bandwidth is 32x higher, while the energy consumption is 1/8 and the layout area is 1/22.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"63 1","pages":"436-437"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73413000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433949
G. Marotta, A. Macerola, A. D'Alessandro, A. Torsi, C. Cerafogli, C. Lattaro, C. Musilli, Doyle Rivers, E. Sirizotti, F. Paolini, Giuliano Gennaro Imondi, G. Naso, G. Santin, L. Botticchio, L. D. Santis, L. Pilolli, M. Gallese, M. Incarnati, M. Tiburzi, P. Conenna, S. Perugini, V. Moschiano, W. D. Francesco, M. Goldman, C. Haid, D. D. Cicco, D. Orlandi, F. Rori, M. Rossini, T. Vali, R. Ghodsi, Frankie Roohparvar
In recent years applications such as mp3 players, SSD, digital cameras and video camcorders have driven the development of increasingly higher density NAND memories. In the presented 3b/cell memory the read and programming throughputs are been enhanced with the adoption of a quad-plane architecture and an industry standard even-odd bitline (BL) decoding scheme. The architecture, while featuring same page size of 16KB as recently disclosed ABL architectures [3,4], avoids the shortcomings such an ABL scheme exhibits in programming mode due to floating-gate-to-floating-gate coupling. The chip features both the newly developed synchronous DDR interface and the standard, asynchronous NAND flash interface. A 66-cell string is adopted to optimize the die size at 126mm2.
{"title":"A 3bit/cell 32Gb NAND flash memory at 34nm with 6MB/s program throughput and with dynamic 2b/cell blocks configuration mode for a program throughput increase up to 13MB/s","authors":"G. Marotta, A. Macerola, A. D'Alessandro, A. Torsi, C. Cerafogli, C. Lattaro, C. Musilli, Doyle Rivers, E. Sirizotti, F. Paolini, Giuliano Gennaro Imondi, G. Naso, G. Santin, L. Botticchio, L. D. Santis, L. Pilolli, M. Gallese, M. Incarnati, M. Tiburzi, P. Conenna, S. Perugini, V. Moschiano, W. D. Francesco, M. Goldman, C. Haid, D. D. Cicco, D. Orlandi, F. Rori, M. Rossini, T. Vali, R. Ghodsi, Frankie Roohparvar","doi":"10.1109/ISSCC.2010.5433949","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433949","url":null,"abstract":"In recent years applications such as mp3 players, SSD, digital cameras and video camcorders have driven the development of increasingly higher density NAND memories. In the presented 3b/cell memory the read and programming throughputs are been enhanced with the adoption of a quad-plane architecture and an industry standard even-odd bitline (BL) decoding scheme. The architecture, while featuring same page size of 16KB as recently disclosed ABL architectures [3,4], avoids the shortcomings such an ABL scheme exhibits in programming mode due to floating-gate-to-floating-gate coupling. The chip features both the newly developed synchronous DDR interface and the standard, asynchronous NAND flash interface. A 66-cell string is adopted to optimize the die size at 126mm2.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"86 1","pages":"444-445"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74018710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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