Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434012
A. Sheikholeslami, T. Saito
The demand for higher bandwidth in chip-to-chip and backplane communication is driven by the video transmission over the internet. This demand has driven the data rates to 10Gb/s and beyond. Currently, there are two approaches to address the increasing bandwidth requirement for high-speed transceivers: one is to increase the number of parallel lines while maintaining the line rate and the other is to increase the data rate per line while maintaining the number of parallel lines. The former eases the requirement for clock and data recovery, as the clock can be forwarded with small overhead. This is applicable to cases where the channel is short and linear equalization is sufficient to compensate for the channel loss. The latter reduces the number of pins on the chips and reduces the board area at the expense of more complicated equalization scheme and techniques for clock and data recovery (CDR). This is applicable to cases where the channel is long and linear equalization is no longer sufficient.
{"title":"Session 8 overview: High-speed wireline transceivers","authors":"A. Sheikholeslami, T. Saito","doi":"10.1109/ISSCC.2010.5434012","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434012","url":null,"abstract":"The demand for higher bandwidth in chip-to-chip and backplane communication is driven by the video transmission over the internet. This demand has driven the data rates to 10Gb/s and beyond. Currently, there are two approaches to address the increasing bandwidth requirement for high-speed transceivers: one is to increase the number of parallel lines while maintaining the line rate and the other is to increase the data rate per line while maintaining the number of parallel lines. The former eases the requirement for clock and data recovery, as the clock can be forwarded with small overhead. This is applicable to cases where the channel is short and linear equalization is sufficient to compensate for the channel loss. The latter reduces the number of pins on the chips and reduces the board area at the expense of more complicated equalization scheme and techniques for clock and data recovery (CDR). This is applicable to cases where the channel is long and linear equalization is no longer sufficient.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82623669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433814
J. Barth, D. Plass, E. Nelson, C. Hwang, G. Fredeman, M. Sperling, A. Mathews, W. Reohr, Kavita Nair, N. Cao
Logic-based embedded DRAM has matured into a wide range of ASIC applications, SRAM replacements [1] and off-chip caches for microprocessors [2]. While embedded DRAM has been leveraged in supercomputers such as IBM's BlueGene/L [3], it's use has been limited to moderate performance bulk logic technologies. Although prototypes have been demonstrated [4], DRAM has yet to be embedded on a high performance microprocessor. This paper discloses an SOI DRAM macro implemented on-chip with the IBM POWER7™ high performance microprocessor [5], and introduces enhancements to the micro sense amp (µSA) architecture [6]. This high performance DRAM macro is used to construct a large 32MB L3 cache on-chip, eliminating delay, area and power from the off-chip interface, simultaneously improving system performance, reducing cost, power and soft error vulnerability. Figure 19.1.1a shows an SEM of the 45nm SOI DRAM Device and Deep Trench (DT) capacitor [7]. DT offers 25x more capacitance than planar structures and was also utilized to reduce on-chip voltage island supply noise.
基于逻辑的嵌入式DRAM已经成熟到广泛的ASIC应用，SRAM替代品[1]和微处理器的片外缓存[2]。虽然嵌入式DRAM已经被用于超级计算机，如IBM的BlueGene/L[3]，但它的使用仅限于中等性能的批量逻辑技术。虽然原型已经被证明[4]，DRAM还没有被嵌入到高性能微处理器上。本文公开了一个采用IBM POWER7™高性能微处理器实现的SOI DRAM宏[5]，并介绍了对微感放大器(µSA)架构的增强[6]。采用该高性能DRAM宏在片上构建32MB的大型L3缓存，从片外接口上消除延迟、面积和功耗，同时提高系统性能，降低成本、功耗和软错误脆弱性。图19.1.1a显示了45nm SOI DRAM器件和深沟(DT)电容器的SEM[7]。DT提供比平面结构多25倍的电容，还用于降低片上电压岛电源噪声。
{"title":"A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache","authors":"J. Barth, D. Plass, E. Nelson, C. Hwang, G. Fredeman, M. Sperling, A. Mathews, W. Reohr, Kavita Nair, N. Cao","doi":"10.1109/ISSCC.2010.5433814","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433814","url":null,"abstract":"Logic-based embedded DRAM has matured into a wide range of ASIC applications, SRAM replacements [1] and off-chip caches for microprocessors [2]. While embedded DRAM has been leveraged in supercomputers such as IBM's BlueGene/L [3], it's use has been limited to moderate performance bulk logic technologies. Although prototypes have been demonstrated [4], DRAM has yet to be embedded on a high performance microprocessor. This paper discloses an SOI DRAM macro implemented on-chip with the IBM POWER7™ high performance microprocessor [5], and introduces enhancements to the micro sense amp (µSA) architecture [6]. This high performance DRAM macro is used to construct a large 32MB L3 cache on-chip, eliminating delay, area and power from the off-chip interface, simultaneously improving system performance, reducing cost, power and soft error vulnerability. Figure 19.1.1a shows an SEM of the 45nm SOI DRAM Device and Deep Trench (DT) capacitor [7]. DT offers 25x more capacitance than planar structures and was also utilized to reduce on-chip voltage island supply noise.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84630398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433935
P. Livi, F. Heer, U. Frey, D. Bakkum, A. Hierlemann
The most sophisticated information processing system, the human brain, consists of a huge number of neurons that form part of an intricate network and communicate through electrical and chemical signals via synapses. To elucidate interneuronal communication and network characteristics, it is important to gain bidirectional access (recording and stimulation) to individual neurons and to be able to do closed-loop experiments in cultures. The targeted stimulation of individual neurons, and the subsequent tracking of a signal's propagation is a valuable tool to decipher network structures as well as strength and plasticity of involved connections. CMOS-based microelectrode arrays (MEAs) featuring high spatial resolution (subcellular) and low noise provide a wealth of information. Extracellular electrodes ensure cell integrity and long-term recordings; neuronal stimulation is performed by either current or voltage pulses, with typical amplitudes of 0.1 to 1V or 5 to 10µA, and durations of 50 to 900µs [1].
{"title":"Compact voltage and current stimulation buffer for high-density microelectrode arrays","authors":"P. Livi, F. Heer, U. Frey, D. Bakkum, A. Hierlemann","doi":"10.1109/ISSCC.2010.5433935","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433935","url":null,"abstract":"The most sophisticated information processing system, the human brain, consists of a huge number of neurons that form part of an intricate network and communicate through electrical and chemical signals via synapses. To elucidate interneuronal communication and network characteristics, it is important to gain bidirectional access (recording and stimulation) to individual neurons and to be able to do closed-loop experiments in cultures. The targeted stimulation of individual neurons, and the subsequent tracking of a signal's propagation is a valuable tool to decipher network structures as well as strength and plasticity of involved connections. CMOS-based microelectrode arrays (MEAs) featuring high spatial resolution (subcellular) and low noise provide a wealth of information. Extracellular electrodes ensure cell integrity and long-term recordings; neuronal stimulation is performed by either current or voltage pulses, with typical amplitudes of 0.1 to 1V or 5 to 10µA, and durations of 50 to 900µs [1].","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83344593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433923
Ahmed M. A. Ali, Andrew S. Morgan, C. Dillon, G. Patterson, S. Puckett, M. Hensley, Russell Stop, Paritosh Bhoraskar, S. Bardsley, David Lattimore, Jeff Bray, Carroll Speir, Robert Sneed
Wireless communication applications have driven the development of high-resolution A/D converters (ADCs) with high sample rates, good AC performance and IF sampling capability to enable wider cellular coverage, more carriers, and to simplify the system design. We describe a 16b ADC with a sample rate up to 250MS/s that employs background calibration of the residue amplifier (RA) gain errors. The ADC has an integrated input buffer and is fabricated on a 0.18µm BiCMOS process. When the input buffer is bypassed, the SNR is 77.5dB and the SFDR is 90dB at 10MHz input frequency. With the input buffer, the SNR is 76dB and the SFDR is 95dB. The ADC consumes 850mW from a 1.8V supply, and the input buffer consumes 150mW from a 3V supply. The input span is 2.6Vp-p and the jitter is 60fs.
{"title":"A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration","authors":"Ahmed M. A. Ali, Andrew S. Morgan, C. Dillon, G. Patterson, S. Puckett, M. Hensley, Russell Stop, Paritosh Bhoraskar, S. Bardsley, David Lattimore, Jeff Bray, Carroll Speir, Robert Sneed","doi":"10.1109/ISSCC.2010.5433923","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433923","url":null,"abstract":"Wireless communication applications have driven the development of high-resolution A/D converters (ADCs) with high sample rates, good AC performance and IF sampling capability to enable wider cellular coverage, more carriers, and to simplify the system design. We describe a 16b ADC with a sample rate up to 250MS/s that employs background calibration of the residue amplifier (RA) gain errors. The ADC has an integrated input buffer and is fabricated on a 0.18µm BiCMOS process. When the input buffer is bypassed, the SNR is 77.5dB and the SFDR is 90dB at 10MHz input frequency. With the input buffer, the SNR is 76dB and the SFDR is 95dB. The ADC consumes 850mW from a 1.8V supply, and the input buffer consumes 150mW from a 3V supply. The input span is 2.6Vp-p and the jitter is 60fs.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83327107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433980
D. Stoppa, N. Massari, L. Pancheri, M. Malfatti, M. Perenzoni, L. Gonzo
Because we are living in a three-dimensional world, the usual intensity map provided by standard digital cameras is often not sufficient to build the sophisticated models required by systems capable of analyzing and interpreting their environment. A three-dimensional (3D) image sensor has great potential for improvement in many areas like ambient-assisted living, virtual reality, gaming, security and surveillance, etc., because it significantly increases the robustness of object classification and avoids time-consuming post-processing steps. Although the first commercial products are now available on the market, one of the main barriers to mass deployment of such 3D vision tools is the large pixel dimension, which ultimately reduces the sensor resolution and increases costs.
{"title":"An 80×60 range image sensor based on 10µm 50MHz lock-in pixels in 0.18µm CMOS","authors":"D. Stoppa, N. Massari, L. Pancheri, M. Malfatti, M. Perenzoni, L. Gonzo","doi":"10.1109/ISSCC.2010.5433980","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433980","url":null,"abstract":"Because we are living in a three-dimensional world, the usual intensity map provided by standard digital cameras is often not sufficient to build the sophisticated models required by systems capable of analyzing and interpreting their environment. A three-dimensional (3D) image sensor has great potential for improvement in many areas like ambient-assisted living, virtual reality, gaming, security and surveillance, etc., because it significantly increases the robustness of object classification and avoids time-consuming post-processing steps. Although the first commercial products are now available on the market, one of the main barriers to mass deployment of such 3D vision tools is the large pixel dimension, which ultimately reduces the sensor resolution and increases costs.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83907158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434001
H. Yamaguchi, H. Tamura, Y. Doi, Y. Tomita, T. Hamada, M. Kibune, Shuhei Ohmoto, Keita Tateishi, Oleksiy Tyshchenko, A. Sheikholeslami, Tomokazu Higuchi, J. Ogawa, Tamio Saito, H. Ishida, K. Gotoh
A high bandwidth and a robust performance are demanded in the consumer market applications. An ADC-based transceiver satisfies these demands and enables power/area scaling with process [1,2]. We developed and tested a spread-spectrum-clocking (SSC) compliant 5-Gb/s transceiver in 65-nm CMOS. The receiver uses an ADC-based front-end that samples the incoming signal without adjusting the phase relation between the sampling clock and the signal, hence eliminating the need for phase control of the sampling clock (Fig. 8.7.1). The phase tracking of the incoming signal and the data decision are performed entirely in the numerical domain without generating physical sampling-clock phases. An adaptive digital FFE (feed-forward equalizer) compensates for a channel loss up to 15dB at 2.5 GHz, using an on-chip adaptation controller based on CMA (constant-modulus algorithm). The CDR operated with BER less than 1E-12 when the transmitter and receiver clock signals were independently SSC-modulated at a modulation frequency of 30 kHz with a frequency deviation of 0 to −5000ppm.
{"title":"A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS","authors":"H. Yamaguchi, H. Tamura, Y. Doi, Y. Tomita, T. Hamada, M. Kibune, Shuhei Ohmoto, Keita Tateishi, Oleksiy Tyshchenko, A. Sheikholeslami, Tomokazu Higuchi, J. Ogawa, Tamio Saito, H. Ishida, K. Gotoh","doi":"10.1109/ISSCC.2010.5434001","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434001","url":null,"abstract":"A high bandwidth and a robust performance are demanded in the consumer market applications. An ADC-based transceiver satisfies these demands and enables power/area scaling with process [1,2]. We developed and tested a spread-spectrum-clocking (SSC) compliant 5-Gb/s transceiver in 65-nm CMOS. The receiver uses an ADC-based front-end that samples the incoming signal without adjusting the phase relation between the sampling clock and the signal, hence eliminating the need for phase control of the sampling clock (Fig. 8.7.1). The phase tracking of the incoming signal and the data decision are performed entirely in the numerical domain without generating physical sampling-clock phases. An adaptive digital FFE (feed-forward equalizer) compensates for a channel loss up to 15dB at 2.5 GHz, using an on-chip adaptation controller based on CMA (constant-modulus algorithm). The CDR operated with BER less than 1E-12 when the transmitter and receiver clock signals were independently SSC-modulated at a modulation frequency of 30 kHz with a frequency deviation of 0 to −5000ppm.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88834840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433958
Xiongchuan Huang, Simonetta Rampu, Xiaoyang Wang, G. Dolmans, H. D. Groot
In order to simultaneously optimize network lifetime and latency in wireless sensor networks (WSN), an always-on wake-up receiver (WuRx) can be used to monitor the radio link continuously. For truly autonomous sensor nodes employing energy scavenging, only 50µW power is available for the WuRx [1]. An envelope detector is a popular choice in WuRx because of its low power consumption. However, the detector is always the bottleneck of the receiver sensitivity since it attenuates low level input signal and adds excessive noise. One way of improving sensitivity is to amplify the signal before the detector, for example at RF [2, 3] or IF [4] stages, to enhance the SNR at the output.
{"title":"A 2.4GHz/915MHz 51µW wake-up receiver with offset and noise suppression","authors":"Xiongchuan Huang, Simonetta Rampu, Xiaoyang Wang, G. Dolmans, H. D. Groot","doi":"10.1109/ISSCC.2010.5433958","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433958","url":null,"abstract":"In order to simultaneously optimize network lifetime and latency in wireless sensor networks (WSN), an always-on wake-up receiver (WuRx) can be used to monitor the radio link continuously. For truly autonomous sensor nodes employing energy scavenging, only 50µW power is available for the WuRx [1]. An envelope detector is a popular choice in WuRx because of its low power consumption. However, the detector is always the bottleneck of the receiver sensitivity since it attenuates low level input signal and adds excessive noise. One way of improving sensitivity is to amplify the signal before the detector, for example at RF [2, 3] or IF [4] stages, to enhance the SNR at the output.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77108882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433948
K. Tsuchida, T. Inaba, K. Fujita, Y. Ueda, Takafumi Shimizu, Y. Asao, T. Kajiyama, M. Iwayama, K. Sugiura, S. Ikegawa, T. Kishi, T. Kai, M. Amano, N. Shimomura, H. Yoda, Y. Watanabe
In order to realize a sub-Giga bit scale NVRAM, the novel MRAM based on the spin-transfer-torque (STT) switching has been intensively investigated due to its excellent scalability compared with a conventional magnetic field induce switching MRAM [1]. However, the memory cell size of STT-MRAM reported so far is still over 1µm2, and the memory capacity is limited to 32Mbit even in almost 100mm2 die size [2]. The large cell size is due to the large switching current of MRAM cells. In order to reduce the cell size, we have proposed the perpendicular tunnel magnetoresistance (P-TMR) device, and have confirmed its high potential to achieve lower switching current [3]. In this paper, a 64Mb STTMRAM with the P-TMR device having the circuit techniques to maximize operational margin is described.
{"title":"A 64Mb MRAM with clamped-reference and adequate-reference schemes","authors":"K. Tsuchida, T. Inaba, K. Fujita, Y. Ueda, Takafumi Shimizu, Y. Asao, T. Kajiyama, M. Iwayama, K. Sugiura, S. Ikegawa, T. Kishi, T. Kai, M. Amano, N. Shimomura, H. Yoda, Y. Watanabe","doi":"10.1109/ISSCC.2010.5433948","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433948","url":null,"abstract":"In order to realize a sub-Giga bit scale NVRAM, the novel MRAM based on the spin-transfer-torque (STT) switching has been intensively investigated due to its excellent scalability compared with a conventional magnetic field induce switching MRAM [1]. However, the memory cell size of STT-MRAM reported so far is still over 1µm2, and the memory capacity is limited to 32Mbit even in almost 100mm2 die size [2]. The large cell size is due to the large switching current of MRAM cells. In order to reduce the cell size, we have proposed the perpendicular tunnel magnetoresistance (P-TMR) device, and have confirmed its high potential to achieve lower switching current [3]. In this paper, a 64Mb STTMRAM with the P-TMR device having the circuit techniques to maximize operational margin is described.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82443604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433821
Kenichi Maruko, Tatsuya Sugioka, H. Hayashi, Zhiwei Zhou, Yasunori Tsukuda, Y. Yagishita, H. Konishi, Toshikyuki Ogata, Hisashi Owa, T. Niki, K. Konda, M. Sato, Hiroshi Shiroshita, Takeshi Ogura, T. Aoki, H. Kihara, Sachiya Tanaka
Since the I/O bandwidth demand for mobile consumer electronics has been growing rapidly, the importance of high-speed low-power I/O links has also been increasing. Among proposed I/O architectures, [1] and [2] are attractive solutions. However, for an application that needs the burst-mode operation, the lock-in time should be within the period of several tens of bits. Therefore, the PLL-based phase rotator with a longer lock-in time, is not suitable for this purpose. In this paper, a 1.296-to-5.184Gb/s transceiver uses an injection-locking-based CDR. The proposed CDR architecture, dual-edge injection-locked oscillator CDR (DILO-CDR), realizes fast lock (≪20 bits), continuous-rate capability (1.296 to 5.184Gb/s) and 2× power efficiency [2.4mW/(Gb/s)] of previous fast-lock continuous-rate CDRs [3, 4].
{"title":"A 1.296-to-5.184Gb/s Transceiver with 2.4mW/(Gb/s) Burst-mode CDR using Dual-Edge Injection-Locked Oscillator","authors":"Kenichi Maruko, Tatsuya Sugioka, H. Hayashi, Zhiwei Zhou, Yasunori Tsukuda, Y. Yagishita, H. Konishi, Toshikyuki Ogata, Hisashi Owa, T. Niki, K. Konda, M. Sato, Hiroshi Shiroshita, Takeshi Ogura, T. Aoki, H. Kihara, Sachiya Tanaka","doi":"10.1109/ISSCC.2010.5433821","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433821","url":null,"abstract":"Since the I/O bandwidth demand for mobile consumer electronics has been growing rapidly, the importance of high-speed low-power I/O links has also been increasing. Among proposed I/O architectures, [1] and [2] are attractive solutions. However, for an application that needs the burst-mode operation, the lock-in time should be within the period of several tens of bits. Therefore, the PLL-based phase rotator with a longer lock-in time, is not suitable for this purpose. In this paper, a 1.296-to-5.184Gb/s transceiver uses an injection-locking-based CDR. The proposed CDR architecture, dual-edge injection-locked oscillator CDR (DILO-CDR), realizes fast lock (≪20 bits), continuous-rate capability (1.296 to 5.184Gb/s) and 2× power efficiency [2.4mW/(Gb/s)] of previous fast-lock continuous-rate CDRs [3, 4].","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72704425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433968
M. Furuta, M. Nozawa, T. Itakura
In 10b SAR ADCs, one of the major design challenges is the large number of capacitors for implementing the capacitor array. A large unit capacitance should be used due to the design constraint of capacitor mismatches and/or layout design rules. As a result, the total capacitance is typically much larger than what is required by kT/C noise. In [1], a 10-bit SAR ADC is presented that achieves an area of 0.075mm2 with a charge redistribution architecture using a small unit capacitance of 10fF, while SNDR is low becasue of using such a small unit capacitance. The charge-sharing SAR proposed in [2] allows a relatively large unit capacitance by reducing the required number of capacitors. However, it requires a large (10pF) S/H capacitor for precise operation. The ADC presented in [3] needs large logic circuits to implement a complex calibration. The converter presented in [4] is a pipelined ADC. The pipelined architecture overcomes the unit capacitance issue of SAR, but the area and the power consumption of the amplifiers are still large.
在10b SAR adc中，主要的设计挑战之一是用于实现电容器阵列的大量电容器。由于电容不匹配的设计约束和/或布局设计规则，应使用较大的单位电容。因此，总电容通常比kT/C噪声所要求的大得多。在[1]中，提出了一个10位SAR ADC，该ADC使用10fF的小单位电容实现了0.075mm2的电荷再分配架构，而由于使用了如此小的单位电容，SNDR很低。[2]中提出的电荷共享SAR通过减少所需的电容器数量，实现了相对较大的单位电容。然而，它需要一个大的(10pF) S/H电容器来精确操作。[3]中提出的ADC需要大型逻辑电路来实现复杂的校准。[4]中给出的转换器是一个流水线ADC。流水线结构克服了SAR的单位电容问题，但放大器的面积和功耗仍然很大。
{"title":"A 0.06mm2 8.9b ENOB 40MS/s pipelined SAR ADC in 65nm CMOS","authors":"M. Furuta, M. Nozawa, T. Itakura","doi":"10.1109/ISSCC.2010.5433968","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433968","url":null,"abstract":"In 10b SAR ADCs, one of the major design challenges is the large number of capacitors for implementing the capacitor array. A large unit capacitance should be used due to the design constraint of capacitor mismatches and/or layout design rules. As a result, the total capacitance is typically much larger than what is required by kT/C noise. In [1], a 10-bit SAR ADC is presented that achieves an area of 0.075mm2 with a charge redistribution architecture using a small unit capacitance of 10fF, while SNDR is low becasue of using such a small unit capacitance. The charge-sharing SAR proposed in [2] allows a relatively large unit capacitance by reducing the required number of capacitors. However, it requires a large (10pF) S/H capacitor for precise operation. The ADC presented in [3] needs large logic circuits to implement a complex calibration. The converter presented in [4] is a pipelined ADC. The pipelined architecture overcomes the unit capacitance issue of SAR, but the area and the power consumption of the amplifiers are still large.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73206192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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