Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433882
C. Y. Law, A. Pham
In wireless communications, high demand for superb video and audio quality increases the required transfer data rate. The unlicensed 7GHz bandwidth at V-band in North America has been drawing a lot of attention by companies and research institutions. Research topics done using CMOS fabrication, which appears to be a more appealing process due to its high level of integration, have been demonstrated to be a viable semiconductor for gigabit wireless at 60GHz [1]. According to the Federal Communications Commission (FCC) regulations, the maximum radiation power for 60GHz systems can reach up to 40dBm [2]. However, due to device limitations such as low maximum operating frequencies and low breakdown voltage, very few power amplifier (PA) designs using CMOS processes with high output power have been reported. To date, medium- to high-power amplifiers in this frequency range are normally implemented using III–V semiconductor fabrication processes.
{"title":"A high-gain 60GHz power amplifier with 20dBm output power in 90nm CMOS","authors":"C. Y. Law, A. Pham","doi":"10.1109/ISSCC.2010.5433882","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433882","url":null,"abstract":"In wireless communications, high demand for superb video and audio quality increases the required transfer data rate. The unlicensed 7GHz bandwidth at V-band in North America has been drawing a lot of attention by companies and research institutions. Research topics done using CMOS fabrication, which appears to be a more appealing process due to its high level of integration, have been demonstrated to be a viable semiconductor for gigabit wireless at 60GHz [1]. According to the Federal Communications Commission (FCC) regulations, the maximum radiation power for 60GHz systems can reach up to 40dBm [2]. However, due to device limitations such as low maximum operating frequencies and low breakdown voltage, very few power amplifier (PA) designs using CMOS processes with high output power have been reported. To date, medium- to high-power amplifiers in this frequency range are normally implemented using III–V semiconductor fabrication processes.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"19 1","pages":"426-427"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73673620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433877
Naresh R Shanbhag, Koichi Yamaguchi, R. Payne
Power consumption in modern day data centers is increasing rapidly to unmanageable proportions. Approximately 50% of the power in a data center is consumed in the electronics (servers, storage and interfaces) today.
{"title":"ES3: Energy-efficient high-speed interfaces","authors":"Naresh R Shanbhag, Koichi Yamaguchi, R. Payne","doi":"10.1109/ISSCC.2010.5433877","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433877","url":null,"abstract":"Power consumption in modern day data centers is increasing rapidly to unmanageable proportions. Approximately 50% of the power in a data center is consumed in the electronics (servers, storage and interfaces) today.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"40 1","pages":"524-525"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79114536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433912
Hyunggon Kim, Jungjune Park, Ki-Tae Park, Pansuk Kwak, O. Kwon, Chulbum Kim, Younyeol Lee, Sangsoo Park, Kyungmin Kim, Doohyung Cho, Juseok Lee, Jungho Song, Soowoong Lee, H. Yoo, Sanglok Kim, Seungwoo Yu, Sungjun Kim, Sungsoo Lee, K. Kyung, Yong Lim, C. Chung
Providing both low cost and high storage capacity by means of device scaling and multi-level cell has been a fundamental feature in developing of NAND flash memory to meet an ever-growing flash market. Recently, however, a high speed interface like DDR (Double Data Rate) was newly adopted in NAND flash to satisfy the requirement of emerging market such as SSD (Solid-State Disk) application where high read and write throughputs are demanded [1]. In addition, as NAND scaling further, a portion of data loading and data out times in overall NAND flash performance has been increased due to increasing page size from 2K to 8K bytes, and even up to 16K bytes at two-plane operation. It significantly affects overall performance degradation in not only SSD but also conventional flash card system. The high speed interface in NAND flash, however, causes to increase chip size because of multiple memory planes more than two and additional signal buses [1]. Therefore, a high speed data interface capability with minimized chip size penalty is required in DDR NAND flash. This paper presents 159mm2 32Gb MLC NAND flash which is capable of 200MB/s read and 12MB/s write throughputs in a 32nm technology.
通过器件缩放和多级单元提供低成本和高存储容量已成为NAND闪存发展的基本特征，以满足不断增长的闪存市场。然而，为了满足SSD (Solid-State Disk)应用等新兴市场对高读写吞吐量的需求，NAND闪存最近采用了DDR (Double Data Rate)等高速接口[1]。此外，随着NAND的进一步扩展，由于页面大小从2K增加到8K字节，甚至在双平面操作时增加到16K字节，整体NAND闪存性能中的一部分数据加载和数据输出时间已经增加。它不仅会严重影响SSD系统的整体性能，也会影响传统闪存卡系统的整体性能。然而，NAND闪存中的高速接口，由于多个存储平面超过两个和额外的信号总线，导致芯片尺寸增加[1]。因此，DDR NAND闪存需要具有最小芯片尺寸损失的高速数据接口能力。本文介绍了159mm2 32Gb MLC NAND闪存，该闪存在32nm技术下具有200MB/s的读取和12MB/s的写入吞吐量。
{"title":"A 159mm2 32nm 32Gb MLC NAND-flash memory with 200MB/s asynchronous DDR interface","authors":"Hyunggon Kim, Jungjune Park, Ki-Tae Park, Pansuk Kwak, O. Kwon, Chulbum Kim, Younyeol Lee, Sangsoo Park, Kyungmin Kim, Doohyung Cho, Juseok Lee, Jungho Song, Soowoong Lee, H. Yoo, Sanglok Kim, Seungwoo Yu, Sungjun Kim, Sungsoo Lee, K. Kyung, Yong Lim, C. Chung","doi":"10.1109/ISSCC.2010.5433912","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433912","url":null,"abstract":"Providing both low cost and high storage capacity by means of device scaling and multi-level cell has been a fundamental feature in developing of NAND flash memory to meet an ever-growing flash market. Recently, however, a high speed interface like DDR (Double Data Rate) was newly adopted in NAND flash to satisfy the requirement of emerging market such as SSD (Solid-State Disk) application where high read and write throughputs are demanded [1]. In addition, as NAND scaling further, a portion of data loading and data out times in overall NAND flash performance has been increased due to increasing page size from 2K to 8K bytes, and even up to 16K bytes at two-plane operation. It significantly affects overall performance degradation in not only SSD but also conventional flash card system. The high speed interface in NAND flash, however, causes to increase chip size because of multiple memory planes more than two and additional signal buses [1]. Therefore, a high speed data interface capability with minimized chip size penalty is required in DDR NAND flash. This paper presents 159mm2 32Gb MLC NAND flash which is capable of 200MB/s read and 12MB/s write throughputs in a 32nm technology.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"8 1","pages":"442-443"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85124919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434039
Alex Lollio, G. Bollati, R. Castello
Modern cellular phones incorporate hands-free operation, MP3 music playback and DMB reception. The users may wish to use these features for many hours and a low efficiency amplifier could deplete the battery in a short time. There are two classes of power amplifiers usually used for this application: Class-D and Class-AB. Class-D architectures provide the benefit of power efficiency at the cost of slightly reduced performance and a level of switching noise, which might, in some cases, interfere with RF functions such as mobile phone, GPS or FM radio reception. Class AB architecture has the benefit of higher audio quality and doesn't produce any switching noise, but its power efficiency is much lower. Notwithstanding their lower efficiency, the great majority of the headphone drivers in commerce operate in Class AB. A Class G is a high-efficiency analog amplifier without EMI problems that tries to bring together the best of Class AB and Class D. It uses multiple voltage rails and switches to the appropriate voltage as required by the instantaneous output voltage level. In this way, it never uses the high supply voltage when a low voltage output is required. The core of a Class G amplifier is the switching circuitry, which should enable a smooth handover of the load driving between the low voltage supply and the higher one. Furthermore, the switching strategy should satisfy two key points: first, the distortion due to the switching operation must be minimized to maintain high audio quality; second, the switching point must be as close as possible to the low voltage supply to maximize efficiency.
{"title":"Class-G headphone driver in 65nm CMOS technology","authors":"Alex Lollio, G. Bollati, R. Castello","doi":"10.1109/ISSCC.2010.5434039","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434039","url":null,"abstract":"Modern cellular phones incorporate hands-free operation, MP3 music playback and DMB reception. The users may wish to use these features for many hours and a low efficiency amplifier could deplete the battery in a short time. There are two classes of power amplifiers usually used for this application: Class-D and Class-AB. Class-D architectures provide the benefit of power efficiency at the cost of slightly reduced performance and a level of switching noise, which might, in some cases, interfere with RF functions such as mobile phone, GPS or FM radio reception. Class AB architecture has the benefit of higher audio quality and doesn't produce any switching noise, but its power efficiency is much lower. Notwithstanding their lower efficiency, the great majority of the headphone drivers in commerce operate in Class AB. A Class G is a high-efficiency analog amplifier without EMI problems that tries to bring together the best of Class AB and Class D. It uses multiple voltage rails and switches to the appropriate voltage as required by the instantaneous output voltage level. In this way, it never uses the high supply voltage when a low voltage output is required. The core of a Class G amplifier is the switching circuitry, which should enable a smooth handover of the load driving between the low voltage supply and the higher one. Furthermore, the switching strategy should satisfy two key points: first, the distortion due to the switching operation must be minimized to maintain high audio quality; second, the switching point must be as close as possible to the low voltage supply to maximize efficiency.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"86 1","pages":"84-85"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84104637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433839
W. Grollitsch, R. Nonis, N. D. Dalt
State of the art digital PLLs can be divided in two categories, depending on the implementation of the digital phase detector. Digital clocking and wireline applications mostly use a Bang-Bang detector (BBPLLs) [1–3], offering very low jitter values in integer-N mode but not supporting fractional-N synthesis, which is desirable to implement, i.e., spread spectrum clocking (SSC) for EMI reductions. Wireless applications implement time to digital converters (TDC) [4–6] which allow fractional-N synthesis, but require high architecture complexity, need calibration routines for period normalization, and introduce analog limitations that a digital PLL should be intended to eliminate.
{"title":"A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS","authors":"W. Grollitsch, R. Nonis, N. D. Dalt","doi":"10.1109/ISSCC.2010.5433839","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433839","url":null,"abstract":"State of the art digital PLLs can be divided in two categories, depending on the implementation of the digital phase detector. Digital clocking and wireline applications mostly use a Bang-Bang detector (BBPLLs) [1–3], offering very low jitter values in integer-N mode but not supporting fractional-N synthesis, which is desirable to implement, i.e., spread spectrum clocking (SSC) for EMI reductions. Wireless applications implement time to digital converters (TDC) [4–6] which allow fractional-N synthesis, but require high architecture complexity, need calibration routines for period normalization, and introduce analog limitations that a digital PLL should be intended to eliminate.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"46 1","pages":"478-479"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81008196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433962
Chungyeol P. Lee, A. Behzad, B. Marholev, V. Magoon, I. Bhatti, Dandan Li, Subhas Bothra, A. Afsahi, Dayo Ojo, R. Roufoogaran, Tom Li, Yuyu Chang, K. R. Rao, S. Au, Prasad Seetharam, K. Carter, J. Rael, Malcolm Macintosh, Bobby Lee, M. Rofougaran, R. Rofougaran, A. Hadji-Abdolhamid, M. Nariman, S. Khorram, S. Anand, E. Chien, Steve Wu, Carol Barrett, Lijun Zhang, A. Zolfaghari, H. Darabi, Ali Sarfaraz, B. Ibrahim, M. Gonikberg, Marcellus Forbes, Colin Fraser, Luis Gutierrez, Yury Gonikberg, M. Hafizi, Siukai Mak, Jesse Castaneda, Kimmer Kim, Zhenhua Liu, S. Bouras, Kevin Chien, V. Chandrasekhar, P. Chang, Edwin Li, Zhimin Zhao
The growing occurrences of WLAN, BT, and FM on the same mobile device have created a demand for putting all three on the same die to save on die size, I/O count, BOM, and ultimately cost. Common blocks such as crystal oscillator, bandgap, and power management units can be easily shared. This paper presents a solution in which 802.11a/b/g WLAN, single-stream 11n (SSN) WLAN, BT, and FM subsystem and radio are integrated on a single die.
{"title":"A multistandard, multiband SoC with integrated BT, FM, WLAN radios and integrated power amplifier","authors":"Chungyeol P. Lee, A. Behzad, B. Marholev, V. Magoon, I. Bhatti, Dandan Li, Subhas Bothra, A. Afsahi, Dayo Ojo, R. Roufoogaran, Tom Li, Yuyu Chang, K. R. Rao, S. Au, Prasad Seetharam, K. Carter, J. Rael, Malcolm Macintosh, Bobby Lee, M. Rofougaran, R. Rofougaran, A. Hadji-Abdolhamid, M. Nariman, S. Khorram, S. Anand, E. Chien, Steve Wu, Carol Barrett, Lijun Zhang, A. Zolfaghari, H. Darabi, Ali Sarfaraz, B. Ibrahim, M. Gonikberg, Marcellus Forbes, Colin Fraser, Luis Gutierrez, Yury Gonikberg, M. Hafizi, Siukai Mak, Jesse Castaneda, Kimmer Kim, Zhenhua Liu, S. Bouras, Kevin Chien, V. Chandrasekhar, P. Chang, Edwin Li, Zhimin Zhao","doi":"10.1109/ISSCC.2010.5433962","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433962","url":null,"abstract":"The growing occurrences of WLAN, BT, and FM on the same mobile device have created a demand for putting all three on the same die to save on die size, I/O count, BOM, and ultimately cost. Common blocks such as crystal oscillator, bandgap, and power management units can be easily shared. This paper presents a solution in which 802.11a/b/g WLAN, single-stream 11n (SSN) WLAN, BT, and FM subsystem and radio are integrated on a single die.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"128 1","pages":"454-455"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88039111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433817
K. Nii, M. Yabuuchi, Y. Tsukamoto, Y. Hirano, T. Iwamatsu, Y. Kihara
Voltage and technology scaling and increasing random variation in MOSFET characteristics reduce the operational margin of SRAM functionality, and several design techniques have been suggested to improve margins [1–3]. However, it is still difficult to achieve low-voltage operation (less than 1V) by design alone for devices such as sensor network applications using solar batteries. Design solutions combined with device techniques are required for robust SRAM operation and at the same time maintain low standby leakage.
{"title":"A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias","authors":"K. Nii, M. Yabuuchi, Y. Tsukamoto, Y. Hirano, T. Iwamatsu, Y. Kihara","doi":"10.1109/ISSCC.2010.5433817","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433817","url":null,"abstract":"Voltage and technology scaling and increasing random variation in MOSFET characteristics reduce the operational margin of SRAM functionality, and several design techniques have been suggested to improve margins [1–3]. However, it is still difficult to achieve low-voltage operation (less than 1V) by design alone for devices such as sensor network applications using solar batteries. Design solutions combined with device techniques are required for robust SRAM operation and at the same time maintain low standby leakage.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"53 1","pages":"356-357"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88051348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434041
Qinwen Fan, J. Huijsing, K. Makinwa
Amplifiers with low offset and low 1/f noise usually employ auto-zeroing (AZ) and/or chopping. However, AZ suffers from noise aliasing, and so requires more power dissipation for a given noise specification. Chopping, although free of noise aliasing, requires notch filters [1, 2] or AZ [3] to remove the ripple caused by up-modulated offset and 1/f noise. This paper describes a chopper-stabilized multi-path current-feedback instrumentation amplifier (CFIA), whose ripple is removed by a continuous-time (CT) ripple-reduction loop (RRL) [2]. In contrast to [2], the notch created by the RRL is eliminated by the use of a multi-path architecture. This results in a CFIA with a smooth single-pole response, which also achieves low offset (2µV) and low noise (21nV/√Hz) in a power efficient manner (NEF=9.6). By appropriately connecting its inputs, the CFIA can also be used as an opamp. In this configuration, its offset is further reduced while its noise and NEF are halved.
{"title":"A 21nV/√Hz chopper-stabilized multipath current-feedback instrumentation amplifier with 2µV offset","authors":"Qinwen Fan, J. Huijsing, K. Makinwa","doi":"10.1109/ISSCC.2010.5434041","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434041","url":null,"abstract":"Amplifiers with low offset and low 1/f noise usually employ auto-zeroing (AZ) and/or chopping. However, AZ suffers from noise aliasing, and so requires more power dissipation for a given noise specification. Chopping, although free of noise aliasing, requires notch filters [1, 2] or AZ [3] to remove the ripple caused by up-modulated offset and 1/f noise. This paper describes a chopper-stabilized multi-path current-feedback instrumentation amplifier (CFIA), whose ripple is removed by a continuous-time (CT) ripple-reduction loop (RRL) [2]. In contrast to [2], the notch created by the RRL is eliminated by the use of a multi-path architecture. This results in a CFIA with a smooth single-pole response, which also achieves low offset (2µV) and low noise (21nV/√Hz) in a power efficient manner (NEF=9.6). By appropriately connecting its inputs, the CFIA can also be used as an opamp. In this configuration, its offset is further reduced while its noise and NEF are halved.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"87 1","pages":"80-81"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85886271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434066
J. Marek
A car is skidding, and stabilizes itself without driver intervention; a laptop falls to the floor, and protects the hard drive by parking the read/write drive head automatically before impact; an airbag fires before the driver/occupant involved in an impending automotive crash impacts the steering wheel, thereby significantly reducing physical injury: - all systems involved are based exclusively on MEMS sensors. These crucial MEMS-sensor components of electronic control systems are making system reaction to human needs more intelligent, precise, and at much faster rates than humanly possible.
{"title":"MEMS for automotive and consumer electronics","authors":"J. Marek","doi":"10.1109/ISSCC.2010.5434066","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434066","url":null,"abstract":"A car is skidding, and stabilizes itself without driver intervention; a laptop falls to the floor, and protects the hard drive by parking the read/write drive head automatically before impact; an airbag fires before the driver/occupant involved in an impending automotive crash impacts the steering wheel, thereby significantly reducing physical injury: - all systems involved are based exclusively on MEMS sensors. These crucial MEMS-sensor components of electronic control systems are making system reaction to human needs more intelligent, precise, and at much faster rates than humanly possible.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"4 1","pages":"9-17"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88692669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433840
J. Borremans, Kameswaran Vengattaramane, Kameswaran Giannini, J. Craninckx
Digital-intensive PLL architectures emerge [1]–[4], exploiting the benefits of CMOS scaling. This work presents a digital-intensive, reconfigurable 86MHz–12GHz synthesizer. Simple 2-step background calibration enables the use of an area- and energy-efficient 5ps TDC (0.01mm2 and 15-pJ per-shot). Static mismatch calibration lowers the DAC area 4 times. The PLL, featuring digital phase modulation is fully reconfigurable, with loop bandwidth ranging from 0.1–2MHz. At 7GHz, the 0.28mm2 PLL achieves −144dBc/Hz phase noise at 20MHz offset, for 0.56ps jitter in 40MHz bandwidth, consuming less than 30mW.
{"title":"A 86MHz-to-12GHz digital-intensive phase-modulated fractional-N PLL using a 15pJ/Shot 5ps TDC in 40nm digital CMOS","authors":"J. Borremans, Kameswaran Vengattaramane, Kameswaran Giannini, J. Craninckx","doi":"10.1109/ISSCC.2010.5433840","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433840","url":null,"abstract":"Digital-intensive PLL architectures emerge [1]–[4], exploiting the benefits of CMOS scaling. This work presents a digital-intensive, reconfigurable 86MHz–12GHz synthesizer. Simple 2-step background calibration enables the use of an area- and energy-efficient 5ps TDC (0.01mm2 and 15-pJ per-shot). Static mismatch calibration lowers the DAC area 4 times. The PLL, featuring digital phase modulation is fully reconfigurable, with loop bandwidth ranging from 0.1–2MHz. At 7GHz, the 0.28mm2 PLL achieves −144dBc/Hz phase noise at 20MHz offset, for 0.56ps jitter in 40MHz bandwidth, consuming less than 30mW.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"106 1","pages":"480-481"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78932684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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