Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856023
J. S. Pereira, A. Petraglia
This paper presents a novel approach for the design of infinite impulse response (IIR) switched-capacitor (SC) filters, based on the optimum allocation of poles and zeros of a transfer function. This approach is aimed at the reduction of sensitivity in the passband and improved phase linearity. Comparisons with classical filter designs are made. An illustrative design example of a proposed low-pass IIR SC filter structure is presented along with experimental results obtained from a prototype filter built and tested in the laboratory.
{"title":"Low-sensitivity direct-form IIR SC filters with improved phase linearity","authors":"J. S. Pereira, A. Petraglia","doi":"10.1109/ISCAS.2000.856023","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856023","url":null,"abstract":"This paper presents a novel approach for the design of infinite impulse response (IIR) switched-capacitor (SC) filters, based on the optimum allocation of poles and zeros of a transfer function. This approach is aimed at the reduction of sensitivity in the passband and improved phase linearity. Comparisons with classical filter designs are made. An illustrative design example of a proposed low-pass IIR SC filter structure is presented along with experimental results obtained from a prototype filter built and tested in the laboratory.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":"61 1","pages":"169-172 vol.3"},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84474923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856432
M. Borremans, B. D. Muer, M. Steyaert
This paper presents the design trade-offs to implement an integrated CMOS quadrature oscillator based on a differential VCO and a differential-to-quadrature converting poly-phase filter. Both the traditional structure, with cascaded building blocks and the appropriate inter circuit buffers, and the merged version, without buffering, are discussed. In the latest, the excessive power consumption in the intermediate buffers is avoided. It is explained how the effect of the poly-phase filter on the phase noise performance of the VCO, can be taken into account in the design, resulting in an optimal trade-off between the overall power consumption and the phase-noise of the quadrature oscillation generator.
{"title":"The optimization of GHz integrated CMOS quadrature VCO's based on a poly-phase filter loaded differential oscillator","authors":"M. Borremans, B. D. Muer, M. Steyaert","doi":"10.1109/ISCAS.2000.856432","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856432","url":null,"abstract":"This paper presents the design trade-offs to implement an integrated CMOS quadrature oscillator based on a differential VCO and a differential-to-quadrature converting poly-phase filter. Both the traditional structure, with cascaded building blocks and the appropriate inter circuit buffers, and the merged version, without buffering, are discussed. In the latest, the excessive power consumption in the intermediate buffers is avoided. It is explained how the effect of the poly-phase filter on the phase noise performance of the VCO, can be taken into account in the design, resulting in an optimal trade-off between the overall power consumption and the phase-noise of the quadrature oscillation generator.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":"46 1","pages":"729-732 vol.2"},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85004075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857096
T. Kan, K. Mak, D. Ma, H. Luong
A 2-V 900-MHz downconversion mixer to be used in a single-chip CMOS receiver is presented. The mixer is based on a Gilbert cell but uses two source-followers as current modulators rather than a common-source input stage in order to support low-voltage operation and to improve the linearity. Two prototypes have been made for different design trade-off. The first mixer prototype achieves a measured conversion gain of -8 dB and an IIP3 of 26 dBm with a power consumption of 1.5 mW from a 3-V supply. The second prototype has a measured conversion gain of -2 dB, a noise figure (NF) of 22 dB and an IIP3 of 6 dBm with a power consumption of 3 mW from a single 2-V supply.
{"title":"A 2-V 900-MHz CMOS mixer for GSM receivers","authors":"T. Kan, K. Mak, D. Ma, H. Luong","doi":"10.1109/ISCAS.2000.857096","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857096","url":null,"abstract":"A 2-V 900-MHz downconversion mixer to be used in a single-chip CMOS receiver is presented. The mixer is based on a Gilbert cell but uses two source-followers as current modulators rather than a common-source input stage in order to support low-voltage operation and to improve the linearity. Two prototypes have been made for different design trade-off. The first mixer prototype achieves a measured conversion gain of -8 dB and an IIP3 of 26 dBm with a power consumption of 1.5 mW from a 3-V supply. The second prototype has a measured conversion gain of -2 dB, a noise figure (NF) of 22 dB and an IIP3 of 6 dBm with a power consumption of 3 mW from a single 2-V supply.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":"s1-2 1","pages":"327-330 vol.1"},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85972586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.855996
Chien‐Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, M. Sheu
The in-place path metric updating is a well-known technique for efficiently dealing with the management of path metric memory in Viterbi decoders. In this paper, we present a simple but efficient technique to partition the path metric memory into 2/sup i/ banks and then distribute a set of path metrics into scheduled add compare select (ACS) units. Results show that applying the presented scheduling technique the equivalent memory bandwidth can be increased with limited hardware overhead. The resulting architecture has the following characteristics: (1) the interconnection overhead between ACS units and the memory bank structure can be significantly reduced, (2) the control circuit is regular and the implementation can be derived in a systematic way. Therefore, the architecture can be easily applied to handle the convolutional code with a long constraint length and it is suitable to be implemented in VLSI applications.
{"title":"An efficient approach for in-place scheduling of path metric update in Viterbi decoders","authors":"Chien‐Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, M. Sheu","doi":"10.1109/ISCAS.2000.855996","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.855996","url":null,"abstract":"The in-place path metric updating is a well-known technique for efficiently dealing with the management of path metric memory in Viterbi decoders. In this paper, we present a simple but efficient technique to partition the path metric memory into 2/sup i/ banks and then distribute a set of path metrics into scheduled add compare select (ACS) units. Results show that applying the presented scheduling technique the equivalent memory bandwidth can be increased with limited hardware overhead. The resulting architecture has the following characteristics: (1) the interconnection overhead between ACS units and the memory bank structure can be significantly reduced, (2) the control circuit is regular and the implementation can be derived in a systematic way. Therefore, the architecture can be easily applied to handle the convolutional code with a long constraint length and it is suitable to be implemented in VLSI applications.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":"57 1","pages":"61-64 vol.3"},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76890457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.858764
J. Boudec, Patrick Thiran, S. Giordano
For pt. I see ibid., vol.4, p.93-6 (May 2000). We model some queuing systems arising in guaranteed service networks (such as RSVP/IP or ATM) as nonlinear min-plus systems that can be bounded by linear systems. We apply this method to the window flow control problem previously studied by Chang (1997), Agrawal and Rajan (1996), to the optimal smoothing of video through a network offering guaranteed service. We revisit the greedy shaper, and we also show how the same method enables us to compute the losses in a shaper by modelling it as a linear min-plus system. Finally, we describe the time-varying shaper.
{"title":"A short tutorial on network calculus. II. Min-plus system theory applied to communication networks","authors":"J. Boudec, Patrick Thiran, S. Giordano","doi":"10.1109/ISCAS.2000.858764","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.858764","url":null,"abstract":"For pt. I see ibid., vol.4, p.93-6 (May 2000). We model some queuing systems arising in guaranteed service networks (such as RSVP/IP or ATM) as nonlinear min-plus systems that can be bounded by linear systems. We apply this method to the window flow control problem previously studied by Chang (1997), Agrawal and Rajan (1996), to the optimal smoothing of video through a network offering guaranteed service. We revisit the greedy shaper, and we also show how the same method enables us to compute the losses in a shaper by modelling it as a linear min-plus system. Finally, we describe the time-varying shaper.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":"21 1","pages":"365-368 vol.4"},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80950001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857153
Lan-Da Van, Chih-Chun Tang, S. Tenqchen, Wu-Shiung Feng
In this paper, we propose the new two-dimensional (2-D) systolic-array structures of IIR/FIR digital filters without global broadcast by the different derivation and another systolic transformation. For more practical considerations, we further provide a detailed block diagram of a 2-D FIR filter using a recently proposed multiplier to reduce the roundoff quantization error in the logic-gate level. These proposed systolic structures amenable to VLSI implementation permit the 2-D input sequence to be scanned in row-wise mode and locally broadcast one value each clock per delay element.
{"title":"A new VLSI architecture without global broadcast for 2-D digital filters","authors":"Lan-Da Van, Chih-Chun Tang, S. Tenqchen, Wu-Shiung Feng","doi":"10.1109/ISCAS.2000.857153","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857153","url":null,"abstract":"In this paper, we propose the new two-dimensional (2-D) systolic-array structures of IIR/FIR digital filters without global broadcast by the different derivation and another systolic transformation. For more practical considerations, we further provide a detailed block diagram of a 2-D FIR filter using a recently proposed multiplier to reduce the roundoff quantization error in the logic-gate level. These proposed systolic structures amenable to VLSI implementation permit the 2-D input sequence to be scanned in row-wise mode and locally broadcast one value each clock per delay element.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":"79 1","pages":"547-550 vol.1"},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81000506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857471
Yaolin Jiang, Richard M. M. Chen, O. Wing
A new waveform bounding algorithm to obtain an upper and lower waveform bound of the time response of a class of RLC circuits is presented. The algorithm produces a sequence of waveforms which converge to the true solution monotonically from above and below. The key step is the choice of the initial guess in the relaxation process. A new method to obtain an initial guess that guarantees monotonic convergence is given. Numerical examples are included to confirm the theoretical results.
{"title":"A waveform bounding algorithm for simulation of RLC circuits","authors":"Yaolin Jiang, Richard M. M. Chen, O. Wing","doi":"10.1109/ISCAS.2000.857471","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857471","url":null,"abstract":"A new waveform bounding algorithm to obtain an upper and lower waveform bound of the time response of a class of RLC circuits is presented. The algorithm produces a sequence of waveforms which converge to the true solution monotonically from above and below. The key step is the choice of the initial guess in the relaxation process. A new method to obtain an initial guess that guarantees monotonic convergence is given. Numerical examples are included to confirm the theoretical results.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":"6 1","pages":"461-464 vol.5"},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82037027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.858697
R. Cruz, A. Santhanam
The development of scalable service models for integrated services networks is crucial for fostering interoperability and competition among multiple network service providers that support quality of service. A key scalability property of a service model is composability, which allows models for network elements in tandem to be lumped together into a composite model which is of the same type as the constituent service models. We present a new service model for lossy network elements, and show that it is composable. To illustrate the new service model, we characterize some fundamental network elements in terms of it.
{"title":"A composable service model for lossy network elements","authors":"R. Cruz, A. Santhanam","doi":"10.1109/ISCAS.2000.858697","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.858697","url":null,"abstract":"The development of scalable service models for integrated services networks is crucial for fostering interoperability and competition among multiple network service providers that support quality of service. A key scalability property of a service model is composability, which allows models for network elements in tandem to be lumped together into a composite model which is of the same type as the constituent service models. We present a new service model for lossy network elements, and show that it is composable. To illustrate the new service model, we characterize some fundamental network elements in terms of it.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":"29 1","pages":"97-100 vol.4"},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85692488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857053
Ying Li, Bendu Bai, L. Jiao
This paper presents a compound neural network model, i.e., adaptive neurofuzzy network (ANFN), which can be used for identifying the complicated nonlinear system. The proposed ANFN has a simple structure and exploits a hybrid algorithm combining supervised learning and unsupervised learning. In addition, ANFN is capable of overcoming the error of system identification due to the existence of some changing points and improving the accuracy of identification of the whole system. The effectiveness of the model and its algorithm is tested on the identification results of missile attacking area.
{"title":"An adaptive neurofuzzy network for identification of the complicated nonlinear system","authors":"Ying Li, Bendu Bai, L. Jiao","doi":"10.1109/ISCAS.2000.857053","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857053","url":null,"abstract":"This paper presents a compound neural network model, i.e., adaptive neurofuzzy network (ANFN), which can be used for identifying the complicated nonlinear system. The proposed ANFN has a simple structure and exploits a hybrid algorithm combining supervised learning and unsupervised learning. In addition, ANFN is capable of overcoming the error of system identification due to the existence of some changing points and improving the accuracy of identification of the whole system. The effectiveness of the model and its algorithm is tested on the identification results of missile attacking area.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":"40 1","pages":"164-167 vol.1"},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85893669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856014
O. Guerra, J. D. Rodríguez-García, E. Roca, F. Fernández, Á. Rodríguez-Vázquez
Limitations of existing approaches for symbolic analysis of large analog circuits are discussed. To address their solution, a new methodology for hierarchical symbolic analysis is introduced. The combination of a hierarchical modeling technique and approximation strategies, comprising circuit reduction, graph-based symbolic solution of circuit equations and matrix-based error control, provides optimum results in terms of speech and quality of results.
{"title":"An error-controlled methodology for approximate hierarchical symbolic analysis","authors":"O. Guerra, J. D. Rodríguez-García, E. Roca, F. Fernández, Á. Rodríguez-Vázquez","doi":"10.1109/ISCAS.2000.856014","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856014","url":null,"abstract":"Limitations of existing approaches for symbolic analysis of large analog circuits are discussed. To address their solution, a new methodology for hierarchical symbolic analysis is introduced. The combination of a hierarchical modeling technique and approximation strategies, comprising circuit reduction, graph-based symbolic solution of circuit equations and matrix-based error control, provides optimum results in terms of speech and quality of results.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":"9 1","pages":"133-136 vol.3"},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84038385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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