Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.858804
Jaewook Lee, H. Chiang
A comprehensive analysis of homotopy methods on the computation of all DC operating points of nonlinear circuits and systems is conducted. Several sufficient conditions for the connectivity of all the solutions along a single homotopy path are derived. These conditions offer criteria to determine a starting point from which one can find all the solutions along one homotopy path. For the class of nonlinear circuits and systems in which all the solutions lie on several homotopy paths, a new systematic method to explicitly construct a starting point for each homotopy path is developed, From a practical viewpoint, the constructive method developed does not require the difficult task of finding a good initial guess and is applicable to general nonlinear circuits and systems. From a methodological viewpoint, the constructive method developed is applicable to general homotopy methods with different homotopy functions.
{"title":"Constructive homotopy methods for finding all or multiple DC operating points of nonlinear circuits and systems","authors":"Jaewook Lee, H. Chiang","doi":"10.1109/ISCAS.2000.858804","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.858804","url":null,"abstract":"A comprehensive analysis of homotopy methods on the computation of all DC operating points of nonlinear circuits and systems is conducted. Several sufficient conditions for the connectivity of all the solutions along a single homotopy path are derived. These conditions offer criteria to determine a starting point from which one can find all the solutions along one homotopy path. For the class of nonlinear circuits and systems in which all the solutions lie on several homotopy paths, a new systematic method to explicitly construct a starting point for each homotopy path is developed, From a practical viewpoint, the constructive method developed does not require the difficult task of finding a good initial guess and is applicable to general nonlinear circuits and systems. From a methodological viewpoint, the constructive method developed is applicable to general homotopy methods with different homotopy functions.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84151097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents various analyses of computational behavior. Namely, the number of datapath operations and memory access on the core profile level 2 (CPL2) of MPEG-4 video standard. These analyzed data exploit the load distribution and mode selection of the video system. The exploration of data-flow behavior and its derived computation of MPEG-4 video processing algorithms will then drive through an efficient architecture design.
{"title":"Performance analysis and architecture evaluation of MPEG-4 video codec system","authors":"Hao-Chieh Chang, Liang-Gee Chen, Mei-Yun Hsu, Yung-Chi Chang","doi":"10.1109/ISCAS.2000.856361","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856361","url":null,"abstract":"This paper presents various analyses of computational behavior. Namely, the number of datapath operations and memory access on the core profile level 2 (CPL2) of MPEG-4 video standard. These analyzed data exploit the load distribution and mode selection of the video system. The exploration of data-flow behavior and its derived computation of MPEG-4 video processing algorithms will then drive through an efficient architecture design.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77843663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856173
Ankireddy Nalamalpu, W. Burleson
Repeaters are now widely used to increase the performance of long on-chip interconnections in CMOS VLSI. In this paper, we take an updated look at repeater insertion in state-of-the-art CMOS, using a new more detailed model. In spite of the more complex model, we present closed form expressions for the delay and the optimal repeater spacing and sizing. Our model is based on the alpha-power law to account for the short-channel effects and resistive loads that arise in deep sub-micron technologies. Unlike previous work, we model the repeater input as a ramp and accurately model both linear and saturation regions of operation for estimating the propagation delay. Our analytical repeater model is applied for estimating the performance of driving various repeated RC loads and exhibits a maximum error of only 5% when compared with SPICE in a 0.13 /spl mu/m CMOS technology. In practice, it is not always feasible to insert the repeaters at the exact optimal locations along an interconnect. We present a placement sensitivity analysis to quantify the effect of the sub-optimal repeater placement on performance. Closed form expressions are derived to re-size the repeaters to compensate for the sub-optimal placement.
{"title":"Repeater insertion in deep sub-micron CMOS: ramp-based analytical model and placement sensitivity analysis","authors":"Ankireddy Nalamalpu, W. Burleson","doi":"10.1109/ISCAS.2000.856173","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856173","url":null,"abstract":"Repeaters are now widely used to increase the performance of long on-chip interconnections in CMOS VLSI. In this paper, we take an updated look at repeater insertion in state-of-the-art CMOS, using a new more detailed model. In spite of the more complex model, we present closed form expressions for the delay and the optimal repeater spacing and sizing. Our model is based on the alpha-power law to account for the short-channel effects and resistive loads that arise in deep sub-micron technologies. Unlike previous work, we model the repeater input as a ramp and accurately model both linear and saturation regions of operation for estimating the propagation delay. Our analytical repeater model is applied for estimating the performance of driving various repeated RC loads and exhibits a maximum error of only 5% when compared with SPICE in a 0.13 /spl mu/m CMOS technology. In practice, it is not always feasible to insert the repeaters at the exact optimal locations along an interconnect. We present a placement sensitivity analysis to quantify the effect of the sub-optimal repeater placement on performance. Closed form expressions are derived to re-size the repeaters to compensate for the sub-optimal placement.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77950061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857372
Charles B. Prado, P. Diniz, F. França
Implementation of overlapped block filtering using Scheduling by Edge Reversal (SER) is proposed in this paper. SER is a very simple and powerful synchronizer. It allows more efficient implementation of parallel structures. This technique is applied for the first time to FIR filters using the overlapped block digital filtering, and implemented on a parallel computer platform. The results confirm the expected reduction in computation time.
{"title":"Implementation of overlapped block filtering using scheduling by edge reversal","authors":"Charles B. Prado, P. Diniz, F. França","doi":"10.1109/ISCAS.2000.857372","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857372","url":null,"abstract":"Implementation of overlapped block filtering using Scheduling by Edge Reversal (SER) is proposed in this paper. SER is a very simple and powerful synchronizer. It allows more efficient implementation of parallel structures. This technique is applied for the first time to FIR filters using the overlapped block digital filtering, and implemented on a parallel computer platform. The results confirm the expected reduction in computation time.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77981556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857428
A. Premkumar, M. Bhardwaj
The Residue Number System (RNS) offers unlimited opportunities for high performance arithmetic provided efficient forward and reverse converters could be constructed for the moduli set at hand. All forward conversion proposals to date, require some form of Read Only Memory (ROM) along with computational elements like Full Adders (FA). In this paper, we show that by formulating the forward conversion problem in terms of modular exponentiation and addition, we can achieve memory free conversion. We generalize our solution such that bit serial and bit parallel implementations can be derived by simply varying a parameter, namely, multiplexers. Apart from this formulation itself, the paper makes two other contributions. Firstly, it demonstrates an entirely new set of converters that use no look up. Secondly, we show how conversion complexity can be reduced significantly by sharing circuitry over several forward converters.
{"title":"Combinatorial logic based forward converters in residue number systems","authors":"A. Premkumar, M. Bhardwaj","doi":"10.1109/ISCAS.2000.857428","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857428","url":null,"abstract":"The Residue Number System (RNS) offers unlimited opportunities for high performance arithmetic provided efficient forward and reverse converters could be constructed for the moduli set at hand. All forward conversion proposals to date, require some form of Read Only Memory (ROM) along with computational elements like Full Adders (FA). In this paper, we show that by formulating the forward conversion problem in terms of modular exponentiation and addition, we can achieve memory free conversion. We generalize our solution such that bit serial and bit parallel implementations can be derived by simply varying a parameter, namely, multiplexers. Apart from this formulation itself, the paper makes two other contributions. Firstly, it demonstrates an entirely new set of converters that use no look up. Secondly, we show how conversion complexity can be reduced significantly by sharing circuitry over several forward converters.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73390377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857150
D. Franken
Wave digital filter principles are known to be applicable to the numerical solution of many kinds of differential equations. But, when applied to an electrical network containing nonlinear dynamical elements, the resulting algorithm often includes implicit equations. In this paper, a new approach is presented which leaves the underlying wave digital structure unchanged but avoids the task of finding exact solutions to the implicit equations involved.
{"title":"Wave digital simulation of electrical networks containing nonlinear dynamical elements-a new approach","authors":"D. Franken","doi":"10.1109/ISCAS.2000.857150","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857150","url":null,"abstract":"Wave digital filter principles are known to be applicable to the numerical solution of many kinds of differential equations. But, when applied to an electrical network containing nonlinear dynamical elements, the resulting algorithm often includes implicit equations. In this paper, a new approach is presented which leaves the underlying wave digital structure unchanged but avoids the task of finding exact solutions to the implicit equations involved.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79855176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.858749
L. Raffo, M. P. Zizola
In this paper a comparison between different methods for block matching in image processing with respect to the efficacy of their digital VLSI implementation is presented. In this framework a new method based on limiting the role of mismatching pixels is proposed. The results obtained on different kinds of images show that the new method achieves the best trade-off between complexity and results.
{"title":"Block-matching evaluation in digital architectures for motion estimation","authors":"L. Raffo, M. P. Zizola","doi":"10.1109/ISCAS.2000.858749","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.858749","url":null,"abstract":"In this paper a comparison between different methods for block matching in image processing with respect to the efficacy of their digital VLSI implementation is presented. In this framework a new method based on limiting the role of mismatching pixels is proposed. The results obtained on different kinds of images show that the new method achieves the best trade-off between complexity and results.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76958032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857048
Matthew Green, A. Zoubir
An approach for identifying time-varying nonlinear systems is presented. The time-variation of the system is approximated by a weighted combination of sequences from a given basis. In this case, to identify the system it is sufficient to estimate the time-invariant coefficients of the sequences. The focus of our investigation is on selecting these sequences to use in the approximation. We propose using a search method to determine which sequences contribute significantly to the approximation and thus lead to a parsimonious model that is able to characterise the system dynamics and time-variation together.
{"title":"A search for a parsimonious basis sequence approximation of time-varying, nonlinear systems","authors":"Matthew Green, A. Zoubir","doi":"10.1109/ISCAS.2000.857048","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857048","url":null,"abstract":"An approach for identifying time-varying nonlinear systems is presented. The time-variation of the system is approximated by a weighted combination of sequences from a given basis. In this case, to identify the system it is sufficient to estimate the time-invariant coefficients of the sequences. The focus of our investigation is on selecting these sequences to use in the approximation. We propose using a search method to determine which sequences contribute significantly to the approximation and thus lead to a parsimonious model that is able to characterise the system dynamics and time-variation together.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81362237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.858796
A. Fuller, B. Nowrouzian
In a previous publication, the theoretical basis provided by Kharitonov's stability theorem was exploited and applied to the development of a novel BIBO stability condition for general-order Bode-type variable-amplitude (VA) digital equalizers. This was achieved under the assumptions, (a) that the VA digital equalizer operates under infinite precision arithmetic, and (b) that it operates under "static" variable digital multiplier variations (i.e. variations which occur slowly or only after the transients resulting from the "dynamic" variations of the digital multiplier have died down to negligible levels). The present paper is concerned with an extension of the results to the investigation of the effect of "dynamic" variations of the variable digital multiplier on the stability and transient signal behaviour of the Bode-type VA digital equalizers both under infinite-precision as well as finite-precision digital equalizer operations. An analytical relationship is also derived for the estimation of the time required for the equalizer output signal transients to reduce to a specified negligible level. An application example is given to illustrate the practical application of the main results.
{"title":"Stability and transient behavior of Bode-type variable-amplitude digital equalizers with dynamic variable multiplier variations","authors":"A. Fuller, B. Nowrouzian","doi":"10.1109/ISCAS.2000.858796","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.858796","url":null,"abstract":"In a previous publication, the theoretical basis provided by Kharitonov's stability theorem was exploited and applied to the development of a novel BIBO stability condition for general-order Bode-type variable-amplitude (VA) digital equalizers. This was achieved under the assumptions, (a) that the VA digital equalizer operates under infinite precision arithmetic, and (b) that it operates under \"static\" variable digital multiplier variations (i.e. variations which occur slowly or only after the transients resulting from the \"dynamic\" variations of the digital multiplier have died down to negligible levels). The present paper is concerned with an extension of the results to the investigation of the effect of \"dynamic\" variations of the variable digital multiplier on the stability and transient signal behaviour of the Bode-type VA digital equalizers both under infinite-precision as well as finite-precision digital equalizer operations. An analytical relationship is also derived for the estimation of the time required for the equalizer output signal transients to reduce to a specified negligible level. An application example is given to illustrate the practical application of the main results.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82216516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857381
K. Chernyshov
The paper is focused on establishing strong consistency of recursive estimates of nonlinear characteristics of dynamic systems. To describe the shape of the nonlinearities, the regression function kernel type estimates are used. Within the approach presented, a feature of the technique is considering a case of mutually dependent observations. Simultaneously, only mild and easy verified assumptions with respect to the system's input and output processes, as well as to the external disturbances, are involved.
{"title":"Strongly consistent recursive regression estimation under depended observations","authors":"K. Chernyshov","doi":"10.1109/ISCAS.2000.857381","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857381","url":null,"abstract":"The paper is focused on establishing strong consistency of recursive estimates of nonlinear characteristics of dynamic systems. To describe the shape of the nonlinearities, the regression function kernel type estimates are used. Within the approach presented, a feature of the technique is considering a case of mutually dependent observations. Simultaneously, only mild and easy verified assumptions with respect to the system's input and output processes, as well as to the external disturbances, are involved.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82361731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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