Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.858680
Weiping Li
Internet communication has been growing rapidly from simple emails and file transfers to sophisticated streaming video and audio. Compared with more traditional means of communications, Internet communication has its own characteristics. Therefore, video coding for Internet streaming has different requirements. In order to understand Internet communication, we need to develop a push-pull communication model. This paper formulates the problem of video coding for Internet communication as an optimization problem over an interval of bitrate. It proposes an approach to solving this problem. This paper is also an attempt to understand the push-pull communication model.
{"title":"Video coding for Internet and push-pull communication","authors":"Weiping Li","doi":"10.1109/ISCAS.2000.858680","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.858680","url":null,"abstract":"Internet communication has been growing rapidly from simple emails and file transfers to sophisticated streaming video and audio. Compared with more traditional means of communications, Internet communication has its own characteristics. Therefore, video coding for Internet streaming has different requirements. In order to understand Internet communication, we need to develop a push-pull communication model. This paper formulates the problem of video coding for Internet communication as an optimization problem over an interval of bitrate. It proposes an approach to solving this problem. This paper is also an attempt to understand the push-pull communication model.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91098616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856132
A. Wassatsch, M. Haase, D. Timmermann
In this paper we describe an approach for using digit online arithmetic in the field of neural network computation. Digit online, a serial most significant digit first arithmetic, shows significant advantages over all other digital implementations. The serial communication between the online modules make the implementation of connection intensive networks feasible. The accuracy of the computation is only loosely coupled with the chosen digit level range, which determine the necessary count of interconnections. Furthermore, the accuracy is eligible through the length of the processed digit vector. The goal of this paper is to develop a strategy for the implementation of different network models. The comparison with the results of other implementations illustrate the advantages of the digit online approaches and the suitability for the application in the field of neural networks.
{"title":"DOLFIN-digit online for integration neural networks","authors":"A. Wassatsch, M. Haase, D. Timmermann","doi":"10.1109/ISCAS.2000.856132","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856132","url":null,"abstract":"In this paper we describe an approach for using digit online arithmetic in the field of neural network computation. Digit online, a serial most significant digit first arithmetic, shows significant advantages over all other digital implementations. The serial communication between the online modules make the implementation of connection intensive networks feasible. The accuracy of the computation is only loosely coupled with the chosen digit level range, which determine the necessary count of interconnections. Furthermore, the accuracy is eligible through the length of the processed digit vector. The goal of this paper is to develop a strategy for the implementation of different network models. The comparison with the results of other implementations illustrate the advantages of the digit online approaches and the suitability for the application in the field of neural networks.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91162864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857543
Shouli Yan, E. Sánchez-Sinencio
We proposed a novel technique for low voltage rail-to-rail constant-g/sub m/ input stages, which does not depend on the operation regions of the MOS transistors. An op amp was designed to demonstrate the new idea using MOSIS AMJ 1.2 /spl mu/m technology. A 2.5 MHz unity-gain bandwidth with 61/spl deg/ phase margin was achieved when driving 10 k/spl Omega/ and 10 pF load, with 240 /spl mu/A current consumption and a power supply of 3 V. The g/sub m/ variation of the input stage is within /spl plusmn/3% from rail-to-rail. By changing the bias current, the unity-gain bandwidth could be programmed from 90 kHz to 3 MHz.
{"title":"A programmable rail-to-rail constant-g/sub m/ input structure for LV amplifier","authors":"Shouli Yan, E. Sánchez-Sinencio","doi":"10.1109/ISCAS.2000.857543","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857543","url":null,"abstract":"We proposed a novel technique for low voltage rail-to-rail constant-g/sub m/ input stages, which does not depend on the operation regions of the MOS transistors. An op amp was designed to demonstrate the new idea using MOSIS AMJ 1.2 /spl mu/m technology. A 2.5 MHz unity-gain bandwidth with 61/spl deg/ phase margin was achieved when driving 10 k/spl Omega/ and 10 pF load, with 240 /spl mu/A current consumption and a power supply of 3 V. The g/sub m/ variation of the input stage is within /spl plusmn/3% from rail-to-rail. By changing the bias current, the unity-gain bandwidth could be programmed from 90 kHz to 3 MHz.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89451848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856334
W. Yung, Min Jian, Yew Wee Ho
Due to the relatively high data rate and the intensive filter operations involved, it is difficult to implement software defined radio functions on a general purpose processor for the channelizer in the base station receiver. This paper presents an efficient channelizer design based on the polyphase decomposition technique. The channelizer was modelled and comparison was made with conventional designs. In terms of the number of arithmetic operations per second, the new model had shown a 130/spl times/ improvement. This paper presents a more realistic outlook of the design improvement taking the algorithm complexities into account as well.
{"title":"Polyphase decomposition channelizers for software radios","authors":"W. Yung, Min Jian, Yew Wee Ho","doi":"10.1109/ISCAS.2000.856334","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856334","url":null,"abstract":"Due to the relatively high data rate and the intensive filter operations involved, it is difficult to implement software defined radio functions on a general purpose processor for the channelizer in the base station receiver. This paper presents an efficient channelizer design based on the polyphase decomposition technique. The channelizer was modelled and comparison was made with conventional designs. In terms of the number of arithmetic operations per second, the new model had shown a 130/spl times/ improvement. This paper presents a more realistic outlook of the design improvement taking the algorithm complexities into account as well.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89948073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.858679
Jeongnam Youn, Jun Xin, Ming-Ting Sun
In various networked multimedia applications, it is often necessary to change the bit-rate and format of a pre-encoded bit-stream. This can be achieved using a cascaded pixel-domain transcoder, which fully decodes an incoming bit-stream and then re-encodes the decoded pictures with the desired bit-rate or format. However, the cascaded pixel-domain transcoder is computationally expensive. To reduce the computations, several fast architectures have been proposed in the literature. However, these fast transcoder architectures introduce new limitations and are not drift-free. In this paper, we propose new techniques to implement a fast cascaded pixel-domain transcoder. We further discuss the limitation and speed of the different transcoder architectures. We also discuss the methods for adding watermark or company logo, using the different transcoder architectures.
{"title":"Fast video transcoding architectures for networked multimedia applications","authors":"Jeongnam Youn, Jun Xin, Ming-Ting Sun","doi":"10.1109/ISCAS.2000.858679","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.858679","url":null,"abstract":"In various networked multimedia applications, it is often necessary to change the bit-rate and format of a pre-encoded bit-stream. This can be achieved using a cascaded pixel-domain transcoder, which fully decodes an incoming bit-stream and then re-encodes the decoded pictures with the desired bit-rate or format. However, the cascaded pixel-domain transcoder is computationally expensive. To reduce the computations, several fast architectures have been proposed in the literature. However, these fast transcoder architectures introduce new limitations and are not drift-free. In this paper, we propose new techniques to implement a fast cascaded pixel-domain transcoder. We further discuss the limitation and speed of the different transcoder architectures. We also discuss the methods for adding watermark or company logo, using the different transcoder architectures.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89531017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856155
D. Blank, A. Kern, R. Stoop
We describe a novel type of bursting that we observe in simulations of large recurrent networks of biophysically plausible, intrinsically non-bursting neurons. The mechanism responsible for the bursting is a combination of excitatory feedback received from neighbouring neurons, together with an activity-dependent adaptation mechanism that slows down spiking. This collective bursting is shown to encode external inputs in the intervals between bursts. The interspike intervals during each burst are irregular and have a high output rate that is insensitive to the input strength. The encoding is reliable and precise, even when individual neurons have imperfect, varying properties and is robust to failure of large numbers of neurons.
{"title":"Robust encoding by collective bursting in biologically plausible neural networks","authors":"D. Blank, A. Kern, R. Stoop","doi":"10.1109/ISCAS.2000.856155","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856155","url":null,"abstract":"We describe a novel type of bursting that we observe in simulations of large recurrent networks of biophysically plausible, intrinsically non-bursting neurons. The mechanism responsible for the bursting is a combination of excitatory feedback received from neighbouring neurons, together with an activity-dependent adaptation mechanism that slows down spiking. This collective bursting is shown to encode external inputs in the intervals between bursts. The interspike intervals during each burst are irregular and have a high output rate that is insensitive to the input strength. The encoding is reliable and precise, even when individual neurons have imperfect, varying properties and is robust to failure of large numbers of neurons.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89581647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.858843
E. Peralías, A. Acosta, A. Rueda, J. Huertas
This paper proposes a behavioural model for digitally corrected/calibrated pipeline A/D converters (ADCs) based on standard VHDL. We will show how VHDL-based analog modelling can be efficiently used to simulate and verify the functionality of these mixed-signal systems where significant interaction exists between analog and digital parts. The main motivation for describing the behavioural model (analog and digital) directly in standard VHDL is to make possible the synthesis and fault simulation of the digital part using standard digital tools. Results from simulations carried out using QuickHDL in Mentor-Graphics prove the feasibility of the approach and are in agreement with those obtained experimentally from a Silicon prototype.
{"title":"VHDL-based behavioural description of pipeline ADCs","authors":"E. Peralías, A. Acosta, A. Rueda, J. Huertas","doi":"10.1109/ISCAS.2000.858843","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.858843","url":null,"abstract":"This paper proposes a behavioural model for digitally corrected/calibrated pipeline A/D converters (ADCs) based on standard VHDL. We will show how VHDL-based analog modelling can be efficiently used to simulate and verify the functionality of these mixed-signal systems where significant interaction exists between analog and digital parts. The main motivation for describing the behavioural model (analog and digital) directly in standard VHDL is to make possible the synthesis and fault simulation of the digital part using standard digital tools. Results from simulations carried out using QuickHDL in Mentor-Graphics prove the feasibility of the approach and are in agreement with those obtained experimentally from a Silicon prototype.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89600963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857184
C. Tse, Y. Lai
This paper reexamines the conventional current-mode control strategy as applied to DC/DC converters in the light of "avoiding bifurcation". This alternative viewpoint permits convenient selection of parameter values to guarantee stable operation. Slope compensation is viewed as a means to keep the system sufficiently remote from the first bifurcation point. It is shown that excessive bifurcation clearance is accompanied by undesirably slow dynamical response. A variable ramp compensation is proposed to dynamically adjust the slope magnitude such that the system is kept clear of bifurcation yet responds sufficiently fast during transients.
{"title":"Control of bifurcation in current-programmed DC/DC converters: a reexamination of slope compensation","authors":"C. Tse, Y. Lai","doi":"10.1109/ISCAS.2000.857184","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857184","url":null,"abstract":"This paper reexamines the conventional current-mode control strategy as applied to DC/DC converters in the light of \"avoiding bifurcation\". This alternative viewpoint permits convenient selection of parameter values to guarantee stable operation. Slope compensation is viewed as a means to keep the system sufficiently remote from the first bifurcation point. It is shown that excessive bifurcation clearance is accompanied by undesirably slow dynamical response. A variable ramp compensation is proposed to dynamically adjust the slope magnitude such that the system is kept clear of bifurcation yet responds sufficiently fast during transients.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89629481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856015
F. Eberhardt, W. Tenten, P. Shepherd
This paper presents a new effective method for symbolic sensitivity analysis of large scale analogue circuits. Based on the "sequence of expressions" (SOE) approach the sensitivities with respect to all parameters are calculated in parallel. Experimental results show that a significant acceleration compared to previously described symbolic procedures is achieved and that the method can be faster than the numerical adjoint approach.
{"title":"Parallel symbolic sensitivity analysis of large-scale linear analogue circuits","authors":"F. Eberhardt, W. Tenten, P. Shepherd","doi":"10.1109/ISCAS.2000.856015","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856015","url":null,"abstract":"This paper presents a new effective method for symbolic sensitivity analysis of large scale analogue circuits. Based on the \"sequence of expressions\" (SOE) approach the sensitivities with respect to all parameters are calculated in parallel. Experimental results show that a significant acceleration compared to previously described symbolic procedures is achieved and that the method can be faster than the numerical adjoint approach.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89704768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856066
J. A. Bragg, R. Harrison, P. Hasler, S. DeWeerth
The complexity of analog VLSI systems is often limited by the number of pins on a chip rather than by the die area. Currently, many analog parameters and biases are stored off chip. Moving parameter storage on chip could save pins and allow us to create complex programmable analog systems. In this paper, we present a design for an on-chip non-volatile analog memory cell that can be configured in addressable arrays and programmed easily. We use floating-gate MOS transistors to store charge, and we use the processes of tunneling and pFET hot-electron injection to program values. With these designs, we achieve greater than 13-bit output precision with a 39 dB power supply rejection ratio and no crosstalk between memory cells.
{"title":"A floating-gate pFET based CMOS programmable analog memory cell array","authors":"J. A. Bragg, R. Harrison, P. Hasler, S. DeWeerth","doi":"10.1109/ISCAS.2000.856066","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856066","url":null,"abstract":"The complexity of analog VLSI systems is often limited by the number of pins on a chip rather than by the die area. Currently, many analog parameters and biases are stored off chip. Moving parameter storage on chip could save pins and allow us to create complex programmable analog systems. In this paper, we present a design for an on-chip non-volatile analog memory cell that can be configured in addressable arrays and programmed easily. We use floating-gate MOS transistors to store charge, and we use the processes of tunneling and pFET hot-electron injection to program values. With these designs, we achieve greater than 13-bit output precision with a 39 dB power supply rejection ratio and no crosstalk between memory cells.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90331120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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