Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857084
S. Sutikno, A. Surya
The elliptic curves cryptosystem is a public key cryptosystem which has the potential to become the dominant encryption method for information and communication systems. This cryptosystem has the same security level compared with other public key cryptosystems, in spite of the relatively short key length that is employed. A short key length makes the encryption and decryption process much faster, requires a lower bandwidth for data and provides a more efficient implementation. An implementation of the elliptic curves cryptosystem needs a high performance finite field arithmetic module. In this paper we discuss an architecture of a finite field F(2/sup 2n/) multiplier using normal basis representations. The proposed architecture offers lower computational time and lower complexity compared with other architectures.
{"title":"An architecture of F(2/sup 2N/) multiplier for elliptic curves cryptosystem","authors":"S. Sutikno, A. Surya","doi":"10.1109/ISCAS.2000.857084","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857084","url":null,"abstract":"The elliptic curves cryptosystem is a public key cryptosystem which has the potential to become the dominant encryption method for information and communication systems. This cryptosystem has the same security level compared with other public key cryptosystems, in spite of the relatively short key length that is employed. A short key length makes the encryption and decryption process much faster, requires a lower bandwidth for data and provides a more efficient implementation. An implementation of the elliptic curves cryptosystem needs a high performance finite field arithmetic module. In this paper we discuss an architecture of a finite field F(2/sup 2n/) multiplier using normal basis representations. The proposed architecture offers lower computational time and lower complexity compared with other architectures.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77579350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857016
Shugang Wei, K. Shimizu
A new concept on residue arithmetic using a radix-2 signed-digit (SD) number representation is presented, by which memoryless residue arithmetic circuits using SD adders can be implemented. For a given modulus m, 2/sup p/-1/spl les/m/spl les/2/sup p/+2/sup p-1/-1, in a residue number system (RNS), the modulo m addition is performed by using two p-digit SD adders. Thus, the module m addition time is independent of the word length of operands. When m=2/sup p/ or m=2/sup p//spl plusmn/1, especially, the module m addition is implemented by only using one SD adder. Moreover, a module m multiplier can be constructed using a binary modulo m SD adder tree, so that the modulo m multiplication can be performed in a time proportional to log/sub 2/p.
{"title":"Residue arithmetic circuits using a signed-digit number representation","authors":"Shugang Wei, K. Shimizu","doi":"10.1109/ISCAS.2000.857016","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857016","url":null,"abstract":"A new concept on residue arithmetic using a radix-2 signed-digit (SD) number representation is presented, by which memoryless residue arithmetic circuits using SD adders can be implemented. For a given modulus m, 2/sup p/-1/spl les/m/spl les/2/sup p/+2/sup p-1/-1, in a residue number system (RNS), the modulo m addition is performed by using two p-digit SD adders. Thus, the module m addition time is independent of the word length of operands. When m=2/sup p/ or m=2/sup p//spl plusmn/1, especially, the module m addition is implemented by only using one SD adder. Moreover, a module m multiplier can be constructed using a binary modulo m SD adder tree, so that the modulo m multiplication can be performed in a time proportional to log/sub 2/p.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79759017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857206
Chulwoo Kim, Seong-ook Jung, K. Baek, S. Kang
In this paper, we describe parallel dynamic logic (PDL) which exhibits high speed and no charge sharing problem. PDL uses only parallel-connected transistors for logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias effect compared to other logic styles which use stacked transistors. Furthermore, PDL needs no signal ordering nor tapering. PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without area penalty due to logic duplication. Our experimental results on two 32-bit carry look ahead adders using 0.25 /spl mu/m CMOS technology showed that PDL with speed-enhanced skewed static (SSS) logic improves performance over clock-delayed (CD)-domino by 15-27% and power delay by 20-37%.
{"title":"Parallel dynamic logic (PDL) with speed-enhanced skewed static (SSS) logic","authors":"Chulwoo Kim, Seong-ook Jung, K. Baek, S. Kang","doi":"10.1109/ISCAS.2000.857206","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857206","url":null,"abstract":"In this paper, we describe parallel dynamic logic (PDL) which exhibits high speed and no charge sharing problem. PDL uses only parallel-connected transistors for logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias effect compared to other logic styles which use stacked transistors. Furthermore, PDL needs no signal ordering nor tapering. PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without area penalty due to logic duplication. Our experimental results on two 32-bit carry look ahead adders using 0.25 /spl mu/m CMOS technology showed that PDL with speed-enhanced skewed static (SSS) logic improves performance over clock-delayed (CD)-domino by 15-27% and power delay by 20-37%.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80079246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.858702
T. Tarim, M. Ismail
The statistical design of the four-MOSFET structure and the 10-bit current division network is presented in this paper. The quantitative measure of the effect of mismatch between the transistors in both circuits is provided. Optimization of transistor W and L values, and yield enhancement are demonstrated. The circuits are fabricated through the MOSIS 2 /spl mu/m process using MOS transistor Level-3 model parameters. The experimental results are included in the paper.
{"title":"Application of a statistical design methodology to low voltage analog MOS integrated circuits","authors":"T. Tarim, M. Ismail","doi":"10.1109/ISCAS.2000.858702","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.858702","url":null,"abstract":"The statistical design of the four-MOSFET structure and the 10-bit current division network is presented in this paper. The quantitative measure of the effect of mismatch between the transistors in both circuits is provided. Optimization of transistor W and L values, and yield enhancement are demonstrated. The circuits are fabricated through the MOSIS 2 /spl mu/m process using MOS transistor Level-3 model parameters. The experimental results are included in the paper.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79140469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856085
M. Laiho, A. Paasio, K. Halonen
In this paper the design issues of large globally connected compact neural networks are targeted. Building blocks of a cell that is capable of performing the hardware annealing function are designed. Different offset compensation schemes are used to eliminate the offset currents. The cell is designed to have voltage outputs to facilitate the interconnecting of cells. The blocks are processed with a 0.5 /spl mu/m standard digital CMOS process and measurement results of selected building blocks of the cell are included.
{"title":"Building blocks for large annealed compact neural networks","authors":"M. Laiho, A. Paasio, K. Halonen","doi":"10.1109/ISCAS.2000.856085","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856085","url":null,"abstract":"In this paper the design issues of large globally connected compact neural networks are targeted. Building blocks of a cell that is capable of performing the hardware annealing function are designed. Different offset compensation schemes are used to eliminate the offset currents. The cell is designed to have voltage outputs to facilitate the interconnecting of cells. The blocks are processed with a 0.5 /spl mu/m standard digital CMOS process and measurement results of selected building blocks of the cell are included.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79297802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.858783
Y. Andreyev, A. Dmitriev, E. Efremova
In this report we discuss the problem of separating the sum of chaotic signals into the individual components with a procedure of backward iteration of the mapping equations describing the chaotic sources. We show that the proposed approach has good stability in respect to additive external noise.
{"title":"Multiplexing chaotic signals in the presence of noise","authors":"Y. Andreyev, A. Dmitriev, E. Efremova","doi":"10.1109/ISCAS.2000.858783","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.858783","url":null,"abstract":"In this report we discuss the problem of separating the sum of chaotic signals into the individual components with a procedure of backward iteration of the mapping equations describing the chaotic sources. We show that the proposed approach has good stability in respect to additive external noise.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81279883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857438
Jye-Jong Leu, A. Wu
In this paper, a design methodology for the design of a Montgomery module is proposed. We summarize the result in pseudo C-like codes and call it Booth-encoded Montgomery modular multiplication algorithm. Using this algorithm, iteration number is reduced to about n/2 in each Montgomery operation. In addition, we apply the folding and unfolding techniques to shorten the critical path. Finally, we propose the 4 bit-digit-serial pipelined architecture to process RSA encryption/decryption in a more efficient way. The speed of the proposed algorithm is approximately 1.7 times that of most RSA VLSI designs based on original Montgomery modular multiplication algorithm.
{"title":"Design methodology for Booth-encoded Montgomery module design for RSA cryptosystem","authors":"Jye-Jong Leu, A. Wu","doi":"10.1109/ISCAS.2000.857438","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857438","url":null,"abstract":"In this paper, a design methodology for the design of a Montgomery module is proposed. We summarize the result in pseudo C-like codes and call it Booth-encoded Montgomery modular multiplication algorithm. Using this algorithm, iteration number is reduced to about n/2 in each Montgomery operation. In addition, we apply the folding and unfolding techniques to shorten the critical path. Finally, we propose the 4 bit-digit-serial pipelined architecture to process RSA encryption/decryption in a more efficient way. The speed of the proposed algorithm is approximately 1.7 times that of most RSA VLSI designs based on original Montgomery modular multiplication algorithm.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84239343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.855989
Chin-Hwa Kuo, Tzu-Chuan Chou, Tay-Shen Wang
An efficient spatial prediction-based progressive image compression scheme is developed in this paper. The proposed scheme consists of two phases, namely, the prediction phase and the quantization phase. In the prediction phase, information of the nearest neighbor pixels is utilized to predict the center pixel. Next in-place processes are taken, i.e., the resulting prediction error is stored in the same memory location as the predicted pixel. Thus, the temporary storage space required is significantly reduced in the encoding process as well as decoding process. The prediction scheme generates prediction error images with hierarchical structure, which can employ the result of many existing quantization schemes, such as EZW and SPIHT algorithms. As a result, a progressive coding feature is obtained in a straightforward manner. In the quantization phase, we extend the multilevel threshold scheme. Not only the pixel intensity value itself but also level significance is taken into account. In the experimental testing, we illustrate that the proposed scheme yields compression quality advantages. It outperforms several existing image compression schemes. Furthermore, the proposed scheme can be realized by only integer addition and shift operations. Tremendous amounts of computation-saving are achieved. The above features make the proposed image compression scheme beneficial to the areas of real-time applications and wireless transmission in limited bandwidth and low computation power environments.
{"title":"An efficient spatial prediction-based image compression scheme","authors":"Chin-Hwa Kuo, Tzu-Chuan Chou, Tay-Shen Wang","doi":"10.1109/ISCAS.2000.855989","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.855989","url":null,"abstract":"An efficient spatial prediction-based progressive image compression scheme is developed in this paper. The proposed scheme consists of two phases, namely, the prediction phase and the quantization phase. In the prediction phase, information of the nearest neighbor pixels is utilized to predict the center pixel. Next in-place processes are taken, i.e., the resulting prediction error is stored in the same memory location as the predicted pixel. Thus, the temporary storage space required is significantly reduced in the encoding process as well as decoding process. The prediction scheme generates prediction error images with hierarchical structure, which can employ the result of many existing quantization schemes, such as EZW and SPIHT algorithms. As a result, a progressive coding feature is obtained in a straightforward manner. In the quantization phase, we extend the multilevel threshold scheme. Not only the pixel intensity value itself but also level significance is taken into account. In the experimental testing, we illustrate that the proposed scheme yields compression quality advantages. It outperforms several existing image compression schemes. Furthermore, the proposed scheme can be realized by only integer addition and shift operations. Tremendous amounts of computation-saving are achieved. The above features make the proposed image compression scheme beneficial to the areas of real-time applications and wireless transmission in limited bandwidth and low computation power environments.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84241683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857132
R. Chandramouli, V. Srikantam
Optimal probability model selection for power estimation in low power VLSI applications is studied. Akaike's information criterion is used to estimate the optimal number of components in a mixture density model for the simulated power data. Theory behind the proposed algorithm is discussed followed by experimental results for ISCAS '85 benchmark circuits and a large industrial circuit. The method is shown to perform well for both large and small circuits even when the number of observed samples is small. The algorithm is promising as a pre-processing step to automatically compute the optimal probability model before any other power estimation procedure is applied. We also note that the method is applicable to other problems in VLSI for model selection.
{"title":"Optimum probability model selection using Akaike's information criterion for low power applications","authors":"R. Chandramouli, V. Srikantam","doi":"10.1109/ISCAS.2000.857132","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857132","url":null,"abstract":"Optimal probability model selection for power estimation in low power VLSI applications is studied. Akaike's information criterion is used to estimate the optimal number of components in a mixture density model for the simulated power data. Theory behind the proposed algorithm is discussed followed by experimental results for ISCAS '85 benchmark circuits and a large industrial circuit. The method is shown to perform well for both large and small circuits even when the number of observed samples is small. The algorithm is promising as a pre-processing step to automatically compute the optimal probability model before any other power estimation procedure is applied. We also note that the method is applicable to other problems in VLSI for model selection.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84285100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856270
A. Baranovski, A. Mögel, W. Schwarz, O. Woywode
Recent publications on DC-DC converters have pointed out that a chaotic operation mode may be of advantage for EMC reasons. This paper proposes a boost-converter scheme the switching operation of which is controlled by a chaotic return map. A spectral analysis of the converter's input current demonstrates how the shape of the return map affects the power density spectrum of the input current. This provides an approach to solve the design problem, i.e. to choose a return map in order to meet particular spectral demands. Finally a simple circuit solution for the chaotic control of the converter is proposed.
{"title":"Chaotic control of a DC-DC-converter","authors":"A. Baranovski, A. Mögel, W. Schwarz, O. Woywode","doi":"10.1109/ISCAS.2000.856270","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856270","url":null,"abstract":"Recent publications on DC-DC converters have pointed out that a chaotic operation mode may be of advantage for EMC reasons. This paper proposes a boost-converter scheme the switching operation of which is controlled by a chaotic return map. A spectral analysis of the converter's input current demonstrates how the shape of the return map affects the power density spectrum of the input current. This provides an approach to solve the design problem, i.e. to choose a return map in order to meet particular spectral demands. Finally a simple circuit solution for the chaotic control of the converter is proposed.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84391391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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