Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857069
W. Lie, Guo-Shiang Lin, Chih-Liang Wu, Ta-Chun Wang
This paper proposes two simple DCT-domain-based schemes to embed single or multiple watermarks into an image for copyright protection and data monitoring and tracking. The watermark data are essentially embedded in the middle band of the DCT domain to make a tradeoff between visual degradation and robustness. The proposed schemes are simple and no original host image is required for watermark extraction. The algorithm also features the capability of embedding multiple orthogonal watermarks into an image simultaneously. A set of systematic experiments, including Gaussian smoothing, JPEG compression, and image cropping are performed to prove the robustness of our algorithms.
{"title":"Robust image watermarking on the DCT domain","authors":"W. Lie, Guo-Shiang Lin, Chih-Liang Wu, Ta-Chun Wang","doi":"10.1109/ISCAS.2000.857069","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857069","url":null,"abstract":"This paper proposes two simple DCT-domain-based schemes to embed single or multiple watermarks into an image for copyright protection and data monitoring and tracking. The watermark data are essentially embedded in the middle band of the DCT domain to make a tradeoff between visual degradation and robustness. The proposed schemes are simple and no original host image is required for watermark extraction. The algorithm also features the capability of embedding multiple orthogonal watermarks into an image simultaneously. A set of systematic experiments, including Gaussian smoothing, JPEG compression, and image cropping are performed to prove the robustness of our algorithms.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72749706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856081
En-Cheng Liu, Tu-Hsing Lin, Ting-Chi Wang
Recently Young and Wong extended the well-known simulated annealing based Wong-Liu algorithm [1986] to solve the problem of slicing floorplan design with boundary constraints. The main idea behind the Young-Wong algorithm [1999] is to determine the boundary information of each module in a floorplan by traversing the corresponding normalized Polish expression from right to left once. By carefully examining each of the three types of moves adopted by the Young-Wong algorithm for generating a new normalized Polish expression, we observe that it is very likely that only a subset of modules might have the boundary information changed in the new normalized Polish expression, and hence only the boundary information for those modules needs to be recomputed. Based on the observation, we improve the Young-Wong algorithm by providing methods to accelerate the boundary information computation.
{"title":"On accelerating slicing floorplan design with boundary constraints","authors":"En-Cheng Liu, Tu-Hsing Lin, Ting-Chi Wang","doi":"10.1109/ISCAS.2000.856081","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856081","url":null,"abstract":"Recently Young and Wong extended the well-known simulated annealing based Wong-Liu algorithm [1986] to solve the problem of slicing floorplan design with boundary constraints. The main idea behind the Young-Wong algorithm [1999] is to determine the boundary information of each module in a floorplan by traversing the corresponding normalized Polish expression from right to left once. By carefully examining each of the three types of moves adopted by the Young-Wong algorithm for generating a new normalized Polish expression, we observe that it is very likely that only a subset of modules might have the boundary information changed in the new normalized Polish expression, and hence only the boundary information for those modules needs to be recomputed. Based on the observation, we improve the Young-Wong algorithm by providing methods to accelerate the boundary information computation.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74423599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857190
Y. Bruck, M. Zelikson, G. Burdo
We report on a novel approach for the linearization of current mode amplifiers. We present the design and tuning procedure outline and then illustrate it by the design of a transconductor amplifier. The amplifier is implemented in the IBM SiGe BiCMOS technology and it features second and third harmonic suppression of about 100 dB respectively at signal-to-bias ratio of 1 (simulation results). Although the procedure is demonstrated on a particular example, it is applicable to a wide class of current mode amplifiers.
{"title":"Novel design technique for highly linear current mode amplifiers. Analysis, design, simulations","authors":"Y. Bruck, M. Zelikson, G. Burdo","doi":"10.1109/ISCAS.2000.857190","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857190","url":null,"abstract":"We report on a novel approach for the linearization of current mode amplifiers. We present the design and tuning procedure outline and then illustrate it by the design of a transconductor amplifier. The amplifier is implemented in the IBM SiGe BiCMOS technology and it features second and third harmonic suppression of about 100 dB respectively at signal-to-bias ratio of 1 (simulation results). Although the procedure is demonstrated on a particular example, it is applicable to a wide class of current mode amplifiers.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78450489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857391
F. Muñoz, A. Torralba, R. Carvajal, J. Ramírez-Angulo
Two new CMOS low-voltage linear transconductors for High Frequency (HF) applications are presented. They use tunable floating voltage sources between the input and the transistor gates of each inverter that forms the transconductor proposed by Nauta (1992). Two implementations of the floating batteries are presented. The proposed transconductors operate under constant low voltage supply as low as 1.2 V and transconductance and output resistance are independently tunable. It is suitable to be used in HF continuous time filters with programmable center frequency and quality factor. To this end, simulation results of a 10.7 MHz band-pass g/sub m/-C filter operating at a voltage supply of 1.5 V and large input swing are presented.
{"title":"Two new VHF tunable CMOS low-voltage linear transconductors and their application to HF GM-C filter design","authors":"F. Muñoz, A. Torralba, R. Carvajal, J. Ramírez-Angulo","doi":"10.1109/ISCAS.2000.857391","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857391","url":null,"abstract":"Two new CMOS low-voltage linear transconductors for High Frequency (HF) applications are presented. They use tunable floating voltage sources between the input and the transistor gates of each inverter that forms the transconductor proposed by Nauta (1992). Two implementations of the floating batteries are presented. The proposed transconductors operate under constant low voltage supply as low as 1.2 V and transconductance and output resistance are independently tunable. It is suitable to be used in HF continuous time filters with programmable center frequency and quality factor. To this end, simulation results of a 10.7 MHz band-pass g/sub m/-C filter operating at a voltage supply of 1.5 V and large input swing are presented.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75019983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857583
N. Tomabechi, T. Ito
This paper proposes a design method of a high-speed RSA encryption processor in which the residue calculation of the redundant binary numbers is realized by table-look-up method where the table is built in the hardware, It is demonstrated that the number of gates through the critical path determining the operation speed of the proposed processor is 1/62 that of the conventional processors.
{"title":"Design of a high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers","authors":"N. Tomabechi, T. Ito","doi":"10.1109/ISCAS.2000.857583","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857583","url":null,"abstract":"This paper proposes a design method of a high-speed RSA encryption processor in which the residue calculation of the redundant binary numbers is realized by table-look-up method where the table is built in the hardware, It is demonstrated that the number of gates through the critical path determining the operation speed of the proposed processor is 1/62 that of the conventional processors.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75042176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856026
A. Doboli, N. Dhanwada, R. Vemuri
This paper presents a heuristic technique for automatically generating different architectures for an analog system. The AG iteratively produces various system net-lists as distinct implementations can realize the signal processing and flow in a system. Area and power for resulting net-lists are rapidly evaluated with High-Level Performance Estimator (HPE), a simplified estimation module. The AG algorithm is simple to implement. It does not require an extensive pattern library as traditional AG techniques do.
{"title":"A heuristic technique for system-level architecture generation from signal-flow graph representations of analog systems","authors":"A. Doboli, N. Dhanwada, R. Vemuri","doi":"10.1109/ISCAS.2000.856026","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856026","url":null,"abstract":"This paper presents a heuristic technique for automatically generating different architectures for an analog system. The AG iteratively produces various system net-lists as distinct implementations can realize the signal processing and flow in a system. Area and power for resulting net-lists are rapidly evaluated with High-Level Performance Estimator (HPE), a simplified estimation module. The AG algorithm is simple to implement. It does not require an extensive pattern library as traditional AG techniques do.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75073611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856399
M. Wróblewski, S. Simon, J. Nossek
Datapath architectures exhibit a large amount of undesired switching (glitches) which does not contribute to the functionality but leads to increased power consumption. While glitch propagation can be effectively reduced by pipelining circuits with acyclic SFGs, this technique is not directly applicable if the circuit contains loops. The paper addresses this problem and discusses a methodology for reducing switching activity in recursive circuits. Simulation results of a few example circuits are given.
{"title":"Low power transformation of datapath architectures with cyclic SFGs","authors":"M. Wróblewski, S. Simon, J. Nossek","doi":"10.1109/ISCAS.2000.856399","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856399","url":null,"abstract":"Datapath architectures exhibit a large amount of undesired switching (glitches) which does not contribute to the functionality but leads to increased power consumption. While glitch propagation can be effectively reduced by pipelining circuits with acyclic SFGs, this technique is not directly applicable if the circuit contains loops. The paper addresses this problem and discusses a methodology for reducing switching activity in recursive circuits. Simulation results of a few example circuits are given.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72622907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857126
Jen-Shiun Chiang, M. Chiang
An experimental low-voltage low-power pipelined analog-to-digital converter is designed and presented in this paper. The power consumption is efficiently reduced by using switched operational amplifiers and dynamic comparators. This chip is designed in a 0.35 /spl mu/m CMOS process. The core area occupies 1450 /spl mu/m/spl times/1100 /spl mu/m. The HSPICE simulation results show that the resolution of this design is 10-bit; the sampling rate is 10 MHz; the peak SNDR is 66 dB, and the power consumption is 15 mW at 1.5 V supply voltage.
{"title":"The design of a 1.5 V, 10-bit, 10 M samples/s low power pipelined analog-to-digital converter","authors":"Jen-Shiun Chiang, M. Chiang","doi":"10.1109/ISCAS.2000.857126","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857126","url":null,"abstract":"An experimental low-voltage low-power pipelined analog-to-digital converter is designed and presented in this paper. The power consumption is efficiently reduced by using switched operational amplifiers and dynamic comparators. This chip is designed in a 0.35 /spl mu/m CMOS process. The core area occupies 1450 /spl mu/m/spl times/1100 /spl mu/m. The HSPICE simulation results show that the resolution of this design is 10-bit; the sampling rate is 10 MHz; the peak SNDR is 66 dB, and the power consumption is 15 mW at 1.5 V supply voltage.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77373330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857115
K. Gałkowski, E. Rogers, A. Gramacki, J. Gramacki, D. Owens
Linear repetitive processes are a distinct class of 2D linear systems of both theoretical and practical interest. The stability theory for these processes currently consists of two distinct concepts termed asymptotic stability and stability along the pass respectively where the former is a necessary condition for the latter. Recently applications have arisen where asymptotic stability is too weak and stability along the pass is too strong for meaningful progress to be made. This paper develops the concept of strong practical stability for such cases.
{"title":"Strong practical stability for a class of 2D linear systems","authors":"K. Gałkowski, E. Rogers, A. Gramacki, J. Gramacki, D. Owens","doi":"10.1109/ISCAS.2000.857115","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857115","url":null,"abstract":"Linear repetitive processes are a distinct class of 2D linear systems of both theoretical and practical interest. The stability theory for these processes currently consists of two distinct concepts termed asymptotic stability and stability along the pass respectively where the former is a necessary condition for the latter. Recently applications have arisen where asymptotic stability is too weak and stability along the pass is too strong for meaningful progress to be made. This paper develops the concept of strong practical stability for such cases.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77397118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856103
F. Komatsu, H. Torikai, Toshimichi Saito
This paper presents N binary hysteresis relaxation oscillators connected by the intermittently coupled capacitors. The network exhibits various interesting synchronous phenomena. As a powerful analysis tool, we derive a hybrid return map which has one real and N binary states. Using this map, the stability of the periodic synchronization can be analyzed simply by the binary states: it is not necessary to check the real state. Then we classify basic phenomena in a bifurcation diagram. Typical phenomena are verified in the laboratory.
{"title":"A network of relaxation oscillators based on intermittently coupled capacitors","authors":"F. Komatsu, H. Torikai, Toshimichi Saito","doi":"10.1109/ISCAS.2000.856103","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856103","url":null,"abstract":"This paper presents N binary hysteresis relaxation oscillators connected by the intermittently coupled capacitors. The network exhibits various interesting synchronous phenomena. As a powerful analysis tool, we derive a hybrid return map which has one real and N binary states. Using this map, the stability of the periodic synchronization can be analyzed simply by the binary states: it is not necessary to check the real state. Then we classify basic phenomena in a bifurcation diagram. Typical phenomena are verified in the laboratory.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77481373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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