Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328963
A. Hafez, W.F. Aboueldahab, A. Helmy
Issues associated with the system design of an offset phase locked modulation loop (OPLL) are presented in this paper. The sources of spurs within the loop are all explained in detail. In order to meet the transmission mask stringent requirements for the EGSM band, a criteria for choosing the IF frequency is presented. Additionally, the paper gives the design procedures for calculating the required suppression of the offset mixer spurious signals by the offset mixer and feed back filter with respect to the IF signal.
{"title":"On the design of an offset-PLL modulation loop for the EGSM band","authors":"A. Hafez, W.F. Aboueldahab, A. Helmy","doi":"10.1109/ISCAS.2004.1328963","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328963","url":null,"abstract":"Issues associated with the system design of an offset phase locked modulation loop (OPLL) are presented in this paper. The sources of spurs within the loop are all explained in detail. In order to meet the transmission mask stringent requirements for the EGSM band, a criteria for choosing the IF frequency is presented. Additionally, the paper gives the design procedures for calculating the required suppression of the offset mixer spurious signals by the offset mixer and feed back filter with respect to the IF signal.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"273 1","pages":"IV-153"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73415370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328903
Chang-Su Kim, Sang Uk Lee
An effective method to reduce gray level disturbances in plasma display panels (PDPs) is proposed in this work. First, we develop a systematic model for gray level disturbances, which occur when PDPs display moving image sequences. Then, we derive an ideal condition for the disturbances removal. Based on the condition, we propose the optimal subfield and driving vectors to minimize the disturbances. Simulation results show that the proposed algorithm provides a good moving image quality.
{"title":"Reduction of gray level disturbances in plasma display panels","authors":"Chang-Su Kim, Sang Uk Lee","doi":"10.1109/ISCAS.2004.1328903","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328903","url":null,"abstract":"An effective method to reduce gray level disturbances in plasma display panels (PDPs) is proposed in this work. First, we develop a systematic model for gray level disturbances, which occur when PDPs display moving image sequences. Then, we derive an ideal condition for the disturbances removal. Based on the condition, we propose the optimal subfield and driving vectors to minimize the disturbances. Simulation results show that the proposed algorithm provides a good moving image quality.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"110 1","pages":"III-941"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76741434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328854
Wei-Ying Kung, Hao-Song Kong, A. Vetro, Huifang Sun
Two error resilient approaches are proposed respectively, to replenish intra and inter frame in this work. First we propose a spatial-domain error concealment method to conceal corrupted still images and intra-coded (I) frames. It can recursively restore pixels from the previously concealed pixels, which are selected by a proposed evaluation method. In such method, object edges can be replenished with a low complexity. Second, we propose an error resilient approach for P-frame. With our proposed approach, only a small amount of side information is extracted and packed at the end of every frame. Decoder can easily restore motion vector from the side information for concealment. Experimental results show that the proposed algorithm can provide better visual quality in comparison with the existing approaches.
{"title":"Error resilient methods for real-time MPEG-4 video streaming","authors":"Wei-Ying Kung, Hao-Song Kong, A. Vetro, Huifang Sun","doi":"10.1109/ISCAS.2004.1328854","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328854","url":null,"abstract":"Two error resilient approaches are proposed respectively, to replenish intra and inter frame in this work. First we propose a spatial-domain error concealment method to conceal corrupted still images and intra-coded (I) frames. It can recursively restore pixels from the previously concealed pixels, which are selected by a proposed evaluation method. In such method, object edges can be replenished with a low complexity. Second, we propose an error resilient approach for P-frame. With our proposed approach, only a small amount of side information is extracted and packed at the end of every frame. Decoder can easily restore motion vector from the side information for concealment. Experimental results show that the proposed algorithm can provide better visual quality in comparison with the existing approaches.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"57 1","pages":"III-745"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82177229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328311
A. Tajalli, S. Mehrmanesh, S. M. Atarodi
An accurate and programmable CMOS duty-cycle control (DCC) circuit for high-speed applications is discussed. Proposed DCC circuit has a first order transfer function the accuracy of which is just limited by the on-chip device mismatch. Operating at 1GHz frequency, the duty-cycle of the output clock can be tuned between 45 to 60% by changing the charge and discharge currents of a charged-pump circuit (CPC). CPC's current is controlled through five controlling bits. The circuit is designed in a 0.18/spl mu/m CMOS technology and draws 160/spl mu/A from a 1.8V supply with less than 0.3/spl times/LSB error.
{"title":"A duty cycle control circuit for high speed applications","authors":"A. Tajalli, S. Mehrmanesh, S. M. Atarodi","doi":"10.1109/ISCAS.2004.1328311","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328311","url":null,"abstract":"An accurate and programmable CMOS duty-cycle control (DCC) circuit for high-speed applications is discussed. Proposed DCC circuit has a first order transfer function the accuracy of which is just limited by the on-chip device mismatch. Operating at 1GHz frequency, the duty-cycle of the output clock can be tuned between 45 to 60% by changing the charge and discharge currents of a charged-pump circuit (CPC). CPC's current is controlled through five controlling bits. The circuit is designed in a 0.18/spl mu/m CMOS technology and draws 160/spl mu/A from a 1.8V supply with less than 0.3/spl times/LSB error.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"14 1","pages":"I-781"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82561573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329947
Antonio Zorzano Martínez, Fernando Beltrán Blázquez, José Ramón Beltrán Blázquez
An inverter topology based on high frequency power conversion and sigma-delta modulation is proposed. Sigma-delta technique is particularly an attractive idea in audio power amplifying area. Analysis of this technique is presented. Power modulation is a way to obtain power amplifiers with better efficiency than conventional linear power amplifiers. A quasi-resonant converter with sigma-delta modulation input has been integrated to reduce switching losses, allowing high frequency operation. Audio power amplifier and isolated high power supply are integrated in one unit and analyzed. Simulations are performed to backup the analysis.
{"title":"A new topology for a sigma-delta audio power amplifier","authors":"Antonio Zorzano Martínez, Fernando Beltrán Blázquez, José Ramón Beltrán Blázquez","doi":"10.1109/ISCAS.2004.1329947","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329947","url":null,"abstract":"An inverter topology based on high frequency power conversion and sigma-delta modulation is proposed. Sigma-delta technique is particularly an attractive idea in audio power amplifying area. Analysis of this technique is presented. Power modulation is a way to obtain power amplifiers with better efficiency than conventional linear power amplifiers. A quasi-resonant converter with sigma-delta modulation input has been integrated to reduce switching losses, allowing high frequency operation. Audio power amplifier and isolated high power supply are integrated in one unit and analyzed. Simulations are performed to backup the analysis.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"34 1","pages":"V-V"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81455645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328726
V. Adrian, B. Gwee, J. Chang
In this paper, we propose a sampling process for low voltage (1.1V) power-critical low-distortion digital class D amplifiers. The sampling process combines first and second-order Lagrange interpolation techniques to effectively increase the sampling rate without the usual overheads. The computation is also simple. The complete class D amplifier features a very low power dissipation (58.8/spl mu/W), low total harmonic distortion (-85.6dB FS) and high signal-to-noise ratio (99dB FS). The power saving is /spl sim/21% and the THD is improved by 9.8dB FS compared to a design embodying only a first order sampling process. We also provide an analysis of the power dissipation of the load power.
{"title":"A novel combined first and second order Lagrange interpolation sampling process for a digital class D amplifier","authors":"V. Adrian, B. Gwee, J. Chang","doi":"10.1109/ISCAS.2004.1328726","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328726","url":null,"abstract":"In this paper, we propose a sampling process for low voltage (1.1V) power-critical low-distortion digital class D amplifiers. The sampling process combines first and second-order Lagrange interpolation techniques to effectively increase the sampling rate without the usual overheads. The computation is also simple. The complete class D amplifier features a very low power dissipation (58.8/spl mu/W), low total harmonic distortion (-85.6dB FS) and high signal-to-noise ratio (99dB FS). The power saving is /spl sim/21% and the THD is improved by 9.8dB FS compared to a design embodying only a first order sampling process. We also provide an analysis of the power dissipation of the load power.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"2007 1","pages":"III-233"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78653867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329469
Junjie Yang, S. Tan
The paper presents an approach to behavioural modelling of analog circuits by dynamic semi-symbolic analysis, where some circuit parameters are kept as symbols and the others are given as numeric values. Our new method is based on the determinant decision diagram (DDD) representation of small-signal characteristics of linear analog circuits. The basic idea is to dynamically reorder DDD vertices such that all the DDD vertices corresponding to symbolic parameters are separated from DDD vertices for numerical parameters. In this way, DDD sizes of symbolic portion of DDD can be significantly reduced by suppressing numerical DDD nodes. Our new approach is different from the existing MTDDD based semi-symbolic analysis method where reordering is done before DDD is constructed and DDD-based graph operations are still valid in the new method. The proposed dynamic ordering algorithm, which is based on swap of adjacent variables, also improves the existing DDD-based vertex sifting algorithm as no special sign rule is required after DDD vertices are swapped. Experimental results have demonstrated that the proposed dynamic semi-symbolic method leads to up to 30% symbolic DDD node reduction compared MTDDD method on real analog circuits and can be performed very efficiently.
{"title":"Behavioural modelling of analog circuits by dynamic semi-symbolic analysis","authors":"Junjie Yang, S. Tan","doi":"10.1109/ISCAS.2004.1329469","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329469","url":null,"abstract":"The paper presents an approach to behavioural modelling of analog circuits by dynamic semi-symbolic analysis, where some circuit parameters are kept as symbols and the others are given as numeric values. Our new method is based on the determinant decision diagram (DDD) representation of small-signal characteristics of linear analog circuits. The basic idea is to dynamically reorder DDD vertices such that all the DDD vertices corresponding to symbolic parameters are separated from DDD vertices for numerical parameters. In this way, DDD sizes of symbolic portion of DDD can be significantly reduced by suppressing numerical DDD nodes. Our new approach is different from the existing MTDDD based semi-symbolic analysis method where reordering is done before DDD is constructed and DDD-based graph operations are still valid in the new method. The proposed dynamic ordering algorithm, which is based on swap of adjacent variables, also improves the existing DDD-based vertex sifting algorithm as no special sign rule is required after DDD vertices are swapped. Experimental results have demonstrated that the proposed dynamic semi-symbolic method leads to up to 30% symbolic DDD node reduction compared MTDDD method on real analog circuits and can be performed very efficiently.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"53 1","pages":"V-V"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78840613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328796
J. Torres, M. R. Petraglia, R. Tenenbaum
In this paper, an efficient method for modeling head-related transfer functions (HRTFs) of an auralization system is presented. The proposed model is based on the decomposition of the impulse response of the HRTFs by wavelet transforms. Through an analysis of the HRTF energy content per subband it is shown how the model can be reduced without introducing considerable error in the magnitude and phase frequency responses. As a result of the proposed technique, the low-order model has approximately 30% of the number of coefficients of the original HRTF, which represents an important reduction in the computational cost of an auralization system implementation.
{"title":"Low-order modeling of head-related transfer functions using wavelet transforms","authors":"J. Torres, M. R. Petraglia, R. Tenenbaum","doi":"10.1109/ISCAS.2004.1328796","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328796","url":null,"abstract":"In this paper, an efficient method for modeling head-related transfer functions (HRTFs) of an auralization system is presented. The proposed model is based on the decomposition of the impulse response of the HRTFs by wavelet transforms. Through an analysis of the HRTF energy content per subband it is shown how the model can be reduced without introducing considerable error in the magnitude and phase frequency responses. As a result of the proposed technique, the low-order model has approximately 30% of the number of coefficients of the original HRTF, which represents an important reduction in the computational cost of an auralization system implementation.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"142 1","pages":"III-513"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78901571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329916
K. Cameron, A. Murray
Analogue VLSI can be used to implement spike timing dependent neuromorphic training algorithms. This work presents a circuitry that uses spike timing to "adapt out" the effects of device mismatch in such circuits. Simulation results for the circuit implemented in 0.35 /spl mu/m CMOS process are reported.
{"title":"Can spike timing dependent plasticity compensate for process mismatch in neuromorphic analogue VLSI?","authors":"K. Cameron, A. Murray","doi":"10.1109/ISCAS.2004.1329916","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329916","url":null,"abstract":"Analogue VLSI can be used to implement spike timing dependent neuromorphic training algorithms. This work presents a circuitry that uses spike timing to \"adapt out\" the effects of device mismatch in such circuits. Simulation results for the circuit implemented in 0.35 /spl mu/m CMOS process are reported.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"6 1","pages":"V-V"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76389044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328339
F. Rezaei, K. Martin
This paper describes the realization of isolated vertical npn transistors in generic CMOS technologies. An improved layout for these parasitic transistors is proposed. The electrical characteristics and modelling of the proposed device are presented. The design, realization, and fabrication of a high-speed open-loop preamplifier using these bipolar transistors are also presented. The preamplifier was found to have more than 1 GHz bandwidth as well as less than -35dB THD, as was verified using die-probe measurements. The amplifier achieved 10.4dB gain and a -9dBm IIP3. The collector-base and the collector-emitter breakdown voltages are 14.8V and 9V, respectively. The output impedance and noise characteristics are comparatively good. The measured current gains, on the order of 20, are less than what would be preferred, but not excessively so, and the unity-gain frequencies on the order of 4GHz, are much less than would be the case for a vertical npn in a typical BiCMOS process, but still are adequate for many applications.
{"title":"A poor man's BiCMOS using standard CMOS","authors":"F. Rezaei, K. Martin","doi":"10.1109/ISCAS.2004.1328339","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328339","url":null,"abstract":"This paper describes the realization of isolated vertical npn transistors in generic CMOS technologies. An improved layout for these parasitic transistors is proposed. The electrical characteristics and modelling of the proposed device are presented. The design, realization, and fabrication of a high-speed open-loop preamplifier using these bipolar transistors are also presented. The preamplifier was found to have more than 1 GHz bandwidth as well as less than -35dB THD, as was verified using die-probe measurements. The amplifier achieved 10.4dB gain and a -9dBm IIP3. The collector-base and the collector-emitter breakdown voltages are 14.8V and 9V, respectively. The output impedance and noise characteristics are comparatively good. The measured current gains, on the order of 20, are less than what would be preferred, but not excessively so, and the unity-gain frequencies on the order of 4GHz, are much less than would be the case for a vertical npn in a typical BiCMOS process, but still are adequate for many applications.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"8 1","pages":"I-893"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87657144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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