Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329500
M. Velev
The paper presents a collection of 20 benchmark suites with a total of 1,132 ISCAS Boolean formulas from formal verification of high-level microprocessors, including pipelined, superscalar, and VLIW models with exceptions, multicycle functional units, branch prediction, instruction queues, and register renaming. These benchmarks can be used in research on testing, logic synthesis and optimization, equivalence verification, decision diagrams, and Boolean satisfiability. The most complex formulas have more than 700,000 logic gates.
{"title":"A new generation of ISCAS benchmarks from formal verification of high-level microprocessors","authors":"M. Velev","doi":"10.1109/ISCAS.2004.1329500","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329500","url":null,"abstract":"The paper presents a collection of 20 benchmark suites with a total of 1,132 ISCAS Boolean formulas from formal verification of high-level microprocessors, including pipelined, superscalar, and VLIW models with exceptions, multicycle functional units, branch prediction, instruction queues, and register renaming. These benchmarks can be used in research on testing, logic synthesis and optimization, equivalence verification, decision diagrams, and Boolean satisfiability. The most complex formulas have more than 700,000 logic gates.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"11 1","pages":"V-V"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87705941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328149
O. Carnu, A. Leuciuc
Resistive networks can be used as spatial filters to average the random errors in arrays of analog cells, specifically for decreasing the offsets in flash and folding A/D converters. In this communication the critical conditions the averaging networks have to satisfy are pointed out and the optimal topology, order, and parameters of the resistive grids are identified for each of the two ADC architectures.
{"title":"Optimal offset averaging for flash and folding A/D converters","authors":"O. Carnu, A. Leuciuc","doi":"10.1109/ISCAS.2004.1328149","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328149","url":null,"abstract":"Resistive networks can be used as spatial filters to average the random errors in arrays of analog cells, specifically for decreasing the offsets in flash and folding A/D converters. In this communication the critical conditions the averaging networks have to satisfy are pointed out and the optimal topology, order, and parameters of the resistive grids are identified for each of the two ADC architectures.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"1 1","pages":"I-I"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88056146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329405
A. Fournaris, O. Koufopavlou
Finite Field arithmetic is becoming increasingly a very prominent solution for calculations in many applications. The most demanding Finite Field arithmetic operation is multiplication. In this paper two Finite Field multiplier architectures and VLSI implementations are proposed using the Montgomery Multiplication Algorithm. The first architecture (Folded) is optimized in order to minimize the silicon covered area (gate count) and the second (Pipelined) is optimized in order to reduce the multiplication time delay. Both architectures are measured in terms of gate count-chip covered area and multiplication time delay and have more than adequate results in comparison with other known multipliers.
{"title":"GF(2/sup K/) multipliers based on Montgomery Multiplication Algorithm","authors":"A. Fournaris, O. Koufopavlou","doi":"10.1109/ISCAS.2004.1329405","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329405","url":null,"abstract":"Finite Field arithmetic is becoming increasingly a very prominent solution for calculations in many applications. The most demanding Finite Field arithmetic operation is multiplication. In this paper two Finite Field multiplier architectures and VLSI implementations are proposed using the Montgomery Multiplication Algorithm. The first architecture (Folded) is optimized in order to minimize the silicon covered area (gate count) and the second (Pipelined) is optimized in order to reduce the multiplication time delay. Both architectures are measured in terms of gate count-chip covered area and multiplication time delay and have more than adequate results in comparison with other known multipliers.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"93 11 1","pages":"II-849"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87756549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328945
Yijun Li, M. Elassal, M. Bayoumi
Most of the current LDPC decoder VLSI architecture research focuses on increasing system throughput or reducing hardware implementation complexity, but neglects power consumption. In this paper, we analyze the power consumption of the (3,k)-regular LDPC decoder architecture. Our analysis shows that 95% of the power consumption is consumed in accessing the memory. A new architecture is proposed which reduces memory access, hence power consumption, without sacrificing the performance. Experimental results show reduction in the power consumption by 14% and lower hardware complexity without sacrificing the Bit-Error-Ratio performance compared to previous work.
{"title":"Power efficient architecture for (3,6)-regular low-density parity-check code decoder","authors":"Yijun Li, M. Elassal, M. Bayoumi","doi":"10.1109/ISCAS.2004.1328945","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328945","url":null,"abstract":"Most of the current LDPC decoder VLSI architecture research focuses on increasing system throughput or reducing hardware implementation complexity, but neglects power consumption. In this paper, we analyze the power consumption of the (3,k)-regular LDPC decoder architecture. Our analysis shows that 95% of the power consumption is consumed in accessing the memory. A new architecture is proposed which reduces memory access, hence power consumption, without sacrificing the performance. Experimental results show reduction in the power consumption by 14% and lower hardware complexity without sacrificing the Bit-Error-Ratio performance compared to previous work.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"18 1","pages":"IV-81"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88329490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329415
Chiu-Wah Ng, T. Ng, K. Yip
Hash algorithms are important components in many cryptographic applications and security protocol suites. In this paper, a unified architecture for MD5 and RIPEMD-160 hash algorithms is developed. These two algorithms are different in speed and security level. Therefore, a unified hardware design allows applications to switch from one algorithm to another based on different requirements. The architecture has been implemented using Altera's EPF10K50SBC356-1, providing a throughput over 200 Mbits/s for MD5 and 80 Mbits/s for RIPEMD-160 when operated at 26.66 MHz with a resource utilization of 1964LC.
{"title":"A unified architecture of MD5 and RIPEMD-160 hash algorithms","authors":"Chiu-Wah Ng, T. Ng, K. Yip","doi":"10.1109/ISCAS.2004.1329415","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329415","url":null,"abstract":"Hash algorithms are important components in many cryptographic applications and security protocol suites. In this paper, a unified architecture for MD5 and RIPEMD-160 hash algorithms is developed. These two algorithms are different in speed and security level. Therefore, a unified hardware design allows applications to switch from one algorithm to another based on different requirements. The architecture has been implemented using Altera's EPF10K50SBC356-1, providing a throughput over 200 Mbits/s for MD5 and 80 Mbits/s for RIPEMD-160 when operated at 26.66 MHz with a resource utilization of 1964LC.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"15 1","pages":"II-889"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88403873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328727
G. Antoniou, M. T. Michael
In this paper the discrete Fourier transform is used to determine the coefficients of a transfer function of a new two-dimensional system model of second-order: x(i/sub 1/ + 2, i/sub 2/ + 2) = A/sub 0/x(i/sub 1/ + 1, i/sub 2/ + 1) + A/sub 1/x(i/sub 1/ + 1, i/sub 2/) + A/sub 2/x(i/sub 1/, i/sub 2/ + 1). The algorithm is straight forward and has been implemented using the software package "Matlab/spl trade/". A step-by-step example illustrating the application of the algorithm is presented.
{"title":"Computing the transfer function for second-order 2D systems","authors":"G. Antoniou, M. T. Michael","doi":"10.1109/ISCAS.2004.1328727","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328727","url":null,"abstract":"In this paper the discrete Fourier transform is used to determine the coefficients of a transfer function of a new two-dimensional system model of second-order: x(i/sub 1/ + 2, i/sub 2/ + 2) = A/sub 0/x(i/sub 1/ + 1, i/sub 2/ + 1) + A/sub 1/x(i/sub 1/ + 1, i/sub 2/) + A/sub 2/x(i/sub 1/, i/sub 2/ + 1). The algorithm is straight forward and has been implemented using the software package \"Matlab/spl trade/\". A step-by-step example illustrating the application of the algorithm is presented.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"90 1","pages":"III-237"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86222801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329069
L. Kocarev, Marjan Sterjev, P. Amato
We propose a public-key encryption algorithm based on torus automorphisms, which is secure, practical, and can be used for both encryption and digital signature. Software implementation and properties of the algorithm are discussed in detail. We show that our algorithm is as secure as RSA algorithm. In this paper we have generalized RSA algorithm replacing powers with matrix powers, choosing the matrix to be a matrix which defines a two-torus automorphisms, an example of strongly chaotic system.
{"title":"RSA encryption algorithm based on torus automorphisms","authors":"L. Kocarev, Marjan Sterjev, P. Amato","doi":"10.1109/ISCAS.2004.1329069","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329069","url":null,"abstract":"We propose a public-key encryption algorithm based on torus automorphisms, which is secure, practical, and can be used for both encryption and digital signature. Software implementation and properties of the algorithm are discussed in detail. We show that our algorithm is as secure as RSA algorithm. In this paper we have generalized RSA algorithm replacing powers with matrix powers, choosing the matrix to be a matrix which defines a two-torus automorphisms, an example of strongly chaotic system.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"50 1","pages":"IV-577"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86263454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329888
K. G. Ruan
Mixed-signal mixed-technology simulation increasingly being used in complex system design verification. Now, it has been adopted by many mixed-technology industries, including automotive and aerospace industries, for designing an electronic-control-unit (ECU). Micro-controllers are often used in ECUs for better features and performance. Design verification of micro-controller based ECUs is a significant challenge to simulation technology. A new model architecture is proposed in this paper. An embedded control system co-simulator, Saber(tm)MC, is under development based on this architecture. Simulation of an entire ECU can be performed with a set of intuitive commands. Software developer may use a debugger to debug the customer code while an entire ECU is being simulated. A brushless DC motor controller is used to illustrate the proposed model architecture and demonstrate that it fits in well in ECU design verification.
{"title":"A new model architecture for customer software integration","authors":"K. G. Ruan","doi":"10.1109/ISCAS.2004.1329888","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329888","url":null,"abstract":"Mixed-signal mixed-technology simulation increasingly being used in complex system design verification. Now, it has been adopted by many mixed-technology industries, including automotive and aerospace industries, for designing an electronic-control-unit (ECU). Micro-controllers are often used in ECUs for better features and performance. Design verification of micro-controller based ECUs is a significant challenge to simulation technology. A new model architecture is proposed in this paper. An embedded control system co-simulator, Saber(tm)MC, is under development based on this architecture. Simulation of an entire ECU can be performed with a set of intuitive commands. Software developer may use a debugger to debug the customer code while an entire ECU is being simulated. A brushless DC motor controller is used to illustrate the proposed model architecture and demonstrate that it fits in well in ECU design verification.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"03 1","pages":"V-V"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86076649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328981
Meng-Lin Hsia, O. Chen, H. Jan, Sun-Chen Wang, Yaw-Tyng Wu
In this work, we develop a method for rapid bit-error-rate (BER) measurements to reduce testing time of infrared communication systems. This method is to increase the probability of errors occurring in the communication system, which are caused by adding some special signals, such as DC offset noise and additive white Gaussian noise, inside the transmitter. The measured results are used to estimate the BER of the IrDA device at normal operation. Additionally, the relationship between the BER and the confidence level is explored to support the proposed rapid measurement. In our practical measurements of IrDA at 115.2 Kbps, measurement time for each testing device can be reduced from 12 hours to 1.45 seconds with a reduction of around 10/sup 5/ times. The proposed rapid measurement system has been successfully developed and can be easily applied to measure various optical communication systems at a low set-up cost.
{"title":"Rapid bit-error-rate measurements of infrared communication systems","authors":"Meng-Lin Hsia, O. Chen, H. Jan, Sun-Chen Wang, Yaw-Tyng Wu","doi":"10.1109/ISCAS.2004.1328981","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328981","url":null,"abstract":"In this work, we develop a method for rapid bit-error-rate (BER) measurements to reduce testing time of infrared communication systems. This method is to increase the probability of errors occurring in the communication system, which are caused by adding some special signals, such as DC offset noise and additive white Gaussian noise, inside the transmitter. The measured results are used to estimate the BER of the IrDA device at normal operation. Additionally, the relationship between the BER and the confidence level is explored to support the proposed rapid measurement. In our practical measurements of IrDA at 115.2 Kbps, measurement time for each testing device can be reduced from 12 hours to 1.45 seconds with a reduction of around 10/sup 5/ times. The proposed rapid measurement system has been successfully developed and can be easily applied to measure various optical communication systems at a low set-up cost.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"21 1","pages":"IV-225"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86110533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328883
F. Ababsa, M. Mallem
A basic problem with augmented reality systems using head-mounted displays (HMDs) is the perceived latency or lag. This delay corresponds to the elapsed time between the moment when the user's head moves and the moment of displaying the corresponding virtual objects in the HMD. One way to eliminate or reduce the effects of system delays is to predict the future head locations. Actually, the most used filter to predict head motion is the extended Kalman filter (EKF). However, when dealing with nonlinear models (like head motion) in state equation and measurement relation and a non Gaussian noise assumption, the EKF method may lead to a non optimal solution. In this paper, we propose to use sequential Monte Carlo methods, also known as particle filters to predict head motion. These methods provide general solutions to many problems with any nonlinearities or distributions. Our purpose is to compare, both in simulation and in real task, the results obtained by particle filter with those given by EKF.
{"title":"Inertial and vision head tracker sensor fusion using a particle filter for augmented reality systems","authors":"F. Ababsa, M. Mallem","doi":"10.1109/ISCAS.2004.1328883","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328883","url":null,"abstract":"A basic problem with augmented reality systems using head-mounted displays (HMDs) is the perceived latency or lag. This delay corresponds to the elapsed time between the moment when the user's head moves and the moment of displaying the corresponding virtual objects in the HMD. One way to eliminate or reduce the effects of system delays is to predict the future head locations. Actually, the most used filter to predict head motion is the extended Kalman filter (EKF). However, when dealing with nonlinear models (like head motion) in state equation and measurement relation and a non Gaussian noise assumption, the EKF method may lead to a non optimal solution. In this paper, we propose to use sequential Monte Carlo methods, also known as particle filters to predict head motion. These methods provide general solutions to many problems with any nonlinearities or distributions. Our purpose is to compare, both in simulation and in real task, the results obtained by particle filter with those given by EKF.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"2013 1","pages":"III-861"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82696579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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