Journal of Materials Science: Materials in Electronics最新文献

Bulk-sized single crystals of (SR-BCPP) were successfully produced using the S–R technique. SR-BCPP belongs to the noncentrosymmetric space group. SR-BCPP’s optical transparency enhanced by 7%. The LDT of SR-BCPP was calculated and the value was 0.4487 GW/cm. SR-BCPP hardness rises with increasing load upto 130 g. The SHG efficacy of SR-BCPP was 4.2 times more than that of the frequently used KDP. The piezoelectric charge coefficient for the SR-BCPP was discovered to be 8.1 pC/N. UV transmittance, refractive index, birefringence, LDT, microhardness, piezoelectric, and SHG all characteristics were enhanced as compared to conventionally produced BCPP.

The demand for supercapacitors with high energy and power densities has accelerated the search for efficient electrode materials. In this study, we prepared a binary composite of multi-walled carbon nanotubes (MWCNT) and nickel tungstate (NiWO₄) using a simple hydrothermal method, achieving a specific capacitance of 885 F g⁻¹ at 1 A g⁻¹ with strong cyclic stability, maintaining 86% capacity after 5000 cycles. Electrochemical analysis revealed a shift in the charge storage mechanism of MWCNT/NiWO₄ composite with “b-values” of 0.84 to low indicating a capacitive-dominant behavior with increased scan rate likely due to the formation of a double-layer and the presence of MWCNTs. The composite exhibited enhanced conductivity with a charge transfer resistance (R_ct) of 0.9 Ω compared to 3.2 Ω for NiWO₄ alone. This study highlights the potential of MWCNT/NiWO₄ as a cost-effective, high-performance electrode material for next-generation supercapacitors.

In this work Sol–Gel synthesized Sn_(1−z) GO_zO₂, (where z = 0, 0.01, and 0.02) nanoparticles were used as a SUT (Sample under test) on Flame Retardant (FR-4) substrate-based fabricated sensor and detailed characterizations of their structural, morphological, and dielectric properties have been obtained. The sensor has good resonance at two different frequencies, 4.8 and 8.4 GHz, with S₁₁ of − 22.29 and − 19.60 dB (for z = 0), − 24.63 and − 21.36 dB (for z = 0.01), and − 24.93 and − 21.95 dB (for z = 0.02), respectively, according to the experimental findings. The results exhibit minimal variations from the experimental findings and are in perfect alignment with the simulated mirrored sensor tuned to function at 4.85 GHz and 7.35 GHz frequencies with insertion loss less than − 20 dB. A detailed understanding of the interactions between crystallite size, frequency, dielectric constant, and reflection coefficients can be achieved through the comprehensive analysis of the Sample Under Test (SUT). Through simulation, and VNA measurements its performance has been verified, showing promise for a variety of applications in the C-, and X- bands. The design and optimization of sophisticated electromagnetic materials, where exact control over dielectric and reflection characteristics is critical, would greatly benefit from these findings.

Worldwide, E-waste is collected large in quantities from electronics and computer components these items are highly harmful to humans and the environment. Printed Circuit Boards (PCBs) are one of the E-waste that has to be received from all electronic items such as hard disks, motherboards and electronic circuitry boards. PCBs are generally made by using E-Glass fibers and mounting of capacitors, diodes etc., these are created harmful to environmental surroundings at the influence of waste conditions. This study makes an effort to defeat the environmental pollutions caused by E-waste (PCBs). In this work replacing E-glass fibers is used in the PCBs with natural fibers, prepared by polymer matrix composites. Natural fibers such as banana fiber and rice husk are blended in equal volume ratio with epoxy resin for making effective composites. Minimum weight loss can be obtained with the optimal parameters of 16 mm of flame gap and 45 mm of flame travel for 15 s. The minimum moisture absorption was observed for the composites fabricated with 60 wt% of fiber, 12 MPa of compaction pressure for 36 h of immersion. The necessary properties of the composites such as flammability and moisture absorption are analyzed with the influence of different parameters with the use of the Taguchi optimization route. The Flame gap parameter is highly influenced by the weight loss in the flammability test, further, the compaction pressure is a major effecting parameter for weight decided in the moisture absorption test.

Copper (Cu)-incorporated (0 to 2 at.%) Zinc oxide (ZnO)-Graphene oxide (GO) nanostructures were synthesized via a hydrothermal technique and spin-coated on silicon (Si) substrates. Structural analysis using X-ray diffraction (XRD) and atomic force microscopy (AFM) confirmed the successful formation of well-crystallized ZnO nanoparticles on GO sheets, with AFM revealing a decrease in grain size as the Cu incorporation concentration increased, resulting in smoother and more homogeneous surfaces. Optical studies revealed a reduction in the bandgap to 3.241 eV for 2 at.% Cu-treated films, compared to pure ZnO. Alongside this, photoluminescence (PL) emission intensity decreased as the Cu concentration increased. Furthermore, optical reflectance measurements showed a gradual decrease in reflectance with increasing Cu incorporation, indicating improved light absorption. The carrier lifetime of the Si and Cu-incorporated ZnO–GO/Si samples significantly increased, with the 2% Cu-doped sample reaching 165 μs. These results highlight that Cu incorporation in ZnO–GO improves surface passivation by reducing recombination sites and enhancing light absorption, making it a promising material for silicon-based devices, particularly in photovoltaic applications.

The ‘novel’ complex material KSmSnO₄ described in the paper “Investigation of structural, dielectric, impedance, and conductivity properties of layered perovskite-type compound; KSmSnO₄”. J Mater Sci: Mater Electron 35, 2174 (2024)) does not exist because the studied sample is another compound: Sm₂Sn₂O₇ with some small amount of potassium dopant.

Chalcogenide semiconductors that contain S, Se and Te as their main components exhibit characteristic properties that stem from the electronic structure of the chalcogen atoms. In particular, they have recently attracted attention as materials for thermoelectric devices, phase-change memories, and electrical switches. In this study, we focused on Sn–Se as a binary chalcogenide, and fabricated thin films and evaluated their electronic properties. The band gap of the Sn–Se films prepared by vacuum deposition was ~ 1.10 eV. The electrical resistivity showed a thermal activation type, and a decrease in resistivity of more than two orders of magnitude was observed by heat treatment at 300 °C. Subgap optical absorption was measured by photothermal deflection spectroscopy, and four types of in-gap states were found. Based on these experimental results, a band model including localized states is discussed.

Lead-free relaxor ferroelectrics (RFEs) have great potential applications in dielectric ceramic capacitors due to their distinguished energy storage performance, such as power pulse devices, manufacturing motors, sensors, and more. However, achieving high energy density and high efficiency simultaneously is a major challenge for practical applications. The performance of a capacitor depends largely on the interface between metal electrode and ceramics, which is related to the transfer of charge carrier process. In this work, the relaxation degree and defect dipole are manipulated by entropy manipulation and cation defect, while the surface micro-region area defect control is caused by the surface buried firing calcination process. We have designed and synthesized the performances of all the series of BaTiO₃-basedperovskite ceramics as well as surface cation defect modification such as BaTiO₃, Ba_0.95TiO₃, (Ba_0.95Sr_0.05)TiO₃, (Ba_0.95-3x/2Sr_0.05Bi_x)TiO₃, resurfaced (Ba_0.95Sr_0.05)TiO₃, and resurfaced (Ba_0.95-3x/2Sr_0.05Bi_x)TiO₃. Surface micro-region lattice distortions caused by the surface cation-defects reduce the carrier diffusion between the metal electrode and the BaTiO₃-basedperovskite ceramic samples, which diminishes the polarization hysteresis and improving the energy storage efficiency. Specifically, the surface reconstructed (Ba_0.8Sr_0.05Bi_0.1)TiO₃ ceramics exhibited excellent breakdown field strength characteristics (E_b = 155 kV·cm⁻¹) and minimal hysteresis residual polarization characteristics (P_r = 1.9 μC·cm⁻²), resulting in the largest storage density (W_rec = 1.193 J/cm³) and highest efficiency (η = 83.41%), indicating the general efficacy of our surface cation-defects engineering strategy, which provided new insights for the design of ceramic components.

Interface trap reliability in MOS devices is a significant area of concern in the domain of semiconductor devices. With the advent of new device architectures with miniaturized dimensions, it has become fundamentally important to include methods to predict interface trap reliability. This article reports the impact of interface traps on the low power performance of tunnel field-effect transistors (TFETs) through statistical variability approach. Tunnel field-effect transistors (TFETs), which function via quantum mechanical tunnelling, have emerged as promising devices for low-power applications. Interface traps are localized energy states at the semiconductor-oxide interface that can trap charge carriers, and affect the low-power performance of the devices. These traps can be either acceptor-like or donor-like based on their position within the energy band gap. This article investigates the impact of these traps on the key performance metrics of a silicon-on-insulator (SOI) n-p-n double-gate TFET (DG TFET). Calibrated with experimental data, the proposed work involves 200 simulations using technology computer-aided design tool, Sentaurus TCAD. Considering Gaussian distribution of interface traps, the traps were physically localized at the interface, where a trap-localized region was 4 nm long. At a time, one trap-localized region was considered, which was randomly placed in each of the 200 simulations. The variations in the threshold voltage (({V}_{th})), on-current (({I}_{text{ON}})), and off-current (({I}_{text{OFF}})) are represented through the standard deviation of the parameters. Since the methodology adopted in this work is universal, it has the potential to be a promising technique to assess the reliability of any kind of MOS device in an unbiased manner.