Fan-out wafer level packaging technology becomes more attractive and popular in the semiconductor packaging industry. The fan-out wafer level package (FOWLP) has the feature of integrating various devices in a tiny form factor. Since the FOWLP size is compact and small, its package strength is critical to its reliability. In this work, the three-point bending test method and finite element method was used to evaluate the FOWLP strength. Two different structural FOWLP were built, and their numerical models were created. The results showed that the FOWLP experiment and simulation flexure strength results matched each other in the lower failure possibility area closely. However, the simulation results under-estimated the FOWLP failure possibility to compare with the experiment results in the upper failure possibility area.
{"title":"Numerical and Experimental Study of Fan-Out Wafer Level Package Strength","authors":"Cheng Xu, Z. Zhong, W. Choi","doi":"10.1109/ECTC.2017.152","DOIUrl":"https://doi.org/10.1109/ECTC.2017.152","url":null,"abstract":"Fan-out wafer level packaging technology becomes more attractive and popular in the semiconductor packaging industry. The fan-out wafer level package (FOWLP) has the feature of integrating various devices in a tiny form factor. Since the FOWLP size is compact and small, its package strength is critical to its reliability. In this work, the three-point bending test method and finite element method was used to evaluate the FOWLP strength. Two different structural FOWLP were built, and their numerical models were created. The results showed that the FOWLP experiment and simulation flexure strength results matched each other in the lower failure possibility area closely. However, the simulation results under-estimated the FOWLP failure possibility to compare with the experiment results in the upper failure possibility area.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"18 1","pages":"2187-2192"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91163845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Lee, Cheng-Chih Chen, Dem Lee, Cherie Chen, Alice Lin
The polymer cored solder interconnect has been investigated in board level strain concerned ball grid array type IC package for many years. The novel solder ball with a polymer core is designed to compensate the board level reliability weakness of current metal alloy interconnect such as mechanical and thermal-mechanical fatigue endurance due to its unique spherical polymeric core able to absorb the strain energy generated during the reliability test, as well as the service in field. In terms of large size BGA packages such as Ceramic BGA and FCBGA, which suffer more significant solder joint strain on the package corner, the polymer cored solder interconnect is adopted to be capable of withstanding solder joint deformation between PCB and package under board level stress due to its more ductile characteristics. In the study, the daisy chained ceramic substrate based BGA with 29x29 mm square, 1.2mm thickness, 483 I/O, 1.27 mm pitch and 2 types of solder ball, one is SAC305 and another is polymer core coated SnAg, were ball attached through standard package assembly process. The assembled IC package was surface mounted on OSP finished PCB with SAC305 NC solder paste, then is subjected to accelerated temperature cycling test until 3000 cycles at 0/100 degree C with 10min dwell and 10min ramp. After that, the electrical failed sample was taken for various failure mode observations through dye and pry analysis and cross section under OM and SEM, respectively. The diverse typical failure modes across all solder joint was investigated for comparison in statistic between SAC305 and polymer cored solder and concluded polymer cored solder will outperform SAC305.
{"title":"The Novel Failure Mechanism of the Polymer Ball Interconnected CBGA under Board Level Thermal Mechanical Stress","authors":"J. Lee, Cheng-Chih Chen, Dem Lee, Cherie Chen, Alice Lin","doi":"10.1109/ECTC.2017.66","DOIUrl":"https://doi.org/10.1109/ECTC.2017.66","url":null,"abstract":"The polymer cored solder interconnect has been investigated in board level strain concerned ball grid array type IC package for many years. The novel solder ball with a polymer core is designed to compensate the board level reliability weakness of current metal alloy interconnect such as mechanical and thermal-mechanical fatigue endurance due to its unique spherical polymeric core able to absorb the strain energy generated during the reliability test, as well as the service in field. In terms of large size BGA packages such as Ceramic BGA and FCBGA, which suffer more significant solder joint strain on the package corner, the polymer cored solder interconnect is adopted to be capable of withstanding solder joint deformation between PCB and package under board level stress due to its more ductile characteristics. In the study, the daisy chained ceramic substrate based BGA with 29x29 mm square, 1.2mm thickness, 483 I/O, 1.27 mm pitch and 2 types of solder ball, one is SAC305 and another is polymer core coated SnAg, were ball attached through standard package assembly process. The assembled IC package was surface mounted on OSP finished PCB with SAC305 NC solder paste, then is subjected to accelerated temperature cycling test until 3000 cycles at 0/100 degree C with 10min dwell and 10min ramp. After that, the electrical failed sample was taken for various failure mode observations through dye and pry analysis and cross section under OM and SEM, respectively. The diverse typical failure modes across all solder joint was investigated for comparison in statistic between SAC305 and polymer cored solder and concluded polymer cored solder will outperform SAC305.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"9 1","pages":"2015-2020"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78445632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Temporary bonding and de-bonding techniques using respectively spin-on glass (SOG) and hydrogenated amorphous-Si (a-Si:H) have been examined for multichip-to-wafer three-dimensional (3D) integration process. In this study, a 280 um-thick known good dies of 5 mm × 5 mm in size were temporarily bonded to a pre-deposited (a-Si:H (100 nm) and SOG (400 nm)) support glass wafer. After completing the die thinning and TSV formation processes, the dies were de-bonded using 248 nm excimer laser. The surfaces of de-bonded chip/wafer and glass substrate were meticulously investigated using x-ray photoelectron spectroscopy (XPS). From C1s, O1s, and Si1s XPS data, it is inferred that the de-bonding occurs in the a-Si:H layer. It reveals that the interface between the SOG and a-Si:H layer was highly intact, and the bonding strength is good enough to withstand the harsh environment during die/wafer thinning and TSV formation processes.
{"title":"Temporary Bonding and De-Bonding for Multichip-to-Wafer 3D Integration Process Using Spin-on Glass and Hydrogenated Amorphous Si","authors":"M. Murugesan, T. Fukushima, M. Koyanagi","doi":"10.1109/ECTC.2017.253","DOIUrl":"https://doi.org/10.1109/ECTC.2017.253","url":null,"abstract":"Temporary bonding and de-bonding techniques using respectively spin-on glass (SOG) and hydrogenated amorphous-Si (a-Si:H) have been examined for multichip-to-wafer three-dimensional (3D) integration process. In this study, a 280 um-thick known good dies of 5 mm × 5 mm in size were temporarily bonded to a pre-deposited (a-Si:H (100 nm) and SOG (400 nm)) support glass wafer. After completing the die thinning and TSV formation processes, the dies were de-bonded using 248 nm excimer laser. The surfaces of de-bonded chip/wafer and glass substrate were meticulously investigated using x-ray photoelectron spectroscopy (XPS). From C1s, O1s, and Si1s XPS data, it is inferred that the de-bonding occurs in the a-Si:H layer. It reveals that the interface between the SOG and a-Si:H layer was highly intact, and the bonding strength is good enough to withstand the harsh environment during die/wafer thinning and TSV formation processes.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"22 1","pages":"1237-1242"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78900070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chiho Ueta, K. Okada, Toko Shiina, T. Hanada, N. Ito
Innovations like virtual cockpit and autonomous car have changed the application landscape of the automotive industry, and two key changes have derived: the footprints of electronic devices in cars increased and the industry demands even higher-density and even higher-performance ICs with higher count I/O for smarter vehicles in the coming future. BGA (Ball Grid Array) is one of the key technologies expected to support these growing and diversifying automotive IC applications, including under-hood and other harsher use cases, which require higher heat resistance and durability. For example, the automotive industry's standard "AEC-Q100 Grade 0" now requires BGA packages heat resistance of storage temperature at 175 deg C, even higher than the conventional marking point of 150 deg C. Development of new packaging materials is the pressing need to support these even more stringent requirements. More reliable solder resists will play the critical role to provide reliable insulation for the BGA technology, but delamination and/or TST (Thermal Shock test) cracks are reported with storage test at 175 deg C and/or shorter high temperature cycling. Delamination is caused mainly by insufficient heat resistance of the resins and degraded adhesion between the SR and base material or Cu layers due to stress changes caused by temperature at the higher range. For the cause of TST cracks, we have checked and determined, by the series of simulation and tests, that they are caused largely because changes in complex modulus derive from crosslink density changes at high temperatures and leads to increase in stress at lower temperatures. These problems need to be solved in order to offer really reliable insulation for smarter automotive ICs. In order to solve the above problems, we first obtained higher Tg by optimizing the filler/resin bond in order to raise the inorganic filler/resin ratio and by engineering a better matrix resin composition which enabled higher thermal crosslink densities. We established a technology that effectively suppresses the heat degradation under high temperature by adopting this higher Tg, which we demonstrated provided excellent dielectric properties. We also developed a method to suppress crosslink density change associated with prolonged exposure to heat and thus to minimize thermal-mechanical changes (i.e. changes in complex modulus) and changes in stress caused by high temperature storage. Furthermore, we fabricated a nanophase separation technique for the elastomer which improved the stress relaxation during thermal cycling without sacrificing the mechanical properties and which provided the internal stress relief due to high temperature storage in the HTSL. We fabricated test coupons using prototype SR accordingly and conducted a high-temperature storage test at 175 deg C for 3000 hrs. We observed neither delamination nor cracks in the test coupons during and after the HTSL. The dissipation factor of this material is 0.008, which is
{"title":"Development of Solder Resist with Improved Adhesion at HTSL (175 deg C for 3000 Hours) and Crack Resistance at TST for Automotive IC Package","authors":"Chiho Ueta, K. Okada, Toko Shiina, T. Hanada, N. Ito","doi":"10.1109/ECTC.2017.198","DOIUrl":"https://doi.org/10.1109/ECTC.2017.198","url":null,"abstract":"Innovations like virtual cockpit and autonomous car have changed the application landscape of the automotive industry, and two key changes have derived: the footprints of electronic devices in cars increased and the industry demands even higher-density and even higher-performance ICs with higher count I/O for smarter vehicles in the coming future. BGA (Ball Grid Array) is one of the key technologies expected to support these growing and diversifying automotive IC applications, including under-hood and other harsher use cases, which require higher heat resistance and durability. For example, the automotive industry's standard \"AEC-Q100 Grade 0\" now requires BGA packages heat resistance of storage temperature at 175 deg C, even higher than the conventional marking point of 150 deg C. Development of new packaging materials is the pressing need to support these even more stringent requirements. More reliable solder resists will play the critical role to provide reliable insulation for the BGA technology, but delamination and/or TST (Thermal Shock test) cracks are reported with storage test at 175 deg C and/or shorter high temperature cycling. Delamination is caused mainly by insufficient heat resistance of the resins and degraded adhesion between the SR and base material or Cu layers due to stress changes caused by temperature at the higher range. For the cause of TST cracks, we have checked and determined, by the series of simulation and tests, that they are caused largely because changes in complex modulus derive from crosslink density changes at high temperatures and leads to increase in stress at lower temperatures. These problems need to be solved in order to offer really reliable insulation for smarter automotive ICs. In order to solve the above problems, we first obtained higher Tg by optimizing the filler/resin bond in order to raise the inorganic filler/resin ratio and by engineering a better matrix resin composition which enabled higher thermal crosslink densities. We established a technology that effectively suppresses the heat degradation under high temperature by adopting this higher Tg, which we demonstrated provided excellent dielectric properties. We also developed a method to suppress crosslink density change associated with prolonged exposure to heat and thus to minimize thermal-mechanical changes (i.e. changes in complex modulus) and changes in stress caused by high temperature storage. Furthermore, we fabricated a nanophase separation technique for the elastomer which improved the stress relaxation during thermal cycling without sacrificing the mechanical properties and which provided the internal stress relief due to high temperature storage in the HTSL. We fabricated test coupons using prototype SR accordingly and conducted a high-temperature storage test at 175 deg C for 3000 hrs. We observed neither delamination nor cracks in the test coupons during and after the HTSL. The dissipation factor of this material is 0.008, which is","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"10 1","pages":"156-165"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84859624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A simple and low-cost fabrication method for single-mode polymer optical waveguides with circular cores was demonstrated for fiber-to-waveguide coupling. The waveguide structure consists of trenches with semicircular cross sections, fabricated with dry film benzocyclobutene (BCB) as the bottom cladding layer, circular cores embedded inside the trenches, and another layer of dry film BCB as the top cladding layer. Simple photolithography is used to pattern both trenches in the bottom cladding layer and cores, and only one mask is used for both lithography steps. The advantages of single-mode circular waveguides on ultra-thin 3D glass interposers are discussed by comparing optical properties of those with conventional polymer waveguides with trapezoidal cross sections. To the best of the author's knowledge, this is the first demonstration of single-mode polymer waveguides with circular cross sections. Fabrication of circular-core waveguides are discussed and geometry characterization and analysis are performed.
{"title":"First Demonstration of Single-Mode Polymer Optical Waveguides with Circular Cores for Fiber-to-Waveguide Coupling in 3D Glass Photonic Interposers","authors":"Rui Zhang, Fuhan Liu, V. Sundaram, R. Tummala","doi":"10.1109/ECTC.2017.306","DOIUrl":"https://doi.org/10.1109/ECTC.2017.306","url":null,"abstract":"A simple and low-cost fabrication method for single-mode polymer optical waveguides with circular cores was demonstrated for fiber-to-waveguide coupling. The waveguide structure consists of trenches with semicircular cross sections, fabricated with dry film benzocyclobutene (BCB) as the bottom cladding layer, circular cores embedded inside the trenches, and another layer of dry film BCB as the top cladding layer. Simple photolithography is used to pattern both trenches in the bottom cladding layer and cores, and only one mask is used for both lithography steps. The advantages of single-mode circular waveguides on ultra-thin 3D glass interposers are discussed by comparing optical properties of those with conventional polymer waveguides with trapezoidal cross sections. To the best of the author's knowledge, this is the first demonstration of single-mode polymer waveguides with circular cross sections. Fabrication of circular-core waveguides are discussed and geometry characterization and analysis are performed.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"34 1","pages":"1606-1611"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82507369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ting-chia Huang, V. Smet, P. Raj, R. Nichols, G. Ramos, Maja Tomic, Robin Taylor, R. Tummala
High-performance computing has been aggressively driving pitch and performance requirements for off-chip interconnections over the last several decades, pushing solder-based interconnections to their limits. The most leading-edge Cu pillar technology faces many fundamental challenges in scaling to pitches below 30um, in particular with stress management and increased risks of Au embrittlement as solder volume is reduced All-intermetallic interconnections formed by solid-liquid interdiffusion (SLID) bonding have been concurrently explored to extend solders to finer pitches and improve their performance, but face their own set of manufacturability and reliability challenges that have, so far, limited their use to 3D-ICs. This research comprehensively addresses these challenges with innovative interconnection designs and advances in surface finish metallurgies, which allow for precisely controlled and unique interfacial reactions. A two-fold approach is pursued to: 1) extend scalability of conventional Cu pillars by replacing standard ENEPIG with ultra-thin electroless Pd autocatalytic Au (EPAG) surface finish, and, for further pitch scaling and enhanced electrical and thermal performances, 2) enable void-free, manufacturable all-intermetallic joints solely composed of the metastable Cu6Sn5 phase by introduction of diffusion barrier layers. This paper presents the design, demonstration and characterization of such high-performance solder-based interconnections at 20um pitch, highlighting the strategic role of surface finish and diffusion barrier layers for potential further pitch scaling.
{"title":"Scaling Cu Pillars to 20um Pitch and Below: Critical Role of Surface Finish and Barrier Layers","authors":"Ting-chia Huang, V. Smet, P. Raj, R. Nichols, G. Ramos, Maja Tomic, Robin Taylor, R. Tummala","doi":"10.1109/ECTC.2017.324","DOIUrl":"https://doi.org/10.1109/ECTC.2017.324","url":null,"abstract":"High-performance computing has been aggressively driving pitch and performance requirements for off-chip interconnections over the last several decades, pushing solder-based interconnections to their limits. The most leading-edge Cu pillar technology faces many fundamental challenges in scaling to pitches below 30um, in particular with stress management and increased risks of Au embrittlement as solder volume is reduced All-intermetallic interconnections formed by solid-liquid interdiffusion (SLID) bonding have been concurrently explored to extend solders to finer pitches and improve their performance, but face their own set of manufacturability and reliability challenges that have, so far, limited their use to 3D-ICs. This research comprehensively addresses these challenges with innovative interconnection designs and advances in surface finish metallurgies, which allow for precisely controlled and unique interfacial reactions. A two-fold approach is pursued to: 1) extend scalability of conventional Cu pillars by replacing standard ENEPIG with ultra-thin electroless Pd autocatalytic Au (EPAG) surface finish, and, for further pitch scaling and enhanced electrical and thermal performances, 2) enable void-free, manufacturable all-intermetallic joints solely composed of the metastable Cu6Sn5 phase by introduction of diffusion barrier layers. This paper presents the design, demonstration and characterization of such high-performance solder-based interconnections at 20um pitch, highlighting the strategic role of surface finish and diffusion barrier layers for potential further pitch scaling.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"48 1","pages":"384-391"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82529059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Junghwa Kim, SeungChul Han, W. Na, Soyoon Kim, Kihyeok Kwon, Deokhoon Park, Donghwan Lee, Sang Kyun Kim
Molded underfill (MUF) is one of the most effective molding technologies in the advanced packaging industry. Developing highly reliable MUF is still challenging due to all basic requisitions of semiconductor packaging. Among all these requirements, controlling interfacial delamination between materials in integrated circuits (IC) packages has been considered to be the most important challenge to be achieved. Even though there are many efforts to characterize the package delamination, an effective method to speculate the delamination has not been well established. Herein, we introduce an effective and reliable evaluation method to characterize and predict the interfacial delamination and cohesive failure under mechanical and thermal stresses. The delamination temperature of moisturized EMC package is defined at the fluctuated thermal mechanical analysis (TMA) signal point which is proportionally correlated to the delamination of real packages. Based on this result, we established the equation of package delamination with the result of package curvature by TMA and package warpage by shadow moire at 20 and 260°C. The package delamination temperature can be simply calculated by using general epoxy molding compound's properties, such as global dimension change and storage modulus from TMA and dynamic mechanical analysis (DMA) respectively. The package delamination temperature calculated by the equation is well matched with the actual package delamination temperature detected by infrared reflow method. In this paper, we will address details of theoretical backgrounds of the equation and introduce a new method for detecting the delamination temperature of packages. This novel evaluation method is able to develop and optimize a highly reliable epoxy molding compounds for MUF package.
{"title":"Effective Evaluation Method: A New Delamination Test Method for MUF (Molded Underfill) Package","authors":"Junghwa Kim, SeungChul Han, W. Na, Soyoon Kim, Kihyeok Kwon, Deokhoon Park, Donghwan Lee, Sang Kyun Kim","doi":"10.1109/ECTC.2017.242","DOIUrl":"https://doi.org/10.1109/ECTC.2017.242","url":null,"abstract":"Molded underfill (MUF) is one of the most effective molding technologies in the advanced packaging industry. Developing highly reliable MUF is still challenging due to all basic requisitions of semiconductor packaging. Among all these requirements, controlling interfacial delamination between materials in integrated circuits (IC) packages has been considered to be the most important challenge to be achieved. Even though there are many efforts to characterize the package delamination, an effective method to speculate the delamination has not been well established. Herein, we introduce an effective and reliable evaluation method to characterize and predict the interfacial delamination and cohesive failure under mechanical and thermal stresses. The delamination temperature of moisturized EMC package is defined at the fluctuated thermal mechanical analysis (TMA) signal point which is proportionally correlated to the delamination of real packages. Based on this result, we established the equation of package delamination with the result of package curvature by TMA and package warpage by shadow moire at 20 and 260°C. The package delamination temperature can be simply calculated by using general epoxy molding compound's properties, such as global dimension change and storage modulus from TMA and dynamic mechanical analysis (DMA) respectively. The package delamination temperature calculated by the equation is well matched with the actual package delamination temperature detected by infrared reflow method. In this paper, we will address details of theoretical backgrounds of the equation and introduce a new method for detecting the delamination temperature of packages. This novel evaluation method is able to develop and optimize a highly reliable epoxy molding compounds for MUF package.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"9 1","pages":"1153-1158"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88068690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Karnick, Nils Bauditsch, L. Eisenblätter, T. Kühner, Marc Schneider, Marc Weber
We present an efficient and easy-to-use process for a permanent fiber-to-chip coupling arrangement with angle-polished single-mode optical fibers (SMF) to maintain a planar profile while surface-coupling to grating couplers of a silicon photonic integrated circuit (PIC). The SMF are polished with a standard polishing machine to match the appropriate coupling angle. Due to the simplicity of the process, it is suitable for both packaging of photonic devices ready for commercialization and the rapid coupling of components at an early stage of development. The coupling arrangement does not impose additional insertion loss compared to a continuously controlled fiber alignment and remains stable even under strong variation of ambient temperature and humidity.
{"title":"Efficient, Easy-to-Use, Planar Fiber-to-Chip Coupling Process with Angle-Polished Fibers","authors":"D. Karnick, Nils Bauditsch, L. Eisenblätter, T. Kühner, Marc Schneider, Marc Weber","doi":"10.1109/ECTC.2017.245","DOIUrl":"https://doi.org/10.1109/ECTC.2017.245","url":null,"abstract":"We present an efficient and easy-to-use process for a permanent fiber-to-chip coupling arrangement with angle-polished single-mode optical fibers (SMF) to maintain a planar profile while surface-coupling to grating couplers of a silicon photonic integrated circuit (PIC). The SMF are polished with a standard polishing machine to match the appropriate coupling angle. Due to the simplicity of the process, it is suitable for both packaging of photonic devices ready for commercialization and the rapid coupling of components at an early stage of development. The coupling arrangement does not impose additional insertion loss compared to a continuously controlled fiber alignment and remains stable even under strong variation of ambient temperature and humidity.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"7 4 1","pages":"1627-1632"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88070370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The migration of high-reliability applications requiring sustained operation in harsh environments needs a better understanding of the acceleration factors under the stresses of operation. Prolonged exposure of the copper wire to elevated temperatures results in growth of excessive intermetallics and degradation of the interface. Behavior of Copper wirebond under high current-temperature conditions is not yet fully understood. Exposure to high current may induce Joule heating and electromigration, and thus significantly increase the degradation rate in comparison with low current operating conditions. Further, the accelerated test results of unbiased conditions cannot be used for life prediction of such high powered parts. EMCs used for encapsulation of the chip and the interconnects may vary widely in their formulation including pH, porosity, diffusion rates, levels and composition of the contaminants. Selection of different materials, such as EMC used in the molding process plays key role in defining lifetime for wirebond system. There is need for predictive models which can account for the exposure to environmental conditions, operating conditions and the EMC formulation in order to be realistically representative of the expected reliability. In this paper, a set of parts, molded with different EMCs were subjected to high temperature-current environment (temperature range of 150°C-200°C, 0.2A-1A). An artificial neural network (ANN) driven predictive model for estimation of the beta-sensitivities of the input variables has been developed for computation of the acceleration factor for the Cu-Al WB under high voltage and high temperature.
{"title":"Model for Interaction of EMC Formulation with Operating Current and Reliability of Cu-Al Wirebonds Operating in Harsh Environments","authors":"P. Lall, Shantanu Deshpande, YiHua Luo, L. Nguyen","doi":"10.1109/ECTC.2017.300","DOIUrl":"https://doi.org/10.1109/ECTC.2017.300","url":null,"abstract":"The migration of high-reliability applications requiring sustained operation in harsh environments needs a better understanding of the acceleration factors under the stresses of operation. Prolonged exposure of the copper wire to elevated temperatures results in growth of excessive intermetallics and degradation of the interface. Behavior of Copper wirebond under high current-temperature conditions is not yet fully understood. Exposure to high current may induce Joule heating and electromigration, and thus significantly increase the degradation rate in comparison with low current operating conditions. Further, the accelerated test results of unbiased conditions cannot be used for life prediction of such high powered parts. EMCs used for encapsulation of the chip and the interconnects may vary widely in their formulation including pH, porosity, diffusion rates, levels and composition of the contaminants. Selection of different materials, such as EMC used in the molding process plays key role in defining lifetime for wirebond system. There is need for predictive models which can account for the exposure to environmental conditions, operating conditions and the EMC formulation in order to be realistically representative of the expected reliability. In this paper, a set of parts, molded with different EMCs were subjected to high temperature-current environment (temperature range of 150°C-200°C, 0.2A-1A). An artificial neural network (ANN) driven predictive model for estimation of the beta-sensitivities of the input variables has been developed for computation of the acceleration factor for the Cu-Al WB under high voltage and high temperature.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"9 1","pages":"815-826"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91539530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Bex, Teng Wang, M. Lofrano, V. Cherman, G. Capuz, E. Sleeckx, E. Beyne
Thermal compression bonding (TCB) is becoming an increasingly important process step in the assembly of advanced components such as fine pitch flip chip packages, system-in-package products, and 3D IC's. To increase the throughput and robustness of TCB processes, it is crucial to understand and control important process parameters like time, force and temperature. However, for TCB processes it becomes challenging to measure and control the temperature over the bond interface, since typically different temperature profiles are applied to top chip and substrate. This paper proposes and validates a new methodology for temperature measurements and characterization of heat transfer during a TCB process. On-chip thermal sensors measure the temperature in real time during the TCB process, at different locations on both top and bottom chips. Since the proposed methodology does not require the insertion of a thermocouple in between the top chip and substrate, it will enable more reliable measurements, especially for fine pitch micro bump devices.
{"title":"Thermal Compression Bonding: Understanding Heat Transfer by in Situ Measurements and Modeling","authors":"P. Bex, Teng Wang, M. Lofrano, V. Cherman, G. Capuz, E. Sleeckx, E. Beyne","doi":"10.1109/ECTC.2017.49","DOIUrl":"https://doi.org/10.1109/ECTC.2017.49","url":null,"abstract":"Thermal compression bonding (TCB) is becoming an increasingly important process step in the assembly of advanced components such as fine pitch flip chip packages, system-in-package products, and 3D IC's. To increase the throughput and robustness of TCB processes, it is crucial to understand and control important process parameters like time, force and temperature. However, for TCB processes it becomes challenging to measure and control the temperature over the bond interface, since typically different temperature profiles are applied to top chip and substrate. This paper proposes and validates a new methodology for temperature measurements and characterization of heat transfer during a TCB process. On-chip thermal sensors measure the temperature in real time during the TCB process, at different locations on both top and bottom chips. Since the proposed methodology does not require the insertion of a thermocouple in between the top chip and substrate, it will enable more reliable measurements, especially for fine pitch micro bump devices.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"3 1","pages":"392-398"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91042060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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