V. N. N. T. Rambhatla, David Samet, S. McCann, S. Sitaraman
The objective of this work is to develop a combinedmode I and mode III characterization method and to use thistest method to study Copper (Cu) / Epoxy mold compound(EMC) interfacial delamination from near-mode I to nearmodeIII global loading. Using the developed test method, aseries of experiments are done with varying loading modeconditions from near-mode I to near-mode III and successfuldelamination of the Cu/EMC interface is observed in manycases. Three-dimensional finite-element analysis is carried outto get compliance vs crack length relationship for differentloading conditions and is used to determine the crack lengthindirectly. The experiments indicate that as the mode mixityincreases from mode I towards mode III, the critical loadincreases for a given crack length, and thus, the interfacialfracture energy increases with the increasing mode mixity.
{"title":"A Characterization Method for Interfacial Delamination of Copper/Epoxy Mold Compound Specimens under Mixed Mode I/III Loading","authors":"V. N. N. T. Rambhatla, David Samet, S. McCann, S. Sitaraman","doi":"10.1109/ECTC.2017.291","DOIUrl":"https://doi.org/10.1109/ECTC.2017.291","url":null,"abstract":"The objective of this work is to develop a combinedmode I and mode III characterization method and to use thistest method to study Copper (Cu) / Epoxy mold compound(EMC) interfacial delamination from near-mode I to nearmodeIII global loading. Using the developed test method, aseries of experiments are done with varying loading modeconditions from near-mode I to near-mode III and successfuldelamination of the Cu/EMC interface is observed in manycases. Three-dimensional finite-element analysis is carried outto get compliance vs crack length relationship for differentloading conditions and is used to determine the crack lengthindirectly. The experiments indicate that as the mode mixityincreases from mode I towards mode III, the critical loadincreases for a given crack length, and thus, the interfacialfracture energy increases with the increasing mode mixity.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"34 1","pages":"1888-1893"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75246899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Daquan Yu, Zhe-Yu Huang, Zhiyi Xiao, Li Yang, Min Xiang
Advanced packaging technology plays more and more important role for device miniaturization, system integration, and performance enhancement. Among many new packaging technologies, fan-out wafer level packaging (FOWLP) aroused more interests and showed the advantages of higher number of I/Os, integration flexibilities, low cost, and small form factor due to the elimination of substrate. However, FOWLP using epoxy mold compound (EMC) material faces a number of technical challenges such as warpage wafer handling, difficult to fabricate fine-pitch redistribution layer (RDL), and reliability issues for large package due to the CTE mismatch between chip and EMC. In addition, for high performance SiP, advanced FOWLP with multilayer fine-pitch RDLs, excellent alignment accuracy, shortest interconnect routing between dies, and ultra small form factor was required. In this paper, the development of a wafer level embedded silicon fan-out, named eSiFO technology was reported. For eSiFO package, the known good dies are embedded in the cavities formed on silicon wafer and the micro-scale gap between the dies and cavities is filled by epoxy material. An almost entire silicon surface was constructed as the fan-out area for RDL and BGA. The process is simple comparing with standard FOWLP since there is no molding, temporary bonding and de-bonding process. The key advantage is that the CTE for dies and silicon wafer is same and there is no warpage issue during manufacturing which results in good packaging yield. An eSiFO package with size of 3.3×3.3mm, one layer RDL and 50 BGAs was successfully demonstrated. The results proved that the process of eSiFO was simple and suitable for high density system integration with ultra low profile. Various reliability tests were carried out to study the package reliability and no failure was found. The simulation results show that for the same package, eSiFO has lower thermal stress than FOWLP using EMC.
{"title":"Embedded Si Fan Out: A Low Cost Wafer Level Packaging Technology without Molding and De-Bonding Processes","authors":"Daquan Yu, Zhe-Yu Huang, Zhiyi Xiao, Li Yang, Min Xiang","doi":"10.1109/ECTC.2017.166","DOIUrl":"https://doi.org/10.1109/ECTC.2017.166","url":null,"abstract":"Advanced packaging technology plays more and more important role for device miniaturization, system integration, and performance enhancement. Among many new packaging technologies, fan-out wafer level packaging (FOWLP) aroused more interests and showed the advantages of higher number of I/Os, integration flexibilities, low cost, and small form factor due to the elimination of substrate. However, FOWLP using epoxy mold compound (EMC) material faces a number of technical challenges such as warpage wafer handling, difficult to fabricate fine-pitch redistribution layer (RDL), and reliability issues for large package due to the CTE mismatch between chip and EMC. In addition, for high performance SiP, advanced FOWLP with multilayer fine-pitch RDLs, excellent alignment accuracy, shortest interconnect routing between dies, and ultra small form factor was required. In this paper, the development of a wafer level embedded silicon fan-out, named eSiFO technology was reported. For eSiFO package, the known good dies are embedded in the cavities formed on silicon wafer and the micro-scale gap between the dies and cavities is filled by epoxy material. An almost entire silicon surface was constructed as the fan-out area for RDL and BGA. The process is simple comparing with standard FOWLP since there is no molding, temporary bonding and de-bonding process. The key advantage is that the CTE for dies and silicon wafer is same and there is no warpage issue during manufacturing which results in good packaging yield. An eSiFO package with size of 3.3×3.3mm, one layer RDL and 50 BGAs was successfully demonstrated. The results proved that the process of eSiFO was simple and suitable for high density system integration with ultra low profile. Various reliability tests were carried out to study the package reliability and no failure was found. The simulation results show that for the same package, eSiFO has lower thermal stress than FOWLP using EMC.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"90 1","pages":"28-34"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75426818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Shahane, K. Mohan, G. Ramos, A. Kilian, Robin Taylor, F. Wei, P. Raj, A. Antoniou, V. Smet, R. Tummala
This paper presents the design and implementation of engineered nanoscale bonding interfaces as an effective strategy to improve manufacturability of Cu-Cu bonding to the level where it can, for the first time, be applied to chip-to-substrate (C2S) assembly. All-Cu interconnections are highly sought after to meet the escalating electrical, thermal, and reliability requirements of a wide range of emerging digital and analog systems. Such applications require low-cost processes with bonding temperatures and pressures ideally below 200°C and 20MPa, respectively, far from existing solutions established in wafer-level packaging. GT-PRC and its industry partners address this technology gap through innovative designs of bonding interfaces, introducing: 1) novel ultra-thin surface finish metallurgies applied on Cu bumps and pads to prevent oxidation and achieve low-temperature assembly, 2) low-cost fly-cut planarization technique to lower bonding pressures, and 3) low-modulus nanocopper foam caps to provide tolerance to non-coplanarities, and further reduce bonding temperatures and pressures.
{"title":"Enabling Chip-to-Substrate All-Cu Interconnections: Design of Engineered Bonding Interfaces for Improved Manufacturability and Low-Temperature Bonding","authors":"N. Shahane, K. Mohan, G. Ramos, A. Kilian, Robin Taylor, F. Wei, P. Raj, A. Antoniou, V. Smet, R. Tummala","doi":"10.1109/ECTC.2017.313","DOIUrl":"https://doi.org/10.1109/ECTC.2017.313","url":null,"abstract":"This paper presents the design and implementation of engineered nanoscale bonding interfaces as an effective strategy to improve manufacturability of Cu-Cu bonding to the level where it can, for the first time, be applied to chip-to-substrate (C2S) assembly. All-Cu interconnections are highly sought after to meet the escalating electrical, thermal, and reliability requirements of a wide range of emerging digital and analog systems. Such applications require low-cost processes with bonding temperatures and pressures ideally below 200°C and 20MPa, respectively, far from existing solutions established in wafer-level packaging. GT-PRC and its industry partners address this technology gap through innovative designs of bonding interfaces, introducing: 1) novel ultra-thin surface finish metallurgies applied on Cu bumps and pads to prevent oxidation and achieve low-temperature assembly, 2) low-cost fly-cut planarization technique to lower bonding pressures, and 3) low-modulus nanocopper foam caps to provide tolerance to non-coplanarities, and further reduce bonding temperatures and pressures.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"83 1","pages":"968-975"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74514632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The motivation behind this study is to detect barrier and dielectric liner degradation in a copper (Cu) through-silicon via (TSV) structure. The integrity of titanium (Ti) barrier and silicon dioxide (SiO2) dielectric liner are evaluated via a non-destructive electrical characterization method after being subjected to different stress tests such as high temperature storage (HTS), temperature cycling (TC) and electrical biasing. The various different stresses were either performed independently, or performed as a combination stress with electrical bias for comparison. After performing the respective stresses, capacitance-voltage (C-V) and current density-electric field (J-E) characteristics were analyzed to identify differences in its electrical characteristics. Degradation of the barrier liner may result in the migration of Cu from the Cu via into the dielectric liner. This is identified by changes observed in the inversion capacitance, as reflected in the C-V curve. Physical failure analysis (PFA) was performed on degraded structures and verified the presence of Cu in the dielectric due to barrier degradation as detected by the electrical measurement. It is suggested that barrier degradation leading to the migration of Cu into the dielectric liner can be associated to material and structural integrity which is dependent on the stress conditions. This understanding is useful in the reliability assessment of Cu TSV structures under various stress conditions, making it appropriate for future TSV degradation studies.
{"title":"Reliability Evaluation of Copper (Cu) Through-Silicon Vias (TSV) Barrier and Dielectric Liner by Electrical Characterization and Physical Failure Analysis (PFA)","authors":"J. Chan, Xu Cheng, K. Lee, W. Kanert, C. S. Tan","doi":"10.1109/ECTC.2017.77","DOIUrl":"https://doi.org/10.1109/ECTC.2017.77","url":null,"abstract":"The motivation behind this study is to detect barrier and dielectric liner degradation in a copper (Cu) through-silicon via (TSV) structure. The integrity of titanium (Ti) barrier and silicon dioxide (SiO2) dielectric liner are evaluated via a non-destructive electrical characterization method after being subjected to different stress tests such as high temperature storage (HTS), temperature cycling (TC) and electrical biasing. The various different stresses were either performed independently, or performed as a combination stress with electrical bias for comparison. After performing the respective stresses, capacitance-voltage (C-V) and current density-electric field (J-E) characteristics were analyzed to identify differences in its electrical characteristics. Degradation of the barrier liner may result in the migration of Cu from the Cu via into the dielectric liner. This is identified by changes observed in the inversion capacitance, as reflected in the C-V curve. Physical failure analysis (PFA) was performed on degraded structures and verified the presence of Cu in the dielectric due to barrier degradation as detected by the electrical measurement. It is suggested that barrier degradation leading to the migration of Cu into the dielectric liner can be associated to material and structural integrity which is dependent on the stress conditions. This understanding is useful in the reliability assessment of Cu TSV structures under various stress conditions, making it appropriate for future TSV degradation studies.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"14 1","pages":"73-79"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74114282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ling Xie, S. Wickramanayaka, V. N. Sekhar, Daniel Ismael Cereno
Cu-Cu is a prefer choice of interconnects as it offered lower electrical resistance, no risk of shorting between the bump and higher reliability as compared to Cu-Solder Bump. However, Cu-Cu interconnect requests stringent condition such as Cu bump surface topography, flatness, uniformity of pillar array heights and clean bonding surface. From throughput point of view, Cu-Cu bonding is challenging as bonding profile involves long heating duration and high temperature. In this paper, we explore the method to improve the bonding throughput and improve interconnect formation. A novel Cu pillar structure is proposed with center core Cu pillar surrounded by side-wall layer solder. Such Cu pillar array is bonded on a bottom wafer with Cu pads through chip-to-wafer (C2W) method. Study shows the solder located at side-wall offers an assist of temporary tacking the chip on the wafer. Then the entire interconnect forms joint through the use of gang bonder. As the side-wall solder seals individual Cu pillar to corresponding bond pad, it helps to prevent non-contact or void interconnection in pillar array. With the tacking and gang bonding process, a higher throughput process can be realized and actively adopted by industry as it offers lower cost of assembly.
{"title":"Study of C2W Bonding Using Cu Pillar with Side-Wall Plated Solder","authors":"Ling Xie, S. Wickramanayaka, V. N. Sekhar, Daniel Ismael Cereno","doi":"10.1109/ECTC.2017.260","DOIUrl":"https://doi.org/10.1109/ECTC.2017.260","url":null,"abstract":"Cu-Cu is a prefer choice of interconnects as it offered lower electrical resistance, no risk of shorting between the bump and higher reliability as compared to Cu-Solder Bump. However, Cu-Cu interconnect requests stringent condition such as Cu bump surface topography, flatness, uniformity of pillar array heights and clean bonding surface. From throughput point of view, Cu-Cu bonding is challenging as bonding profile involves long heating duration and high temperature. In this paper, we explore the method to improve the bonding throughput and improve interconnect formation. A novel Cu pillar structure is proposed with center core Cu pillar surrounded by side-wall layer solder. Such Cu pillar array is bonded on a bottom wafer with Cu pads through chip-to-wafer (C2W) method. Study shows the solder located at side-wall offers an assist of temporary tacking the chip on the wafer. Then the entire interconnect forms joint through the use of gang bonder. As the side-wall solder seals individual Cu pillar to corresponding bond pad, it helps to prevent non-contact or void interconnection in pillar array. With the tacking and gang bonding process, a higher throughput process can be realized and actively adopted by industry as it offers lower cost of assembly.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"1572-1577"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72572648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Poliks, Yilin Sung, J. Lombardi, Robert Malay, Jeremiah M. Dederick, C. Westgate, Ming-Huang Huang, S. Garner, S. Pollard, C. Daly
Efficient antennas were achieved at 2.4 GHz and 5.8 GHz in which a transparent conductor, ITO, was deposited on only one side of the glass through sputtering. Antenna structures including grid, loop, and split ring monopoles were also designed and tested. An ITO layer of 650 nm was needed to consistently maintain a sheet resistance of 10 ohms/square or less to reduce antenna losses. A 100 nm aluminum doped silicon dioxide layer was deposited to buffer the ITO from the flexible glass to ensure high conductivity, and photolithography was used to define the antennas followed by an annealing process to improve the ITO conductivity and transparency. A packaging technique using 3D printed frames, Corning® GPPO connectors, and conducting epoxies yielded good antenna performance in terms of radiation efficiency and mismatch loss. Good agreement between simulations and measurements for packaged devices was obtained. Examples of antenna packaging, measurement results, and performance are presented.
{"title":"Transparent Antennas for Wireless Systems Based on Patterned Indium Tin Oxide and Flexible Glass","authors":"M. Poliks, Yilin Sung, J. Lombardi, Robert Malay, Jeremiah M. Dederick, C. Westgate, Ming-Huang Huang, S. Garner, S. Pollard, C. Daly","doi":"10.1109/ECTC.2017.314","DOIUrl":"https://doi.org/10.1109/ECTC.2017.314","url":null,"abstract":"Efficient antennas were achieved at 2.4 GHz and 5.8 GHz in which a transparent conductor, ITO, was deposited on only one side of the glass through sputtering. Antenna structures including grid, loop, and split ring monopoles were also designed and tested. An ITO layer of 650 nm was needed to consistently maintain a sheet resistance of 10 ohms/square or less to reduce antenna losses. A 100 nm aluminum doped silicon dioxide layer was deposited to buffer the ITO from the flexible glass to ensure high conductivity, and photolithography was used to define the antennas followed by an annealing process to improve the ITO conductivity and transparency. A packaging technique using 3D printed frames, Corning® GPPO connectors, and conducting epoxies yielded good antenna performance in terms of radiation efficiency and mismatch loss. Good agreement between simulations and measurements for packaged devices was obtained. Examples of antenna packaging, measurement results, and performance are presented.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"77 1","pages":"1443-1448"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78692939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, the pumping behaviors of copper filler from TSV were systematically investigated. First, in-situ observation of copper pumping from TSV was conducted in scanning electronic microscope (SEM), the pumping height of copper filler and its evolution with time and temperature was recorded, it is found that the pumping rate increase with temperature and the maximum pumping height reached 12 µm. Second, the micro-mechanism of copper pumping was experimentally investigated with the aid of acoustic emission (AE) system, it was found that mass diffusion controlled creep deformation of interface should be the main mechanism copper pumping. Based on these experimental results and some reasonable assumptions, a theoretical model and its corresponding calculation algorithm were developed. After comparison with the known results about shear stress distribution along the TSV interface, the verified model was applied to predict the pumping height of TSV and qualitative consistence was obtained, possible sources of error were analyzed.
{"title":"Investigations on the Pumping Behaviors of Copper Filler in Through-Silicon-vias (TSV)","authors":"F. Su, R. Yao","doi":"10.1109/ECTC.2017.24","DOIUrl":"https://doi.org/10.1109/ECTC.2017.24","url":null,"abstract":"In this paper, the pumping behaviors of copper filler from TSV were systematically investigated. First, in-situ observation of copper pumping from TSV was conducted in scanning electronic microscope (SEM), the pumping height of copper filler and its evolution with time and temperature was recorded, it is found that the pumping rate increase with temperature and the maximum pumping height reached 12 µm. Second, the micro-mechanism of copper pumping was experimentally investigated with the aid of acoustic emission (AE) system, it was found that mass diffusion controlled creep deformation of interface should be the main mechanism copper pumping. Based on these experimental results and some reasonable assumptions, a theoretical model and its corresponding calculation algorithm were developed. After comparison with the known results about shear stress distribution along the TSV interface, the verified model was applied to predict the pumping height of TSV and qualitative consistence was obtained, possible sources of error were analyzed.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"100 1","pages":"2073-2079"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77366916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Qidong Wang, Alexander D. Rider, D. Moore, Charles P. Blakemore, Liqiang Cao, G. Gratta
A density staggered cantilever was developed to measure the micron length gravity between itself and an optically levitated microsphere in high vacuum. The cantilever, has two main density contrasted materials gold(19.3g/cm3) and silicon(2.33g/cm3), where each of the material is finger-shaped and stagger placed next to each other, constitute an integral finger array on the device layer of SOI wafer. The scallop of the DRIE defined fingers was optimized to be less than 50nm to reduce the surface variation between the cantilever and levitated microsphere. The end of each fingers were covered with 2-10um silicon and gold to shield the undesired charged particles. The back side of SOI wafer were defined with DRIE to release the cantilever. The Cantilever will be placed microns away from the microsphere and mechanically move back and forth to interact with the microsphere. This paper introduces the design, manufacturing of the density staggered cantilever for micron length gravity.
{"title":"A Density Staggered Cantilever for Micron Length Gravity Probing","authors":"Qidong Wang, Alexander D. Rider, D. Moore, Charles P. Blakemore, Liqiang Cao, G. Gratta","doi":"10.1109/ECTC.2017.274","DOIUrl":"https://doi.org/10.1109/ECTC.2017.274","url":null,"abstract":"A density staggered cantilever was developed to measure the micron length gravity between itself and an optically levitated microsphere in high vacuum. The cantilever, has two main density contrasted materials gold(19.3g/cm3) and silicon(2.33g/cm3), where each of the material is finger-shaped and stagger placed next to each other, constitute an integral finger array on the device layer of SOI wafer. The scallop of the DRIE defined fingers was optimized to be less than 50nm to reduce the surface variation between the cantilever and levitated microsphere. The end of each fingers were covered with 2-10um silicon and gold to shield the undesired charged particles. The back side of SOI wafer were defined with DRIE to release the cantilever. The Cantilever will be placed microns away from the microsphere and mechanically move back and forth to interact with the microsphere. This paper introduces the design, manufacturing of the density staggered cantilever for micron length gravity.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"9 3 1","pages":"1773-1778"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77564028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the multiscale approach for investigating the new deformation and failure mechanisms including such deformation modes as single crystal slips and texture evolution as sub-grains and recrystallization. Failure criteria from microvoids and microcracks shall be embedded into constitutive equations for the power of failure process visualization. The constitutive framework developed by the first author for solder alloys has been furthermore advanced into the multiscale constitutive framework with damage evolution and failure criteria. The investigation is focus on the anisotropic and viscoplastic constitutive framework with texture evolution for tin-based lead-free solders. It is found that the ancient material is still challenging concurrent constitutive modeling and reliability of microscale lead-free solder joints.
{"title":"Anisotropic and Multiscale Constitutive Framework for the Reliability of Microscale Interconnects Based on Damage Mechanics","authors":"Z. Qian, Hongtao Chen","doi":"10.1109/ECTC.2017.305","DOIUrl":"https://doi.org/10.1109/ECTC.2017.305","url":null,"abstract":"This paper presents the multiscale approach for investigating the new deformation and failure mechanisms including such deformation modes as single crystal slips and texture evolution as sub-grains and recrystallization. Failure criteria from microvoids and microcracks shall be embedded into constitutive equations for the power of failure process visualization. The constitutive framework developed by the first author for solder alloys has been furthermore advanced into the multiscale constitutive framework with damage evolution and failure criteria. The investigation is focus on the anisotropic and viscoplastic constitutive framework with texture evolution for tin-based lead-free solders. It is found that the ancient material is still challenging concurrent constitutive modeling and reliability of microscale lead-free solder joints.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"65 1","pages":"1051-1057"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80055642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Lin, C. Ko, W. Ho, Chi-Hai Kuo, Kuan-Wen Chen, Yu-Hua Chen, T. Tseng
Rapid development of semiconductor technology and multi-function demands of end products has driven IC foundry industry toward 7nm node process, and even next generation of 5nm. The I/O pitch of chip is reduced accordingly but the build-up layer of IC carrier is still too large to fit interconnects. In order to overcome the gap of I/O pitch between IC chip and carrier, the interposer technology has been considered as a solution to resolve the issue. However, the cost of silicon interposer is too high, and the glass interposer lacks the associated infrastructure and is difficult to be handled, which makes a technology drawback for market applications. Alternatively, fan-out wafer/panel level package technology is getting more attractions for advanced package recently because of its features of low profile, small form factor, and high bandwidth with fine line re-distribution layer (RDL) routability. There are lots of literatures addressing about the residual stress and warpage mostly on wafer level fan-out technology, especially for chip-first technology scheme. However, comprehensive study on the panel level fan-out is not mature yet. This paper investigates fundamental factors that impact the residual stress and warpage level of panel level fan-out package, such as metal layer counts, thickness of dielectric and metal layer, coefficient of thermal expansion (CTE) and Young's modulus of dielectric and molding compound, molding gap and molding process temperature, etc. In this study, a RDL-first (chip-last) fan-out panel level structure of three metal layers on releasing film molded with epoxy compound was established as a simulation model by means of finite element analysis software. The simulation results provide a guideline of design rules for fabricating multi-layer RDL panel level fan-out package and making the minimum residual stress while chip assembly. Fabrication of three-layer dielectric panel level fan-out, where 370mmx470mm panel size is applied, is also demonstrated to compare with the simulation results.
{"title":"A Comprehensive Study on Stress and Warpage by Design, Simulation and Fabrication of RDL-First Panel Level Fan-Out Technology for Advanced Package","authors":"P. Lin, C. Ko, W. Ho, Chi-Hai Kuo, Kuan-Wen Chen, Yu-Hua Chen, T. Tseng","doi":"10.1109/ECTC.2017.106","DOIUrl":"https://doi.org/10.1109/ECTC.2017.106","url":null,"abstract":"Rapid development of semiconductor technology and multi-function demands of end products has driven IC foundry industry toward 7nm node process, and even next generation of 5nm. The I/O pitch of chip is reduced accordingly but the build-up layer of IC carrier is still too large to fit interconnects. In order to overcome the gap of I/O pitch between IC chip and carrier, the interposer technology has been considered as a solution to resolve the issue. However, the cost of silicon interposer is too high, and the glass interposer lacks the associated infrastructure and is difficult to be handled, which makes a technology drawback for market applications. Alternatively, fan-out wafer/panel level package technology is getting more attractions for advanced package recently because of its features of low profile, small form factor, and high bandwidth with fine line re-distribution layer (RDL) routability. There are lots of literatures addressing about the residual stress and warpage mostly on wafer level fan-out technology, especially for chip-first technology scheme. However, comprehensive study on the panel level fan-out is not mature yet. This paper investigates fundamental factors that impact the residual stress and warpage level of panel level fan-out package, such as metal layer counts, thickness of dielectric and metal layer, coefficient of thermal expansion (CTE) and Young's modulus of dielectric and molding compound, molding gap and molding process temperature, etc. In this study, a RDL-first (chip-last) fan-out panel level structure of three metal layers on releasing film molded with epoxy compound was established as a simulation model by means of finite element analysis software. The simulation results provide a guideline of design rules for fabricating multi-layer RDL panel level fan-out package and making the minimum residual stress while chip assembly. Fabrication of three-layer dielectric panel level fan-out, where 370mmx470mm panel size is applied, is also demonstrated to compare with the simulation results.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"32 1","pages":"1413-1418"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85103840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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