Tae-Ryong Kim, Kisu Joo, B. Lim, Sung-Soon Choi, B. Lee, E. Yoon, Se Young Jeong, M. Yim
In this study, we investigated the correlation between thermal conductivity and insulative shell thickness of SiO2 coated Ag (SCA) particles for the thermal filler material in the high performance underfill with focus on improved thermal conductivity. We synthesized the coating of various SiO2 insulation layer on the surface of spherical Ag powder and used them for underfill material formulation to achieve >2 W/mK grade high thermal conductivity capillary underfill. In order to achieve powder distribution with gaussian curve additional spherical alumina was mixed with SCA powder. This mixture blended with epoxy based multifunctional resin matrix. Trend profiling of thermal conductivity and electrical resistivity as a function of SiO2 shell thickness were performed. In addition, correlation of thermal conductivity and viscosity were investigated. Resulting capillary underfill with SCA powders showed 2.14 W/mK thermal conductivity and passed thermal cycling test corresponding to JEDEC LEVEL 3.
{"title":"Enhanced Thermal Conductivity of the Underfill Materials Using Insulated Core/shell Filler Particles for High Performance Flip Chip Applications","authors":"Tae-Ryong Kim, Kisu Joo, B. Lim, Sung-Soon Choi, B. Lee, E. Yoon, Se Young Jeong, M. Yim","doi":"10.1109/ECTC.2017.196","DOIUrl":"https://doi.org/10.1109/ECTC.2017.196","url":null,"abstract":"In this study, we investigated the correlation between thermal conductivity and insulative shell thickness of SiO2 coated Ag (SCA) particles for the thermal filler material in the high performance underfill with focus on improved thermal conductivity. We synthesized the coating of various SiO2 insulation layer on the surface of spherical Ag powder and used them for underfill material formulation to achieve >2 W/mK grade high thermal conductivity capillary underfill. In order to achieve powder distribution with gaussian curve additional spherical alumina was mixed with SCA powder. This mixture blended with epoxy based multifunctional resin matrix. Trend profiling of thermal conductivity and electrical resistivity as a function of SiO2 shell thickness were performed. In addition, correlation of thermal conductivity and viscosity were investigated. Resulting capillary underfill with SCA powders showed 2.14 W/mK thermal conductivity and passed thermal cycling test corresponding to JEDEC LEVEL 3.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"84 1","pages":"1340-1347"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77142541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this report, the prototype of micro-supercapacitor (MSC) arrays based on the art of paper folding (Miura folding) were demonstrated as foldable and miniaturized energy storage components. The Miura folding is a method to fold a flat surface into crease patterns consisting of parallelograms with smaller areas. Here each MSC unit was made by deposition of conductive graphene sheets followed by plasma etching to form the interdigitated patterns. The single MSC unit delivered a large areal capacitance of 1.5 mF/cm2 with excellent power handling capability. The foldable MSC arrays consisting of 3×2 patterns were connected via combinations of series and parallel configurations. The folded MSCs showed ~4.3 times increase in areal capacitance with improved energy densities.
{"title":"Design of Miura Folding-Based Micro-Supercapacitors as Foldable and Miniaturized Energy Storage Devices","authors":"B. Song, Yun Chen, K. Moon, C. Wong","doi":"10.1109/ECTC.2017.150","DOIUrl":"https://doi.org/10.1109/ECTC.2017.150","url":null,"abstract":"In this report, the prototype of micro-supercapacitor (MSC) arrays based on the art of paper folding (Miura folding) were demonstrated as foldable and miniaturized energy storage components. The Miura folding is a method to fold a flat surface into crease patterns consisting of parallelograms with smaller areas. Here each MSC unit was made by deposition of conductive graphene sheets followed by plasma etching to form the interdigitated patterns. The single MSC unit delivered a large areal capacitance of 1.5 mF/cm2 with excellent power handling capability. The foldable MSC arrays consisting of 3×2 patterns were connected via combinations of series and parallel configurations. The folded MSCs showed ~4.3 times increase in areal capacitance with improved energy densities.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"42 1","pages":"2027-2032"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85698707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yong Han, B. L. Lau, G. Tang, Seow Meng Low, J. Goh
The Si micro-fluid cooler, combining micro-jet array impingement, micro-channel flow and micro-trench drainage, has been designed and experimentally evaluated. Enhanced jet array impingement has been achieved by eliminating the negative cross-flow effect among adjacent nozzles. Low thermal resistance
{"title":"Package-Level Si Micro-Fluid Cooler with Enhanced Jet Array for High Performance 3D Systems","authors":"Yong Han, B. L. Lau, G. Tang, Seow Meng Low, J. Goh","doi":"10.1109/ECTC.2017.42","DOIUrl":"https://doi.org/10.1109/ECTC.2017.42","url":null,"abstract":"The Si micro-fluid cooler, combining micro-jet array impingement, micro-channel flow and micro-trench drainage, has been designed and experimentally evaluated. Enhanced jet array impingement has been achieved by eliminating the negative cross-flow effect among adjacent nozzles. Low thermal resistance","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"1654-1659"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87968330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Silver (Ag) has been emerging as an attractive die-attach material for high power devices because of its highest thermal conductivity among metals and high melting stability. The most well-known silver die-attach technique is to sinter micro-or nano-silver pastes. The challenging issues of sintered Ag joints are pores in the joint and migration of unfriendly species such as chlorine ions through these pores. In this paper, a novel Ag die-attach technique using foils is reported. The foils are fabricated in house using many runs of cold rolling and subsequent annealing. Annealing is needed to establish favorable microstructure. X-ray diffraction (XRD) is carried out to reveal the crystallographic information. Solid-state bonding is conducted in 0.1 torr vacuum at 300 °C assisted by low applied pressure (1,000 psi). This pressure is several orders of magnitude lower than what used in conventional thermal compression bonding. The Si/Ag/Cu structure, where Ag is the foil, is bonded in one step to achieve two bonding interfaces. Prior to bonding, Si is metallized with thin Cr and Au layers. Cross section SEM images show that there are no large voids and cracks in the interfacial regions. The Ag region is a dense pure silver layer without any foreign substances. Regardless of significant coefficient of thermal expansion (CTE) mismatch between silicon and copper, the bonded samples do not crack after cooling down to room temperature. This indicates that the ductile Ag layer is able to manage the stress produced by the CTE mismatch. The new Ag die-attach method produces joints of lowest possible thermal resistance and extremely high operation temperature. It should be very valuable to high power and high temperature electronics and photonics.
{"title":"Low Pressure Solid-State Bonding Using Silver Preforms for High Power Device Packaging","authors":"Jiaqi Wu, Chin C. Lee","doi":"10.1109/ECTC.2017.192","DOIUrl":"https://doi.org/10.1109/ECTC.2017.192","url":null,"abstract":"Silver (Ag) has been emerging as an attractive die-attach material for high power devices because of its highest thermal conductivity among metals and high melting stability. The most well-known silver die-attach technique is to sinter micro-or nano-silver pastes. The challenging issues of sintered Ag joints are pores in the joint and migration of unfriendly species such as chlorine ions through these pores. In this paper, a novel Ag die-attach technique using foils is reported. The foils are fabricated in house using many runs of cold rolling and subsequent annealing. Annealing is needed to establish favorable microstructure. X-ray diffraction (XRD) is carried out to reveal the crystallographic information. Solid-state bonding is conducted in 0.1 torr vacuum at 300 °C assisted by low applied pressure (1,000 psi). This pressure is several orders of magnitude lower than what used in conventional thermal compression bonding. The Si/Ag/Cu structure, where Ag is the foil, is bonded in one step to achieve two bonding interfaces. Prior to bonding, Si is metallized with thin Cr and Au layers. Cross section SEM images show that there are no large voids and cracks in the interfacial regions. The Ag region is a dense pure silver layer without any foreign substances. Regardless of significant coefficient of thermal expansion (CTE) mismatch between silicon and copper, the bonded samples do not crack after cooling down to room temperature. This indicates that the ductile Ag layer is able to manage the stress produced by the CTE mismatch. The new Ag die-attach method produces joints of lowest possible thermal resistance and extremely high operation temperature. It should be very valuable to high power and high temperature electronics and photonics.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"31 1","pages":"2002-2007"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88213507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Flip-chip bonding has become an efficient method to realize fine-pitch interconnection in high density interconnection applications. Thermal-compression bonding of Cu/Sn microbumps can induce extra thermal stress because of high bonding temperature, long bonding time and high bonding force. Temperature, time and force are expected to be decreased to improve the thermal-mechanical reliability of the integration systems. In this work, low-temperature ultrasonic bonding of Cu/Sn microbumps with a thin layer of gold was studied. We also studied bonding of redistribution layers (RDLs) that consisted of electrodeposited copper and a thin layer of gold. The feasibility of the low-temperature ultrasonic bonding was demonstrated through the preliminary experimental results. Cu/Sn microbumps with Au layer were successfully bonded through a quick bonding process and a followed annealing process. However, in the case of bonding of the RDLs, the cross-section of some bonded RDLs showed that cracks existed at the interface of Au/Au layers, which resulted from the uneven surface. The electrodeposition process needs improving to get a flatter surface and the parameters of the bonding process still needs to be optimized.
{"title":"Low-Temperature Ultrasonic Bonding of Cu/Sn Microbumps with Au Layer for High Density Interconnection Applications","authors":"Qinghua Zeng, Y. Guan, J. Chen, Yufeng Jin","doi":"10.1109/ECTC.2017.217","DOIUrl":"https://doi.org/10.1109/ECTC.2017.217","url":null,"abstract":"Flip-chip bonding has become an efficient method to realize fine-pitch interconnection in high density interconnection applications. Thermal-compression bonding of Cu/Sn microbumps can induce extra thermal stress because of high bonding temperature, long bonding time and high bonding force. Temperature, time and force are expected to be decreased to improve the thermal-mechanical reliability of the integration systems. In this work, low-temperature ultrasonic bonding of Cu/Sn microbumps with a thin layer of gold was studied. We also studied bonding of redistribution layers (RDLs) that consisted of electrodeposited copper and a thin layer of gold. The feasibility of the low-temperature ultrasonic bonding was demonstrated through the preliminary experimental results. Cu/Sn microbumps with Au layer were successfully bonded through a quick bonding process and a followed annealing process. However, in the case of bonding of the RDLs, the cross-section of some bonded RDLs showed that cracks existed at the interface of Au/Au layers, which resulted from the uneven surface. The electrodeposition process needs improving to get a flatter surface and the parameters of the bonding process still needs to be optimized.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"87 1","pages":"1894-1899"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86764511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Colloidal quantum dots (QDs) applied in illuminants and displays have been offered great prospects due to their narrow and tunable emission bands. However, the QD's incompatibility to encapsulant and sensitivities to oxygen and moisture are still limiting their performance in white light emitting diode (WLED). In this research, we have developed a new kind of QDs composites as QDs luminescent microspheres (QLMS). QLMS is a new kind of highly robust QD composite featuring of high efficiency, narrow FWHM and excellent long-term operation stability. QLMS is fully compatible with current LED packaging process and can be used as phosphors for direct On-Chip applications. QLMS provide a promising way for QDs-optimized WLED with high efficiency, color rendering and stability.
{"title":"Highly Efficient and Stable Quantum Dot Light Emitting Diodes Optimized by Micro-Packaged Luminescent Microspheres","authors":"Kai Wang, Xiaobing Luo, Sheng Liu, X. W. Sun","doi":"10.1109/ECTC.2017.74","DOIUrl":"https://doi.org/10.1109/ECTC.2017.74","url":null,"abstract":"Colloidal quantum dots (QDs) applied in illuminants and displays have been offered great prospects due to their narrow and tunable emission bands. However, the QD's incompatibility to encapsulant and sensitivities to oxygen and moisture are still limiting their performance in white light emitting diode (WLED). In this research, we have developed a new kind of QDs composites as QDs luminescent microspheres (QLMS). QLMS is a new kind of highly robust QD composite featuring of high efficiency, narrow FWHM and excellent long-term operation stability. QLMS is fully compatible with current LED packaging process and can be used as phosphors for direct On-Chip applications. QLMS provide a promising way for QDs-optimized WLED with high efficiency, color rendering and stability.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"25 1","pages":"2129-2132"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89126925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Given the recent interest in power delivery design for the Internet of Things (IoT), current work aims to design a packaged power delivery solution for IoT. The power inductor takes up a large amount of the area in such an implementation. Planar power inductors are preferred for fabrication simplicity and cost. However, air core inductors do not have sufficient area efficiency for IoT solutions, necessitating the integration of a magnetic core on a planar inductor. This research demonstrates a low cost method of miniaturizing planar inductors using stencil printing technique with a magnetic composite for embedded power inductors for IoT edge device applications. Planar spiral inductors of varying dimensions and inductances are designed using a full wave EM solver. Inductors are then fabricated on FR4 using standard printed wiring board process. NiZn is a low loss magnetic material and is mixed with an epoxy and solvent to facilitate stencil printing. Stencil printing is a low cost fabrication method with great utility to electronic packaging. A single layer of NiZn is screen printed as squares directly on the fabricated spiral inductors. Measurements are performed using a vector network analyzer at frequencies between 10 and 50 MHz. The measured inductance of the inductors ranges from 37 nH-340 nH without NiZn to 42 nH-452 nH with a single NiZn layer at the operating frequencies. In addition, the Q factor is actually improved at the frequency of operation, as the inductance gained from the magnetic layer is more significant than the loss incurred. This increase in inductance leads to great potential for decrease of size of packaged inductors.
{"title":"Miniaturization of Planar Packaged Inductor Using NiZn and Low Cost Screen Printing Technique","authors":"C. Pardue, M. Bellaredj, A. Davis, M. Swaminathan","doi":"10.1109/ECTC.2017.183","DOIUrl":"https://doi.org/10.1109/ECTC.2017.183","url":null,"abstract":"Given the recent interest in power delivery design for the Internet of Things (IoT), current work aims to design a packaged power delivery solution for IoT. The power inductor takes up a large amount of the area in such an implementation. Planar power inductors are preferred for fabrication simplicity and cost. However, air core inductors do not have sufficient area efficiency for IoT solutions, necessitating the integration of a magnetic core on a planar inductor. This research demonstrates a low cost method of miniaturizing planar inductors using stencil printing technique with a magnetic composite for embedded power inductors for IoT edge device applications. Planar spiral inductors of varying dimensions and inductances are designed using a full wave EM solver. Inductors are then fabricated on FR4 using standard printed wiring board process. NiZn is a low loss magnetic material and is mixed with an epoxy and solvent to facilitate stencil printing. Stencil printing is a low cost fabrication method with great utility to electronic packaging. A single layer of NiZn is screen printed as squares directly on the fabricated spiral inductors. Measurements are performed using a vector network analyzer at frequencies between 10 and 50 MHz. The measured inductance of the inductors ranges from 37 nH-340 nH without NiZn to 42 nH-452 nH with a single NiZn layer at the operating frequencies. In addition, the Q factor is actually improved at the frequency of operation, as the inductance gained from the magnetic layer is more significant than the loss incurred. This increase in inductance leads to great potential for decrease of size of packaged inductors.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"3 1","pages":"2275-2281"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83503387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Honda, N. Suzuki, T. Nonaka, H. Noma, Yoshinobu Ozaki
The novel expanding film and the process have been developed for the fabrication of 5 sides protection of die and fan out wafer level package. This can skip the time-consuming die-replacement process for die gap widening. The process consists of the steps of expanding of diced-wafer on the film, transferring the dice to the carrier, over-molding and mold dicing. Every die edge protection by molding compound and the singulation was demonstrated. The die gap was able to be controlled from 0.5 mm to 3.5 mm. In the case of 1.5 mm die gap, the standard deviation was about 0.05 mm. It was also indicated that the film could be applied for 1 mm × 1 mm, 5 mm × 5 mm and 10 mm × 10 mm size dice.
开发了一种新型的扩展膜和工艺，可用于制造五面保护的模具和扇形圆片级封装。这可以跳过耗时的模具更换过程，以扩大模具间隙。该工艺包括在薄膜上展开晶片、将晶片转移到载体上、复模和模切等步骤。对各种成型复合材料对模具边缘的保护及仿真进行了论证。模具间隙可以控制在0.5 mm到3.5 mm之间。在模具间隙为1.5 mm的情况下，标准差约为0.05 mm。该薄膜可应用于1 mm × 1 mm、5 mm × 5 mm和10 mm × 10 mm尺寸的薄片。
{"title":"Expanding Film and Process for High Efficiency 5 Sides Protection and FO-WLP Fabrication","authors":"K. Honda, N. Suzuki, T. Nonaka, H. Noma, Yoshinobu Ozaki","doi":"10.1109/ECTC.2017.293","DOIUrl":"https://doi.org/10.1109/ECTC.2017.293","url":null,"abstract":"The novel expanding film and the process have been developed for the fabrication of 5 sides protection of die and fan out wafer level package. This can skip the time-consuming die-replacement process for die gap widening. The process consists of the steps of expanding of diced-wafer on the film, transferring the dice to the carrier, over-molding and mold dicing. Every die edge protection by molding compound and the singulation was demonstrated. The die gap was able to be controlled from 0.5 mm to 3.5 mm. In the case of 1.5 mm die gap, the standard deviation was about 0.05 mm. It was also indicated that the film could be applied for 1 mm × 1 mm, 5 mm × 5 mm and 10 mm × 10 mm size dice.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"28 1","pages":"331-336"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84639384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
David C. Woodrum, M. Nasr, Xuchen Zhang, M. Bakir, S. Sitaraman
As power demands for microelectronic devices continue to rise, new techniques for heat dissipation require innovative fabrication solutions such as on-chip cooling methods. The mechanical reliability of these high-powered, high-pressure systems is particularly sensitive to the interfacial strengths within the microelectronic architectures. In research at Georgia Tech, on-chip cooling methodologies involve cooling of devices with high-pressure coolant which is pumped through a microchannel. The microchannels are etched directly into a silicon wafer and then capped by a second wafer of pyrex glass. When fluid flows through the system, internal pressures can exceed 2000 kPa in certain locations of the microchannel. Overall system failure due to cracking of the brittle materials is of particular interest given the potential for catastrophic crack propagation. Using a combination of experiments and modeling, a methodology for predicting interfacial and cohesive strength of the silicon-glass bonded microchannel system has been developed. The objective of this work is to demonstrate the results of the experimental test technique and to extract appropriate silicon-glass interfacial test data in conjunction with numerical modeling of the fracture conditions.
{"title":"Mechanical Characterization of Anodic Bonding Using Chevron Microchannel","authors":"David C. Woodrum, M. Nasr, Xuchen Zhang, M. Bakir, S. Sitaraman","doi":"10.1109/ECTC.2017.335","DOIUrl":"https://doi.org/10.1109/ECTC.2017.335","url":null,"abstract":"As power demands for microelectronic devices continue to rise, new techniques for heat dissipation require innovative fabrication solutions such as on-chip cooling methods. The mechanical reliability of these high-powered, high-pressure systems is particularly sensitive to the interfacial strengths within the microelectronic architectures. In research at Georgia Tech, on-chip cooling methodologies involve cooling of devices with high-pressure coolant which is pumped through a microchannel. The microchannels are etched directly into a silicon wafer and then capped by a second wafer of pyrex glass. When fluid flows through the system, internal pressures can exceed 2000 kPa in certain locations of the microchannel. Overall system failure due to cracking of the brittle materials is of particular interest given the potential for catastrophic crack propagation. Using a combination of experiments and modeling, a methodology for predicting interfacial and cohesive strength of the silicon-glass bonded microchannel system has been developed. The objective of this work is to demonstrate the results of the experimental test technique and to extract appropriate silicon-glass interfacial test data in conjunction with numerical modeling of the fracture conditions.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"6 1","pages":"1646-1653"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89379936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Nagashima, T. Uemura, A. Izawa, Y. Ishikawa, H. Nasu
We demonstrate >1.3-Tb/s VCSEL-based on-board optical module for high-density optical interconnects. The optical module integrates 28-Gb/s × 24-channel transmitter and receiver into one package of 1-inch^2 footprint. Subsequently, the total data rate is as high as 1.34 Tb/s. As investigated the temperature distributions of an optical module in calculation and experiment, an operating case temperature of optical module is lower than the maximum case temperature of 70 degree C in a practical air-cooling environment with the total power consumption of 9.1 W when activating all CDR circuitries as the harshest condition. The module exhibits a total jitter margin of 0.48 U. I. at a BER of 10^-12 when operated by a 28.05-Gb/s NRZ PRBS bit stream for each channel. By bypassing CDR circuitries with a capable length of electrical transmission line of 30 mm, a jitter margin was degraded to 0.21 U. I. at a case temperature of 70 degree C. If a system accepts such a level of jitter margin, the total power consumption can be suppressed to 6.0 W and an operating case temperature can be decreased accordingly.
{"title":"A Very High-Dense on-Board Optical Module Realizing >1.3 Tb/s/Inch ^2","authors":"K. Nagashima, T. Uemura, A. Izawa, Y. Ishikawa, H. Nasu","doi":"10.1109/ECTC.2017.213","DOIUrl":"https://doi.org/10.1109/ECTC.2017.213","url":null,"abstract":"We demonstrate >1.3-Tb/s VCSEL-based on-board optical module for high-density optical interconnects. The optical module integrates 28-Gb/s × 24-channel transmitter and receiver into one package of 1-inch^2 footprint. Subsequently, the total data rate is as high as 1.34 Tb/s. As investigated the temperature distributions of an optical module in calculation and experiment, an operating case temperature of optical module is lower than the maximum case temperature of 70 degree C in a practical air-cooling environment with the total power consumption of 9.1 W when activating all CDR circuitries as the harshest condition. The module exhibits a total jitter margin of 0.48 U. I. at a BER of 10^-12 when operated by a 28.05-Gb/s NRZ PRBS bit stream for each channel. By bypassing CDR circuitries with a capable length of electrical transmission line of 30 mm, a jitter margin was degraded to 0.21 U. I. at a case temperature of 70 degree C. If a system accepts such a level of jitter margin, the total power consumption can be suppressed to 6.0 W and an operating case temperature can be decreased accordingly.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"14 1","pages":"532-537"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87406490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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