A. Garnier, L. Arnaud, R. Franiatte, A. Toffoli, S. Moreau, F. Bana, S. Chéramy
Microbump-based interconnects with 20 µm pitch have been fabricated on 300 mm wafers using industrial tools. Good processes control enables to get narrow standard deviations for the microbumps height (0.2 µm) and diameter (0.4 µm). Assembly was studied with chip to wafer (CtW) test vehicles by either mass reflow (MR) or thermo-compression (TC) with or without non-conductive paste (NCP). MR and TC processes result in suitable CtW alignments without significant defects at bonding interface. TC NCP assembly suffers from larger misalignment and underfill entrapment, reducing top to bottom bonding section. Consequently, unit electrical resistance is lower for MR and TC processes with ~25 m ascribed to pure vertical link, than for TC NCP process exhibiting ~50 m vertical link with larger standard deviation (15 m versus 2 m). Intermetallic compounds have been studied and Ni3Sn4 proves to be the main contributor for electrical resistance in our configuration where SnAg is sandwiched between 2 Ni layers. Electrical yield measured on daisy chains is very good (close to or higher than 90%) for MR or TC, even on more than 20,000 interconnects. For TC NCP, electrical yield remains to be improved, particularly on large daisy chains. Finally, an original electrical test has been designed and successfully implemented to characterize top to bottom misalignment. These results are promising for future high performance computing products that would require 20 µm pitch microbumps.
{"title":"Electrical Performance of High Density 10 µm Diameter 20 µm Pitch Cu-Pillar with Chip to Wafer Assembly","authors":"A. Garnier, L. Arnaud, R. Franiatte, A. Toffoli, S. Moreau, F. Bana, S. Chéramy","doi":"10.1109/ECTC.2017.38","DOIUrl":"https://doi.org/10.1109/ECTC.2017.38","url":null,"abstract":"Microbump-based interconnects with 20 µm pitch have been fabricated on 300 mm wafers using industrial tools. Good processes control enables to get narrow standard deviations for the microbumps height (0.2 µm) and diameter (0.4 µm). Assembly was studied with chip to wafer (CtW) test vehicles by either mass reflow (MR) or thermo-compression (TC) with or without non-conductive paste (NCP). MR and TC processes result in suitable CtW alignments without significant defects at bonding interface. TC NCP assembly suffers from larger misalignment and underfill entrapment, reducing top to bottom bonding section. Consequently, unit electrical resistance is lower for MR and TC processes with ~25 m ascribed to pure vertical link, than for TC NCP process exhibiting ~50 m vertical link with larger standard deviation (15 m versus 2 m). Intermetallic compounds have been studied and Ni3Sn4 proves to be the main contributor for electrical resistance in our configuration where SnAg is sandwiched between 2 Ni layers. Electrical yield measured on daisy chains is very good (close to or higher than 90%) for MR or TC, even on more than 20,000 interconnects. For TC NCP, electrical yield remains to be improved, particularly on large daisy chains. Finally, an original electrical test has been designed and successfully implemented to characterize top to bottom misalignment. These results are promising for future high performance computing products that would require 20 µm pitch microbumps.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"82 1","pages":"999-1007"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91402536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As mobile and handheld devices become more functionalities, required to accommodate more frequency bands, and to meet small form factor requirements. IPD (Integrated Passive Device) offers small form factor, and high performance benefits for RF solutions. To achieve a high performance RF filters, high-Q inductor is a key factor. A possible best high-Q inductor can be achieved is by Glass based solenoid inductor. In addition, 3D IPD process is another approach to reduce package size and increase functionality. In this paper, the fabrication process of IPD, based on 8" glass wafer with Through Glass Via (TGV) to form the 3D solenoid inductor is presented. In addition, the process integration between wafer level, assembly, and double-sided process are addressed. Along the process integration, a RF ASIC is integrated through wafer level and assembly process to form the 3D integrated Wafer Level Chip Scale Package (WLCSP). The quality factor of 3D solenoid inductors can achieve Q of 70~100 in this study. The TGV and package reliability results are also discussed.
{"title":"Glass Based 3D-IPD Integrated RF ASIC in WLCSP","authors":"T. Lee, Yung-shun Chang, Che-Ming Hsu, Sheng-Chi Hsieh, Pao-Nan Lee, Yu-Chang Hsieh, Long-Ching Wang, Lijuan Zhang","doi":"10.1109/ECTC.2017.328","DOIUrl":"https://doi.org/10.1109/ECTC.2017.328","url":null,"abstract":"As mobile and handheld devices become more functionalities, required to accommodate more frequency bands, and to meet small form factor requirements. IPD (Integrated Passive Device) offers small form factor, and high performance benefits for RF solutions. To achieve a high performance RF filters, high-Q inductor is a key factor. A possible best high-Q inductor can be achieved is by Glass based solenoid inductor. In addition, 3D IPD process is another approach to reduce package size and increase functionality. In this paper, the fabrication process of IPD, based on 8\" glass wafer with Through Glass Via (TGV) to form the 3D solenoid inductor is presented. In addition, the process integration between wafer level, assembly, and double-sided process are addressed. Along the process integration, a RF ASIC is integrated through wafer level and assembly process to form the 3D integrated Wafer Level Chip Scale Package (WLCSP). The quality factor of 3D solenoid inductors can achieve Q of 70~100 in this study. The TGV and package reliability results are also discussed.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"76 1","pages":"631-636"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91531726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shreya Dwarakanath, P. Raj, Collen Z. Leng, V. Smet, M. Losego, V. Sundaram, R. Tummala
This paper demonstrates a new class of inorganic-organic hybrid dielectric materials to address the requirements for high-temperature reliability of next-generation high-density, high-power packages and electronics in harsh environments for automotive applications. A major concern for reliability is the inadequate adhesion of metals with high-temperature polymers. Adhesion deteriorates further via thermal and oxidative exposure and moisture absorption. In this paper, a novel vapor phase infiltration (VPI) technique is applied to create an organic-inorganic hybrid dielectric surface that improves metal-polymer adhesion. The VPI process infuses inorganic constituents to a depth of at least 3 microns, as revealed by elemental analysis using SEM-EDX and XPS depth profiles. In preliminary testing, Cu/Cr films deposited onto these modified polymer surfaces exhibit 3x higher peel strength than metal films deposited on untreated polymer.
{"title":"Infusing Inorganics into the Subsurface of Polymer Redistribution Layer Dielectrics for Improved Adhesion to Metals Interconnects","authors":"Shreya Dwarakanath, P. Raj, Collen Z. Leng, V. Smet, M. Losego, V. Sundaram, R. Tummala","doi":"10.1109/ECTC.2017.277","DOIUrl":"https://doi.org/10.1109/ECTC.2017.277","url":null,"abstract":"This paper demonstrates a new class of inorganic-organic hybrid dielectric materials to address the requirements for high-temperature reliability of next-generation high-density, high-power packages and electronics in harsh environments for automotive applications. A major concern for reliability is the inadequate adhesion of metals with high-temperature polymers. Adhesion deteriorates further via thermal and oxidative exposure and moisture absorption. In this paper, a novel vapor phase infiltration (VPI) technique is applied to create an organic-inorganic hybrid dielectric surface that improves metal-polymer adhesion. The VPI process infuses inorganic constituents to a depth of at least 3 microns, as revealed by elemental analysis using SEM-EDX and XPS depth profiles. In preliminary testing, Cu/Cr films deposited onto these modified polymer surfaces exhibit 3x higher peel strength than metal films deposited on untreated polymer.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"34 1","pages":"150-155"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90713887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Lall, Nakul Kothari, John Deep, J. Foley, Ryan Lowe
Electronic fuze assemblies may be exposed to harsh environments during prolonged storage, transport and deployment. Under exposure to storage-transport environmental loads including mechanical shock, temperature, vibration and humidity the fuze assemblies may sustain damage without any surface signs of visible degradation. Further, the operational environment requires survivability under high-g loads often in excess of 10,000g. The need for non-destructive test methods to allow for determination of the internal damage and the assessment of expected operational reliability under the presence of accrued damage from prolonged storage is extremely desirable. While a number of non-destructive test methods such as x-ray, and acoustic imaging exist in the state-of-art – they are limited to the acquisition of imaging of the internal damage state without the ability of conducting measurement of deformation under the action of environment loads. In this paper, a new method has been presented for the creation of the finite element models using x-ray micro-computed tomography data. Further, a method has been presented for measurement of internal deformation in fuze assemblies under the action of environment temperature gradients prior to and subsequent to exposure to operational mechanical shock using a combination of x-ray micro-computed tomography and digital volume correlation.
{"title":"Development of FE Models and Measurement of Internal Deformations of Fuze Electronics Using X-Ray MicroCT Data with Digital Volume Correlation","authors":"P. Lall, Nakul Kothari, John Deep, J. Foley, Ryan Lowe","doi":"10.1109/ECTC.2017.302","DOIUrl":"https://doi.org/10.1109/ECTC.2017.302","url":null,"abstract":"Electronic fuze assemblies may be exposed to harsh environments during prolonged storage, transport and deployment. Under exposure to storage-transport environmental loads including mechanical shock, temperature, vibration and humidity the fuze assemblies may sustain damage without any surface signs of visible degradation. Further, the operational environment requires survivability under high-g loads often in excess of 10,000g. The need for non-destructive test methods to allow for determination of the internal damage and the assessment of expected operational reliability under the presence of accrued damage from prolonged storage is extremely desirable. While a number of non-destructive test methods such as x-ray, and acoustic imaging exist in the state-of-art – they are limited to the acquisition of imaging of the internal damage state without the ability of conducting measurement of deformation under the action of environment loads. In this paper, a new method has been presented for the creation of the finite element models using x-ray micro-computed tomography data. Further, a method has been presented for measurement of internal deformation in fuze assemblies under the action of environment temperature gradients prior to and subsequent to exposure to operational mechanical shock using a combination of x-ray micro-computed tomography and digital volume correlation.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"497-506"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88802734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Tokunari, Koji Masuda, Hsiang-Han Hsu, T. Hisada, S. Nakagawa, R. Langlois, Patrick Jacques, P. Fortier
Assembly process reliability for Optical Multi-Chip Modules (MCM) is studied and improved. In the optoelectronic (OE) chip assembly for the Optical MCM, the OE chip with Au stud bump is joined with Sn-Ag-Cu (SAC) soldered in a through-waveguide via on an organic substrate to obtain high optical coupling efficiency. Since solid-liquid diffusion of Au to molten SAC is rapid, and formation of brittle intermetallic compounds such as AuSn4 is observed by an energy-dispersive X-ray analysis, and as a result the temperature and the dwell time for the chip assembly process should minimized. Furthermore, if OE chips are underfilled, resin could infiltrate into the total internal reflection mirror cavity, and it will not reflect anymore. On the other hand, Au - SAC joints are not mechanically stable without underfill because of a large thermal stress from the coefficient of thermal expansion mismatch between the OE chip and the optical waveguide-integrated organic substrate. The issue is solved by using sidefill encapsulation instead of underfill. Appropriate material selection of a high viscosity and high thixotropic index prevented infiltration under the chip. The effect of the sidefill process is verified by simulation and experimental results. The chip assembly with sidefill passes more than 1500 deep thermal cycles from -55 °C to 125 °C.
{"title":"Optoelectronic Chip Assembly Process of Optical MCM","authors":"M. Tokunari, Koji Masuda, Hsiang-Han Hsu, T. Hisada, S. Nakagawa, R. Langlois, Patrick Jacques, P. Fortier","doi":"10.1109/ECTC.2017.204","DOIUrl":"https://doi.org/10.1109/ECTC.2017.204","url":null,"abstract":"Assembly process reliability for Optical Multi-Chip Modules (MCM) is studied and improved. In the optoelectronic (OE) chip assembly for the Optical MCM, the OE chip with Au stud bump is joined with Sn-Ag-Cu (SAC) soldered in a through-waveguide via on an organic substrate to obtain high optical coupling efficiency. Since solid-liquid diffusion of Au to molten SAC is rapid, and formation of brittle intermetallic compounds such as AuSn4 is observed by an energy-dispersive X-ray analysis, and as a result the temperature and the dwell time for the chip assembly process should minimized. Furthermore, if OE chips are underfilled, resin could infiltrate into the total internal reflection mirror cavity, and it will not reflect anymore. On the other hand, Au - SAC joints are not mechanically stable without underfill because of a large thermal stress from the coefficient of thermal expansion mismatch between the OE chip and the optical waveguide-integrated organic substrate. The issue is solved by using sidefill encapsulation instead of underfill. Appropriate material selection of a high viscosity and high thixotropic index prevented infiltration under the chip. The effect of the sidefill process is verified by simulation and experimental results. The chip assembly with sidefill passes more than 1500 deep thermal cycles from -55 °C to 125 °C.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"95 1","pages":"545-550"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85889823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jinhui Li, Qiang Liu, Guoping Zhang, Bin Zhao, R. Sun, C. Wong
2.5D and 3D Integration technology using temporary bonding has become main stream in the semiconductor industry in recent years. However, thermal stability, low damage, and debonding at comparative low temperature are still areas of challenge. In this present study, a novel three-dimensional crosslinked polyurethane (3DPU) based on thermal reversible Diels-Alder chemistry, which can be used as temporary bonding adhesive to support wafer thinning and back side processes and be de-bonded by typical thermal-sliding method at comparatively low-temperature, has been developed. The crosslinked 3DPU showed high thermal stability and excellent adhesion strength both at room temperature and higher temperature. The adhesion strength of 3DPU decreased when the wafer pair was heat to the de-bonding temperature (150 oC) when the retro-DA reaction happened which guaranteed a low-temperature de-bonding process.
{"title":"Thermally Reversible and Crosslinked Polyurethane Based on Diels-Alder Chemistry for Ultrathin Wafer Temporary Bonding at Low-Temperature","authors":"Jinhui Li, Qiang Liu, Guoping Zhang, Bin Zhao, R. Sun, C. Wong","doi":"10.1109/ECTC.2017.295","DOIUrl":"https://doi.org/10.1109/ECTC.2017.295","url":null,"abstract":"2.5D and 3D Integration technology using temporary bonding has become main stream in the semiconductor industry in recent years. However, thermal stability, low damage, and debonding at comparative low temperature are still areas of challenge. In this present study, a novel three-dimensional crosslinked polyurethane (3DPU) based on thermal reversible Diels-Alder chemistry, which can be used as temporary bonding adhesive to support wafer thinning and back side processes and be de-bonded by typical thermal-sliding method at comparatively low-temperature, has been developed. The crosslinked 3DPU showed high thermal stability and excellent adhesion strength both at room temperature and higher temperature. The adhesion strength of 3DPU decreased when the wafer pair was heat to the de-bonding temperature (150 oC) when the retro-DA reaction happened which guaranteed a low-temperature de-bonding process.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"24 1","pages":"746-751"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81494574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ming-Hung Chen, Tzu-Hsing Chiang, Jia-Hao Zhang, Hsu-Chiang Shih, Sheng-Chi Hsieh, T. Lee, C. Hung
In this paper, a mass production solution of integrated passive device utilized on radio frequency communication systems was proposed through a glass panel platform where the size could be up to 408 mm * 512 mm and provided 1-layer capacitor and 1-layer inductor for IPD design. The structure characterization of panel-based IPD was performed as well as the electrical stability and RF functional test were evaluated to show the capability reference for further applications. The panel-based process could also provide a cost effective solution on emerging production.
本文提出了一种用于射频通信系统的集成无源器件的量产解决方案，该方案通过尺寸可达408 mm * 512 mm的玻璃面板平台，为IPD设计提供1层电容和1层电感。对基于面板的IPD进行了结构表征，并进行了电稳定性和射频功能测试，为进一步应用提供了性能参考。基于面板的工艺也可以为新兴生产提供具有成本效益的解决方案。
{"title":"Panel-Based Integrated Passive Device for RF Applicatio","authors":"Ming-Hung Chen, Tzu-Hsing Chiang, Jia-Hao Zhang, Hsu-Chiang Shih, Sheng-Chi Hsieh, T. Lee, C. Hung","doi":"10.1109/ECTC.2017.256","DOIUrl":"https://doi.org/10.1109/ECTC.2017.256","url":null,"abstract":"In this paper, a mass production solution of integrated passive device utilized on radio frequency communication systems was proposed through a glass panel platform where the size could be up to 408 mm * 512 mm and provided 1-layer capacitor and 1-layer inductor for IPD design. The structure characterization of panel-based IPD was performed as well as the electrical stability and RF functional test were evaluated to show the capability reference for further applications. The panel-based process could also provide a cost effective solution on emerging production.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"13 1","pages":"185-189"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85013412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Li-Yin Gao, Li Liu, Zhi-Quan Liu, Jing Wang, Zhaoxia Zhou, Changqing Liu
The high temperature storage test (HTST) was conducted on the SnAgCu/Ni-W-P and Ni-Fe solder joints. While the conventional Ni-P solder joints were used as comparison to study the diffusion barrier effect of Ni-W-P and Ni-Fe under bump metallization (UBM). Both cross section and top view for the microstructural evolution of solder joints during 150°C aging were observed by the scanning electron microscope (SEM). After reflow, (Cu, Ni)6Sn5 in the forms of chunky and rod-like was formed with an average thickness of around 1µm in SAC/Ni-P solder joint. During the HTST, bulky (Cu, Ni)6Sn5 grains were formed with a 5µm in diameter due to the interconnections of multiple (Cu, Ni)6Sn5 grains. In terms of SAC/Ni-Fe solder joints, during the reflow process, FeSn2 layer and rod-like (Cu, Ni)6Sn5 grains were formed. During the aging at 150°C, rod-like dispersed (Cu, Ni)6Sn5 grains started to interconnect with each other which finally progressed into an outer IMC layer upon FeSn2 phase. In Ni-W-P solder joints, the morphology and composition of IMCs is similar to it in Ni-P solder joints. The thickness of (Cu, Ni)6Sn5 was much thicker during reflow but turned out to be below it in Ni-P solder joints after 120h aging. Experimentally, both Ni-W-P and Ni-Fe UBM show an excellent diffusion barrier effect to retard the Kirkendall voids formation compared to the conventional Ni-P UBM. Specifically, (Cu, Ni)6Sn5 were formed at the SnAgCu/ Ni-W-P interface with a total thickness around 2µm, while only a 1µm thick FeSn2 layer accompanying with several dispersing (Cu, Ni)6Sn5 grains outside were formed at the SnAgCu/Ni-Fe interface. The addition of Fe elements can dramatically supress the diffusion of Ni and the formation of Ni3Sn4, which shows superior diffusion barrier compared to Ni-P UBM. The addition of W into Ni-P significantly decreases the growth rate of the interfacial IMCs during the aging process, which shows potential for electronic devices operated under long-term aging process.
对SnAgCu/Ni-W-P和Ni-Fe焊点进行了高温贮存试验。以传统的Ni-P焊点为对照，研究了凹凸金属化过程中Ni-W-P和Ni-Fe的扩散阻挡效应。利用扫描电子显微镜(SEM)观察了焊点在150℃时效过程中的组织演变过程。回流后，SAC/Ni- p焊点中形成块状和棒状的(Cu, Ni)6Sn5，平均厚度约为1µm。在高温加热过程中，由于多个(Cu, Ni)6Sn5晶粒相互连接，形成了直径为5 μ m的大块(Cu, Ni)6Sn5晶粒。SAC/Ni- fe焊点在回流过程中形成了FeSn2层和棒状(Cu, Ni)6Sn5晶粒。在150℃时效过程中，棒状分散(Cu, Ni)6Sn5晶粒开始相互连接，最终在FeSn2相上形成外IMC层。在Ni-W-P焊点中，IMCs的形貌和组成与Ni-P焊点相似。(Cu, Ni)6Sn5在回流焊时厚度较厚，但时效120h后在Ni- p焊点中厚度低于该厚度。实验结果表明，与传统的Ni-P复合材料相比，Ni-W-P复合材料和Ni-Fe复合材料均表现出良好的扩散阻挡效应，可以抑制Kirkendall空洞的形成。其中，(Cu, Ni)6Sn5在SnAgCu/Ni- w - p界面形成，总厚度约为2µm，而在SnAgCu/Ni- fe界面形成的FeSn2层厚度仅为1µm，并在表面形成分散的(Cu, Ni)6Sn5晶粒。Fe元素的加入能显著抑制Ni的扩散和Ni3Sn4的形成，表现出比Ni- p UBM更强的扩散屏障。在Ni-P中加入W可显著降低老化过程中界面imc的生长速度，显示出在长期老化过程中工作的电子器件的潜力。
{"title":"Diffusion Barrier Effect of Ni-W-P and Ni-Fe UBMs during High Temperature Storage","authors":"Li-Yin Gao, Li Liu, Zhi-Quan Liu, Jing Wang, Zhaoxia Zhou, Changqing Liu","doi":"10.1109/ECTC.2017.51","DOIUrl":"https://doi.org/10.1109/ECTC.2017.51","url":null,"abstract":"The high temperature storage test (HTST) was conducted on the SnAgCu/Ni-W-P and Ni-Fe solder joints. While the conventional Ni-P solder joints were used as comparison to study the diffusion barrier effect of Ni-W-P and Ni-Fe under bump metallization (UBM). Both cross section and top view for the microstructural evolution of solder joints during 150°C aging were observed by the scanning electron microscope (SEM). After reflow, (Cu, Ni)6Sn5 in the forms of chunky and rod-like was formed with an average thickness of around 1µm in SAC/Ni-P solder joint. During the HTST, bulky (Cu, Ni)6Sn5 grains were formed with a 5µm in diameter due to the interconnections of multiple (Cu, Ni)6Sn5 grains. In terms of SAC/Ni-Fe solder joints, during the reflow process, FeSn2 layer and rod-like (Cu, Ni)6Sn5 grains were formed. During the aging at 150°C, rod-like dispersed (Cu, Ni)6Sn5 grains started to interconnect with each other which finally progressed into an outer IMC layer upon FeSn2 phase. In Ni-W-P solder joints, the morphology and composition of IMCs is similar to it in Ni-P solder joints. The thickness of (Cu, Ni)6Sn5 was much thicker during reflow but turned out to be below it in Ni-P solder joints after 120h aging. Experimentally, both Ni-W-P and Ni-Fe UBM show an excellent diffusion barrier effect to retard the Kirkendall voids formation compared to the conventional Ni-P UBM. Specifically, (Cu, Ni)6Sn5 were formed at the SnAgCu/ Ni-W-P interface with a total thickness around 2µm, while only a 1µm thick FeSn2 layer accompanying with several dispersing (Cu, Ni)6Sn5 grains outside were formed at the SnAgCu/Ni-Fe interface. The addition of Fe elements can dramatically supress the diffusion of Ni and the formation of Ni3Sn4, which shows superior diffusion barrier compared to Ni-P UBM. The addition of W into Ni-P significantly decreases the growth rate of the interfacial IMCs during the aging process, which shows potential for electronic devices operated under long-term aging process.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"19 1","pages":"1566-1571"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90927735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Bellaredj, S. Mueller, A. Davis, Paul A. Kohl, Madhavan Swaminathan, Y. Mano
Integrated voltage regulators (IVRs) are considered nowadays as major elements in the development of power delivery networks for digital electronics because of their ability to implement point-of-load voltage regulation in multicore microprocessors and system-on-chip (SoC) architectures. Inductive regulators generally enable higher power efficiency over a wide range of conversion voltages. However, high efficiency IVRs require the integration of power inductors with low loss and reduced size at very high frequency. The use of a magnetic material core can reduce significantly the inductor area while increasing the inductance value at the same time. This paper focuses on the fabrication, characterization and modeling of Nickel Zinc (NiZn) Ferrite and Carbonyl Iron powder (CIP) epoxy composite magnet material which will be used as the magnetic core material of an embedded inductor in the PWB for SIP based buck type IVR. The fabricated composite materials and process are fully compatible with FR4 epoxy resin prepreg and laminate (PWB-compatible). The composite materials show (for 85% weigh loading, around 100 MHz at room temperature) a relative permeability between 7.5-8.1 for NiZn-composite (0.78 volume fraction) and between 5.2-5.6 for CIP composite (0.47 volume fraction) and a loss tangent value between 0.24-0.28 for NiZn-composite and 0.09- 0.1 for CIP-composite. The variation of the relative permeability and the frequency dispersion parameters of the magnetic composites are evaluated using Maxwell-Garnet Approximation (MGA) mixing rule and a simplified Lorentz and Landau-Lifshitz-Gilbert equation for Debye type relaxation. Evaluation of a buck type IVR based on the measured material properties shows that an embedded solenoidal inductor with an open core made with the NiZn Ferrite and CIP composite magnets can reach peak efficiencies of 91.7 % at 11 MHz for NiZn-composite, 91.6 % at 14 MHz for CIP-composite and 87.5 % (NiZn-composite) and 87.3 % (CIP-composite) efficiencies at 100 MHz for a 1.7V:1.05V conversion.
{"title":"Fabrication, Characterization and Comparison of FR4-Compatible Composite Magnetic Materials for High Efficiency Integrated Voltage Regulators with Embedded Magnetic Core Micro-Inductors","authors":"M. Bellaredj, S. Mueller, A. Davis, Paul A. Kohl, Madhavan Swaminathan, Y. Mano","doi":"10.1109/ECTC.2017.187","DOIUrl":"https://doi.org/10.1109/ECTC.2017.187","url":null,"abstract":"Integrated voltage regulators (IVRs) are considered nowadays as major elements in the development of power delivery networks for digital electronics because of their ability to implement point-of-load voltage regulation in multicore microprocessors and system-on-chip (SoC) architectures. Inductive regulators generally enable higher power efficiency over a wide range of conversion voltages. However, high efficiency IVRs require the integration of power inductors with low loss and reduced size at very high frequency. The use of a magnetic material core can reduce significantly the inductor area while increasing the inductance value at the same time. This paper focuses on the fabrication, characterization and modeling of Nickel Zinc (NiZn) Ferrite and Carbonyl Iron powder (CIP) epoxy composite magnet material which will be used as the magnetic core material of an embedded inductor in the PWB for SIP based buck type IVR. The fabricated composite materials and process are fully compatible with FR4 epoxy resin prepreg and laminate (PWB-compatible). The composite materials show (for 85% weigh loading, around 100 MHz at room temperature) a relative permeability between 7.5-8.1 for NiZn-composite (0.78 volume fraction) and between 5.2-5.6 for CIP composite (0.47 volume fraction) and a loss tangent value between 0.24-0.28 for NiZn-composite and 0.09- 0.1 for CIP-composite. The variation of the relative permeability and the frequency dispersion parameters of the magnetic composites are evaluated using Maxwell-Garnet Approximation (MGA) mixing rule and a simplified Lorentz and Landau-Lifshitz-Gilbert equation for Debye type relaxation. Evaluation of a buck type IVR based on the measured material properties shows that an embedded solenoidal inductor with an open core made with the NiZn Ferrite and CIP composite magnets can reach peak efficiencies of 91.7 % at 11 MHz for NiZn-composite, 91.6 % at 14 MHz for CIP-composite and 87.5 % (NiZn-composite) and 87.3 % (CIP-composite) efficiencies at 100 MHz for a 1.7V:1.05V conversion.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"4 1","pages":"2008-2014"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88471631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hung-Yuan Li, Allen Chen, S. Peng, George Pan, Stephen Chen
In recent years, the IoT popularity pushes the package development of 3C products into a more functional and thinner target. For high I/O density and low cost considered package, the promising Fan-out Wafer Level Packaging (FOWLP) provides a solution to match OSAT existing capability, besides, the chip last process in FOWLP can further enhance the total yield by selectable known-good dies (KGDs). However, under processing, the large portion of molding compound induces high warpage to challenge fabrication limitation. The additional leveling process is usually applied to lower the warpage that caused by the mismatch of coefficient of thermal expansion and Young's modulus from carriers, dies, and molding compound. This process results in the increase of package cost and even induce internal damages that affect device reliability. In order to avoid leveling process and improve warpage trend, in this paper, we simulated several models with different design of molding compound and dies, and then developed a multi-chip last FOWLP test vehicle by package dimension of 12x15 mm2 with 8x9 and 4x9 mm2 multiple dies, respectively. The test vehicle performed three redistribution layers (RDLs) including one fine pitch RDL of line width/line spacing 2um/2um, which is also the advantage of multi-chip last FOWLP, and also exhibited ball on trace structure for another low cost option. For the wafer warpage discussion, the results showed that tuning the thickness of molding compound can improve warpage trend, especially in the application of high modulus carrier, which improved wafer warpage within 1mm, for package warpage discussion, the thinner die can lower the warpage of package. Through well warpage controlling, the multi-chip last FOWLP package with ball on trace design was successfully presented in this paper, and also passed the package level reliability of TCB 1000 cycles, HTSL 1000 hrs, and uHAST 96 hrs, and drop test by board level reliability.
{"title":"Warpage Tuning Study for Multi-chip Last Fan Out Wafer Level Package","authors":"Hung-Yuan Li, Allen Chen, S. Peng, George Pan, Stephen Chen","doi":"10.1109/ECTC.2017.92","DOIUrl":"https://doi.org/10.1109/ECTC.2017.92","url":null,"abstract":"In recent years, the IoT popularity pushes the package development of 3C products into a more functional and thinner target. For high I/O density and low cost considered package, the promising Fan-out Wafer Level Packaging (FOWLP) provides a solution to match OSAT existing capability, besides, the chip last process in FOWLP can further enhance the total yield by selectable known-good dies (KGDs). However, under processing, the large portion of molding compound induces high warpage to challenge fabrication limitation. The additional leveling process is usually applied to lower the warpage that caused by the mismatch of coefficient of thermal expansion and Young's modulus from carriers, dies, and molding compound. This process results in the increase of package cost and even induce internal damages that affect device reliability. In order to avoid leveling process and improve warpage trend, in this paper, we simulated several models with different design of molding compound and dies, and then developed a multi-chip last FOWLP test vehicle by package dimension of 12x15 mm2 with 8x9 and 4x9 mm2 multiple dies, respectively. The test vehicle performed three redistribution layers (RDLs) including one fine pitch RDL of line width/line spacing 2um/2um, which is also the advantage of multi-chip last FOWLP, and also exhibited ball on trace structure for another low cost option. For the wafer warpage discussion, the results showed that tuning the thickness of molding compound can improve warpage trend, especially in the application of high modulus carrier, which improved wafer warpage within 1mm, for package warpage discussion, the thinner die can lower the warpage of package. Through well warpage controlling, the multi-chip last FOWLP package with ball on trace design was successfully presented in this paper, and also passed the package level reliability of TCB 1000 cycles, HTSL 1000 hrs, and uHAST 96 hrs, and drop test by board level reliability.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"118 1","pages":"1384-1391"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87002580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：