A. Garnier, L. Arnaud, R. Franiatte, A. Toffoli, S. Moreau, F. Bana, S. Chéramy
Microbump-based interconnects with 20 µm pitch have been fabricated on 300 mm wafers using industrial tools. Good processes control enables to get narrow standard deviations for the microbumps height (0.2 µm) and diameter (0.4 µm). Assembly was studied with chip to wafer (CtW) test vehicles by either mass reflow (MR) or thermo-compression (TC) with or without non-conductive paste (NCP). MR and TC processes result in suitable CtW alignments without significant defects at bonding interface. TC NCP assembly suffers from larger misalignment and underfill entrapment, reducing top to bottom bonding section. Consequently, unit electrical resistance is lower for MR and TC processes with ~25 m ascribed to pure vertical link, than for TC NCP process exhibiting ~50 m vertical link with larger standard deviation (15 m versus 2 m). Intermetallic compounds have been studied and Ni3Sn4 proves to be the main contributor for electrical resistance in our configuration where SnAg is sandwiched between 2 Ni layers. Electrical yield measured on daisy chains is very good (close to or higher than 90%) for MR or TC, even on more than 20,000 interconnects. For TC NCP, electrical yield remains to be improved, particularly on large daisy chains. Finally, an original electrical test has been designed and successfully implemented to characterize top to bottom misalignment. These results are promising for future high performance computing products that would require 20 µm pitch microbumps.
{"title":"Electrical Performance of High Density 10 µm Diameter 20 µm Pitch Cu-Pillar with Chip to Wafer Assembly","authors":"A. Garnier, L. Arnaud, R. Franiatte, A. Toffoli, S. Moreau, F. Bana, S. Chéramy","doi":"10.1109/ECTC.2017.38","DOIUrl":"https://doi.org/10.1109/ECTC.2017.38","url":null,"abstract":"Microbump-based interconnects with 20 µm pitch have been fabricated on 300 mm wafers using industrial tools. Good processes control enables to get narrow standard deviations for the microbumps height (0.2 µm) and diameter (0.4 µm). Assembly was studied with chip to wafer (CtW) test vehicles by either mass reflow (MR) or thermo-compression (TC) with or without non-conductive paste (NCP). MR and TC processes result in suitable CtW alignments without significant defects at bonding interface. TC NCP assembly suffers from larger misalignment and underfill entrapment, reducing top to bottom bonding section. Consequently, unit electrical resistance is lower for MR and TC processes with ~25 m ascribed to pure vertical link, than for TC NCP process exhibiting ~50 m vertical link with larger standard deviation (15 m versus 2 m). Intermetallic compounds have been studied and Ni3Sn4 proves to be the main contributor for electrical resistance in our configuration where SnAg is sandwiched between 2 Ni layers. Electrical yield measured on daisy chains is very good (close to or higher than 90%) for MR or TC, even on more than 20,000 interconnects. For TC NCP, electrical yield remains to be improved, particularly on large daisy chains. Finally, an original electrical test has been designed and successfully implemented to characterize top to bottom misalignment. These results are promising for future high performance computing products that would require 20 µm pitch microbumps.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"82 1","pages":"999-1007"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91402536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As mobile and handheld devices become more functionalities, required to accommodate more frequency bands, and to meet small form factor requirements. IPD (Integrated Passive Device) offers small form factor, and high performance benefits for RF solutions. To achieve a high performance RF filters, high-Q inductor is a key factor. A possible best high-Q inductor can be achieved is by Glass based solenoid inductor. In addition, 3D IPD process is another approach to reduce package size and increase functionality. In this paper, the fabrication process of IPD, based on 8" glass wafer with Through Glass Via (TGV) to form the 3D solenoid inductor is presented. In addition, the process integration between wafer level, assembly, and double-sided process are addressed. Along the process integration, a RF ASIC is integrated through wafer level and assembly process to form the 3D integrated Wafer Level Chip Scale Package (WLCSP). The quality factor of 3D solenoid inductors can achieve Q of 70~100 in this study. The TGV and package reliability results are also discussed.
{"title":"Glass Based 3D-IPD Integrated RF ASIC in WLCSP","authors":"T. Lee, Yung-shun Chang, Che-Ming Hsu, Sheng-Chi Hsieh, Pao-Nan Lee, Yu-Chang Hsieh, Long-Ching Wang, Lijuan Zhang","doi":"10.1109/ECTC.2017.328","DOIUrl":"https://doi.org/10.1109/ECTC.2017.328","url":null,"abstract":"As mobile and handheld devices become more functionalities, required to accommodate more frequency bands, and to meet small form factor requirements. IPD (Integrated Passive Device) offers small form factor, and high performance benefits for RF solutions. To achieve a high performance RF filters, high-Q inductor is a key factor. A possible best high-Q inductor can be achieved is by Glass based solenoid inductor. In addition, 3D IPD process is another approach to reduce package size and increase functionality. In this paper, the fabrication process of IPD, based on 8\" glass wafer with Through Glass Via (TGV) to form the 3D solenoid inductor is presented. In addition, the process integration between wafer level, assembly, and double-sided process are addressed. Along the process integration, a RF ASIC is integrated through wafer level and assembly process to form the 3D integrated Wafer Level Chip Scale Package (WLCSP). The quality factor of 3D solenoid inductors can achieve Q of 70~100 in this study. The TGV and package reliability results are also discussed.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"76 1","pages":"631-636"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91531726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shreya Dwarakanath, P. Raj, Collen Z. Leng, V. Smet, M. Losego, V. Sundaram, R. Tummala
This paper demonstrates a new class of inorganic-organic hybrid dielectric materials to address the requirements for high-temperature reliability of next-generation high-density, high-power packages and electronics in harsh environments for automotive applications. A major concern for reliability is the inadequate adhesion of metals with high-temperature polymers. Adhesion deteriorates further via thermal and oxidative exposure and moisture absorption. In this paper, a novel vapor phase infiltration (VPI) technique is applied to create an organic-inorganic hybrid dielectric surface that improves metal-polymer adhesion. The VPI process infuses inorganic constituents to a depth of at least 3 microns, as revealed by elemental analysis using SEM-EDX and XPS depth profiles. In preliminary testing, Cu/Cr films deposited onto these modified polymer surfaces exhibit 3x higher peel strength than metal films deposited on untreated polymer.
{"title":"Infusing Inorganics into the Subsurface of Polymer Redistribution Layer Dielectrics for Improved Adhesion to Metals Interconnects","authors":"Shreya Dwarakanath, P. Raj, Collen Z. Leng, V. Smet, M. Losego, V. Sundaram, R. Tummala","doi":"10.1109/ECTC.2017.277","DOIUrl":"https://doi.org/10.1109/ECTC.2017.277","url":null,"abstract":"This paper demonstrates a new class of inorganic-organic hybrid dielectric materials to address the requirements for high-temperature reliability of next-generation high-density, high-power packages and electronics in harsh environments for automotive applications. A major concern for reliability is the inadequate adhesion of metals with high-temperature polymers. Adhesion deteriorates further via thermal and oxidative exposure and moisture absorption. In this paper, a novel vapor phase infiltration (VPI) technique is applied to create an organic-inorganic hybrid dielectric surface that improves metal-polymer adhesion. The VPI process infuses inorganic constituents to a depth of at least 3 microns, as revealed by elemental analysis using SEM-EDX and XPS depth profiles. In preliminary testing, Cu/Cr films deposited onto these modified polymer surfaces exhibit 3x higher peel strength than metal films deposited on untreated polymer.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"34 1","pages":"150-155"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90713887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Che, M. Kawano, M. Ding, Y. Han, S. Bhattacharya
TSV-Free Interposer (TFI) technology eliminates TSV fabrication and reduces manufacturing and material cost. Co-design modelling methodology is established for TFI technology with considering wafer process, package assembly and package/board level reliability and thermal performance to optimize structure design, wafer process, assembly process and material selection. Experimental results are used for validating warpage modelling results. Through wafer level modelling, suitable carrier wafer and EMC materials are recommended to control wafer warpage less than 2mm. Effects of package substrate coefficient of thermal expansion (CTE) and stiffener on assembly induced package warpage are simulated to reduce package warpage. The recommended materials and geometry design based on reliability are aligned with that from wafer and package warpage simulation results. The final test vehicle (TV) design and material selection are determined based on co-design modelling results for achieving successful TFI wafer process and package assembly process and long term package/board level reliability.
{"title":"Co-Design for Low Warpage and High Reliability in Advanced Package with TSV-Free Interposer (TFI)","authors":"F. Che, M. Kawano, M. Ding, Y. Han, S. Bhattacharya","doi":"10.1109/ECTC.2017.31","DOIUrl":"https://doi.org/10.1109/ECTC.2017.31","url":null,"abstract":"TSV-Free Interposer (TFI) technology eliminates TSV fabrication and reduces manufacturing and material cost. Co-design modelling methodology is established for TFI technology with considering wafer process, package assembly and package/board level reliability and thermal performance to optimize structure design, wafer process, assembly process and material selection. Experimental results are used for validating warpage modelling results. Through wafer level modelling, suitable carrier wafer and EMC materials are recommended to control wafer warpage less than 2mm. Effects of package substrate coefficient of thermal expansion (CTE) and stiffener on assembly induced package warpage are simulated to reduce package warpage. The recommended materials and geometry design based on reliability are aligned with that from wafer and package warpage simulation results. The final test vehicle (TV) design and material selection are determined based on co-design modelling results for achieving successful TFI wafer process and package assembly process and long term package/board level reliability.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"21 1","pages":"853-861"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73987271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Hanss, E. Liu, M. Schmid, D. Müller, U. Karbowski, Robert Derix, G. Elger
A high reliability of light emitting diode (LED) light sources is essential for general and automotive lighting applications, where exchange of LED components is expensive. Thermal management of modern high power LEDs is crucial for their lifetime. An important aspect is the thermal path for heat conduction. Many different defects can have an influence on this path of an electronic system: on the one hand process failures during production, e.g. voids inside the solder joint, on the other hand typical failures induced by thermo-mechanical stress during their lifetime, like cracks in the solder joint or delamination in the package. The transient thermal analysis (TTA) is a powerful tool to detect changes in the thermal path. Due to improvements in the TTA method during the last years, not only cracks can be detected but also failure modes can be separated, and the root cause can be analyzed by support of transient finite element analysis. In this paper, transient thermal testing is applied and further developed, to monitor the structural integrity of new wafer level LED packages during thermal stress testing. Failure modes are defined and separated. For failure analysis the different defects are simulated by transient finite element analysis and correlated to the TTA results. The simulation results, that solder cracks increase the peak height of the derivative of the transient thermal curves (b(z)). A delamination of an inner layer of the LED package creates additionally to the increase of the peak height also a separation of the b(z) curves between 1 µs and 5 µs. Therefore a transient thermal measurement equipment with a dead time
{"title":"New Method to Separate Failure Modes by Transient Thermal Analysis of High Power LEDs","authors":"A. Hanss, E. Liu, M. Schmid, D. Müller, U. Karbowski, Robert Derix, G. Elger","doi":"10.1109/ECTC.2017.137","DOIUrl":"https://doi.org/10.1109/ECTC.2017.137","url":null,"abstract":"A high reliability of light emitting diode (LED) light sources is essential for general and automotive lighting applications, where exchange of LED components is expensive. Thermal management of modern high power LEDs is crucial for their lifetime. An important aspect is the thermal path for heat conduction. Many different defects can have an influence on this path of an electronic system: on the one hand process failures during production, e.g. voids inside the solder joint, on the other hand typical failures induced by thermo-mechanical stress during their lifetime, like cracks in the solder joint or delamination in the package. The transient thermal analysis (TTA) is a powerful tool to detect changes in the thermal path. Due to improvements in the TTA method during the last years, not only cracks can be detected but also failure modes can be separated, and the root cause can be analyzed by support of transient finite element analysis. In this paper, transient thermal testing is applied and further developed, to monitor the structural integrity of new wafer level LED packages during thermal stress testing. Failure modes are defined and separated. For failure analysis the different defects are simulated by transient finite element analysis and correlated to the TTA results. The simulation results, that solder cracks increase the peak height of the derivative of the transient thermal curves (b(z)). A delamination of an inner layer of the LED package creates additionally to the increase of the peak height also a separation of the b(z) curves between 1 µs and 5 µs. Therefore a transient thermal measurement equipment with a dead time","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"27 1","pages":"1136-1144"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73242413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Boyer, Alexander Janta-Polczynski, J. Morissette, S. Martel, Ted W. Lichoulas, S. Kamlapurkar, S. Engelmann, P. Fortier, T. Barwicz
Cost-efficient assembly of single-mode fibers to silicon chips is a significant challenge for large-scale deployment of Si photonics. We have previously demonstrated a fully automated approach to parallelized assembly of fiber arrays to nanophotonic chips meant to be performed with standard high-throughput microelectronic tooling. Our original approach required a customization of a standard fiber component, which could limit cost-efficiency and scalability. Here, we demonstrate a novel approach to fiber assembly employing off-the-shelf fiber components only. The new concept employs a dual vacuum pick-tip that can be integrated in standard high-throughput microelectronic tooling. We validate this approach with assemblies of standard 12-fiber interfaces to nanophotonic chips. The assembly performance is assessed via x-ray tomography cross-sections, polished mechanical cross-sections, and optical coupling measurements.
{"title":"Novel, High-Throughput, Fiber-to-Chip Assembly Employing Only Off-the-Shelf Components","authors":"N. Boyer, Alexander Janta-Polczynski, J. Morissette, S. Martel, Ted W. Lichoulas, S. Kamlapurkar, S. Engelmann, P. Fortier, T. Barwicz","doi":"10.1109/ECTC.2017.185","DOIUrl":"https://doi.org/10.1109/ECTC.2017.185","url":null,"abstract":"Cost-efficient assembly of single-mode fibers to silicon chips is a significant challenge for large-scale deployment of Si photonics. We have previously demonstrated a fully automated approach to parallelized assembly of fiber arrays to nanophotonic chips meant to be performed with standard high-throughput microelectronic tooling. Our original approach required a customization of a standard fiber component, which could limit cost-efficiency and scalability. Here, we demonstrate a novel approach to fiber assembly employing off-the-shelf fiber components only. The new concept employs a dual vacuum pick-tip that can be integrated in standard high-throughput microelectronic tooling. We validate this approach with assemblies of standard 12-fiber interfaces to nanophotonic chips. The assembly performance is assessed via x-ray tomography cross-sections, polished mechanical cross-sections, and optical coupling measurements.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"52 1","pages":"1632-1639"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73369113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
O. Phillips, J. Schwartz, A. Engler, Gerald Gourdin, P. Kohl
Transient electronics is an emerging field oftechnology where the controlled, programmable vaporizationof a device is needed because retrieval is not possible or adifferent form of disposal is desired. Decomposable polymersare of interest and may be used to form electronic componentsand packages. The ability to trigger these polymers todepolymerize and vaporize at ambient conditions can lead tomany applications. Low ceiling temperature polyaldehydeshave been evaluated for transience. Incorporation of morevolatile monomer units significantly increase the evaporationrate of decomposition products. The stimulus fordisappearance is a photochemical reaction that has beenextended from the ultraviolet to the visible region. Chemicalamplification of the trigger source has been demonstrated withacid amplifiers.
{"title":"Phototriggerable Transient Electronics: Materials and Concepts","authors":"O. Phillips, J. Schwartz, A. Engler, Gerald Gourdin, P. Kohl","doi":"10.1109/ECTC.2017.174","DOIUrl":"https://doi.org/10.1109/ECTC.2017.174","url":null,"abstract":"Transient electronics is an emerging field oftechnology where the controlled, programmable vaporizationof a device is needed because retrieval is not possible or adifferent form of disposal is desired. Decomposable polymersare of interest and may be used to form electronic componentsand packages. The ability to trigger these polymers todepolymerize and vaporize at ambient conditions can lead tomany applications. Low ceiling temperature polyaldehydeshave been evaluated for transience. Incorporation of morevolatile monomer units significantly increase the evaporationrate of decomposition products. The stimulus fordisappearance is a photochemical reaction that has beenextended from the ultraviolet to the visible region. Chemicalamplification of the trigger source has been demonstrated withacid amplifiers.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"61 1","pages":"772-779"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73823487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Nagarkar, Xiaoxiao Hou, N. Stoffel, E. Davis, Jeffrey M. Ashe, D. Borton
In this paper, we propose a fused silica packaging platform with a micro-cavity designed to house and protect active electronics for neural interfaces. Proof-of-concept test vehicles were specifically designed, fabricated, and packaged in order to evaluate the ability of the packaging to protect against water and ion incursion. Accelerated degradation testing of three test vehicles in physiological saline was performed in a custom-built encapsulation test system (ETS) at 57 °C for 16 days (nominally equivalent to 68 days at 37 °C). Leakage current, as well as gross functionality of the test circuit, was evaluated and is presented as preliminary results.
{"title":"Micro-Hermetic Packaging Technology for Active Implantable Neural Interfaces","authors":"K. Nagarkar, Xiaoxiao Hou, N. Stoffel, E. Davis, Jeffrey M. Ashe, D. Borton","doi":"10.1109/ECTC.2017.340","DOIUrl":"https://doi.org/10.1109/ECTC.2017.340","url":null,"abstract":"In this paper, we propose a fused silica packaging platform with a micro-cavity designed to house and protect active electronics for neural interfaces. Proof-of-concept test vehicles were specifically designed, fabricated, and packaged in order to evaluate the ability of the packaging to protect against water and ion incursion. Accelerated degradation testing of three test vehicles in physiological saline was performed in a custom-built encapsulation test system (ETS) at 57 °C for 16 days (nominally equivalent to 68 days at 37 °C). Leakage current, as well as gross functionality of the test circuit, was evaluated and is presented as preliminary results.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"23 1","pages":"218-223"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74234736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Exploring along the road of More Moore with integration degree increasing significantly, different wafer level 3-D technologies are developed facing various circumstances. Thermal issue has become an important concern in IC designing and manufacturing. Fan-out wafer level package (FOWLP), as one of the most popular packaging trends lately, compared to high cost through silicon via (TSV) based 3D integration method, requires system level thermal management. Full scale numerical simulation as a critical procedure is facing huge difficulties, such as huge structure size variation, huge thermal properties variation, in-plane and off-plane displacement, etc. Equivalent thermal conductivity model (ETCM) based full scale numerical simulation for thermal management, which has already been applied to TSV based 3-D ICs with computation consumption significantly decreased, is applied to Fan-out packages in this paper. Equivalent and anisotropic thermal conductivity is calculated and modified concerning FOWLP structure and material thermal properties. A chip-first face-up fan-out package with 100 pads and 100 bumps is modeled and simulated, with mesh elements number drops from 874836 to 174810. With more than 80% computation consumption saved, less than 2% difference in total temperature rise is obtained compared with detail simulation.
{"title":"Equivalent Thermal Conductivity Model Based Full Scale Numerical Simulation for Thermal Management in Fan-Out Packages","authors":"Ningyu Wang, Yudan Pi, Wei Wang, Yufeng Jin","doi":"10.1109/ECTC.2017.82","DOIUrl":"https://doi.org/10.1109/ECTC.2017.82","url":null,"abstract":"Exploring along the road of More Moore with integration degree increasing significantly, different wafer level 3-D technologies are developed facing various circumstances. Thermal issue has become an important concern in IC designing and manufacturing. Fan-out wafer level package (FOWLP), as one of the most popular packaging trends lately, compared to high cost through silicon via (TSV) based 3D integration method, requires system level thermal management. Full scale numerical simulation as a critical procedure is facing huge difficulties, such as huge structure size variation, huge thermal properties variation, in-plane and off-plane displacement, etc. Equivalent thermal conductivity model (ETCM) based full scale numerical simulation for thermal management, which has already been applied to TSV based 3-D ICs with computation consumption significantly decreased, is applied to Fan-out packages in this paper. Equivalent and anisotropic thermal conductivity is calculated and modified concerning FOWLP structure and material thermal properties. A chip-first face-up fan-out package with 100 pads and 100 bumps is modeled and simulated, with mesh elements number drops from 874836 to 174810. With more than 80% computation consumption saved, less than 2% difference in total temperature rise is obtained compared with detail simulation.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"137 1","pages":"2054-2059"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80091122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jinhui Li, Qiang Liu, Guoping Zhang, Bin Zhao, R. Sun, C. Wong
2.5D and 3D Integration technology using temporary bonding has become main stream in the semiconductor industry in recent years. However, thermal stability, low damage, and debonding at comparative low temperature are still areas of challenge. In this present study, a novel three-dimensional crosslinked polyurethane (3DPU) based on thermal reversible Diels-Alder chemistry, which can be used as temporary bonding adhesive to support wafer thinning and back side processes and be de-bonded by typical thermal-sliding method at comparatively low-temperature, has been developed. The crosslinked 3DPU showed high thermal stability and excellent adhesion strength both at room temperature and higher temperature. The adhesion strength of 3DPU decreased when the wafer pair was heat to the de-bonding temperature (150 oC) when the retro-DA reaction happened which guaranteed a low-temperature de-bonding process.
{"title":"Thermally Reversible and Crosslinked Polyurethane Based on Diels-Alder Chemistry for Ultrathin Wafer Temporary Bonding at Low-Temperature","authors":"Jinhui Li, Qiang Liu, Guoping Zhang, Bin Zhao, R. Sun, C. Wong","doi":"10.1109/ECTC.2017.295","DOIUrl":"https://doi.org/10.1109/ECTC.2017.295","url":null,"abstract":"2.5D and 3D Integration technology using temporary bonding has become main stream in the semiconductor industry in recent years. However, thermal stability, low damage, and debonding at comparative low temperature are still areas of challenge. In this present study, a novel three-dimensional crosslinked polyurethane (3DPU) based on thermal reversible Diels-Alder chemistry, which can be used as temporary bonding adhesive to support wafer thinning and back side processes and be de-bonded by typical thermal-sliding method at comparatively low-temperature, has been developed. The crosslinked 3DPU showed high thermal stability and excellent adhesion strength both at room temperature and higher temperature. The adhesion strength of 3DPU decreased when the wafer pair was heat to the de-bonding temperature (150 oC) when the retro-DA reaction happened which guaranteed a low-temperature de-bonding process.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"24 1","pages":"746-751"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81494574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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