Chi-An Pan, C. Yeh, Wei-Chun Qiu, Rong-Zheng Lin, Liang-Yih Hung, Kong-Toon Ng, C. F. Lin, C. Chung, D. Jiang, C. Hsiao
High power consumption & high input/out (IO) density are requested by modem electronic components such as high-density electronics, communication satellites, advanced aircraft, networking server and telecommunication devices. Challenges in the heat dissipation of an electronic package arise from the continued increase in power dissipation and power density of higher-power devices. A thermal interface material (TIM) with excellent heat conduction coefficient is applied between the heat source surface and the heat-spreading module. This is to efficiently dissipate heat from the heat source. Thermal performance of an assembled device becomes one of the most important quality factors in electronic packaging. Therefore, beside the thermal properties, a good mechanical strength of TIM is required. In order to meet demands for higher thermal performance and reliability strength needs in modem electronic devices, various new TIM materials were proposed by industry leading material suppliers. Some of the leading new TIM materials used for this purpose are graphite based and metal based materials where thermal conductivity could be higher than epoxy based TIM materials. In this paper, we will compare new graphite based and metal based TIM materials with existing epoxy based TIM materials and will discuss the various assembly challenges and reliability performance of these new TIM materials. Compare to commercial TIM, the graphite based TIM provide a heat conduction path in a direction perpendicular, metal based TIM is disposed in the Nano-particle metal by sintering to consist of heat conduction path. The junction temperature (Tj) of metal based TIM material shows 5 degrees C decreased than epoxy based material. Also, TIM coverage has been verified via scanning acoustic tomography (SAT) post reliability testing. Moreover, thermal simulations will be conducted and presented in this paper.
{"title":"Assembly and Reliability Challenges for Next Generation High Thermal TIM Materials","authors":"Chi-An Pan, C. Yeh, Wei-Chun Qiu, Rong-Zheng Lin, Liang-Yih Hung, Kong-Toon Ng, C. F. Lin, C. Chung, D. Jiang, C. Hsiao","doi":"10.1109/ECTC.2017.114","DOIUrl":"https://doi.org/10.1109/ECTC.2017.114","url":null,"abstract":"High power consumption & high input/out (IO) density are requested by modem electronic components such as high-density electronics, communication satellites, advanced aircraft, networking server and telecommunication devices. Challenges in the heat dissipation of an electronic package arise from the continued increase in power dissipation and power density of higher-power devices. A thermal interface material (TIM) with excellent heat conduction coefficient is applied between the heat source surface and the heat-spreading module. This is to efficiently dissipate heat from the heat source. Thermal performance of an assembled device becomes one of the most important quality factors in electronic packaging. Therefore, beside the thermal properties, a good mechanical strength of TIM is required. In order to meet demands for higher thermal performance and reliability strength needs in modem electronic devices, various new TIM materials were proposed by industry leading material suppliers. Some of the leading new TIM materials used for this purpose are graphite based and metal based materials where thermal conductivity could be higher than epoxy based TIM materials. In this paper, we will compare new graphite based and metal based TIM materials with existing epoxy based TIM materials and will discuss the various assembly challenges and reliability performance of these new TIM materials. Compare to commercial TIM, the graphite based TIM provide a heat conduction path in a direction perpendicular, metal based TIM is disposed in the Nano-particle metal by sintering to consist of heat conduction path. The junction temperature (Tj) of metal based TIM material shows 5 degrees C decreased than epoxy based material. Also, TIM coverage has been verified via scanning acoustic tomography (SAT) post reliability testing. Moreover, thermal simulations will be conducted and presented in this paper.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"8 1","pages":"2033-2039"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90100001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Michael Dittrich, A. Heinig, Fabian Hopsch, R. Trieb
Silicon Interposers enable very high routing density in between integrated circuits (ICs) that are fabricated in different technologies like 65 nm for power amplifiers and 14 nm FinFET for highest performance. This is not possible within a System on Chip (SoC). While heterogeneous silicon interposer integration is now used in the first products for processor-memory-integration, it is still rarely used in other fields of application. This paper proposes an approach to integrate an ADC (e.g. fabricated in SiGe bipolar technology) with an existing processing unit like a digital signal processor (DSP) or a field programmable gate array (FPGA) using an interposer and an additional IC for communication. This approach allows to further increase the data rate from the ADC to the processor. It also simplifies the large and costly interface of the ADC. The paper discusses different options of the approach and their impact to the interposer routing. The requirements for the routing of the interposer interconnections are derived from the application, models of the interconnections are extracted with 3D FEM Tools. Finally the interconnections are simulated using accurate Spice models for the IO cells.
{"title":"Heterogeneous Interposer Based Integration of Chips with Copper Pillars and C4 Balls to Achieve High Speed Interfaces for ADC Application","authors":"Michael Dittrich, A. Heinig, Fabian Hopsch, R. Trieb","doi":"10.1109/ECTC.2017.221","DOIUrl":"https://doi.org/10.1109/ECTC.2017.221","url":null,"abstract":"Silicon Interposers enable very high routing density in between integrated circuits (ICs) that are fabricated in different technologies like 65 nm for power amplifiers and 14 nm FinFET for highest performance. This is not possible within a System on Chip (SoC). While heterogeneous silicon interposer integration is now used in the first products for processor-memory-integration, it is still rarely used in other fields of application. This paper proposes an approach to integrate an ADC (e.g. fabricated in SiGe bipolar technology) with an existing processing unit like a digital signal processor (DSP) or a field programmable gate array (FPGA) using an interposer and an additional IC for communication. This approach allows to further increase the data rate from the ADC to the processor. It also simplifies the large and costly interface of the ADC. The paper discusses different options of the approach and their impact to the interposer routing. The requirements for the routing of the interposer interconnections are derived from the application, models of the interconnections are extracted with 3D FEM Tools. Finally the interconnections are simulated using accurate Spice models for the IO cells.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"14 1","pages":"643-648"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90101476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hao Tang, G. Shi, Raphael He, Hsiang-Hung Chang, Shengchun Yang, M. Yin, Wei Zhang, M. Nguyen
Fan-out wafer level packaging (FOWLP) not only provides simplified supply chain management and lower cost structure, but also enables thinner profile and heterogeneous system integration. FOWLP is becoming increasingly significant and is projected to drive growth in advanced packaging for the foreseeable future. There are many different processing technologies for fabricating FOWLP. One common key practice, which is very different from fan-in wafer level packaging, is the use of a temporary carrier to support wafer-level fabrication. The redistribution-layer (RDL) first approach is one of two mainstream processing technologies for FOWLP at present. One benefit is that the RDL is fabricated with direct support of a flat, rigid carrier prior to the occurrence of molding warpage and die shift. However, the RDL-first approach requires a carrier sacrificial layer that can withstand high-temperature/high-vacuum RDL build-up fabrication. Determined by adhesive chemistry's availability, the present forms of RDL-first FOWLP processing require carrier release by laser ablation, thus further limiting the choice of carrier to glass. At present, laser debonding for RDL-first FOWLP is a very costly and lengthy process. This paper presents a design for optimizing and processing a carrier-sacrificial layer that is compatible not only with current RDL-first FOWLP fabrication, but also enables the carrier's instant release by air jetting at room temperature. This air-assisted mechanical release of the carrier minimizes debonding stress on the wafer surface without localized heating and burning, and provides even more stress relief for larger carriers. A fan-out WLP process flow with air jetting carrier release is presented and evaluated. Key material properties of the current sacrificial-layer design are also analyzed.
{"title":"High Throughput Low Stress Air Jetting Carrier Release for RDL-First Fan-Out Wafer-Level-Packaging","authors":"Hao Tang, G. Shi, Raphael He, Hsiang-Hung Chang, Shengchun Yang, M. Yin, Wei Zhang, M. Nguyen","doi":"10.1109/ECTC.2017.338","DOIUrl":"https://doi.org/10.1109/ECTC.2017.338","url":null,"abstract":"Fan-out wafer level packaging (FOWLP) not only provides simplified supply chain management and lower cost structure, but also enables thinner profile and heterogeneous system integration. FOWLP is becoming increasingly significant and is projected to drive growth in advanced packaging for the foreseeable future. There are many different processing technologies for fabricating FOWLP. One common key practice, which is very different from fan-in wafer level packaging, is the use of a temporary carrier to support wafer-level fabrication. The redistribution-layer (RDL) first approach is one of two mainstream processing technologies for FOWLP at present. One benefit is that the RDL is fabricated with direct support of a flat, rigid carrier prior to the occurrence of molding warpage and die shift. However, the RDL-first approach requires a carrier sacrificial layer that can withstand high-temperature/high-vacuum RDL build-up fabrication. Determined by adhesive chemistry's availability, the present forms of RDL-first FOWLP processing require carrier release by laser ablation, thus further limiting the choice of carrier to glass. At present, laser debonding for RDL-first FOWLP is a very costly and lengthy process. This paper presents a design for optimizing and processing a carrier-sacrificial layer that is compatible not only with current RDL-first FOWLP fabrication, but also enables the carrier's instant release by air jetting at room temperature. This air-assisted mechanical release of the carrier minimizes debonding stress on the wafer surface without localized heating and burning, and provides even more stress relief for larger carriers. A fan-out WLP process flow with air jetting carrier release is presented and evaluated. Key material properties of the current sacrificial-layer design are also analyzed.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"1748-1754"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89231708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Stretchable conductive composites have received considerable research interest recently for high-end microelectronic applications. Here we report conductive and stretchable composites by incorporating various shape-modified silver fillers into polyurethane elastomer matrix. By selecting soft and hard segments of polyurethane, the polymer resin can not only provide sufficient stretchability/flexibility, but also serve to reduce the surfactants on silver surface due to the presence of hydroxyl groups. Three conductive fillers, including commercial silver flakes, synthesized silver nanowires and three-dimensional silver dendrites were employed. The conductive composites could achieve resistivity as low as 5×10-5 .cm at using 80 wt% of silver flakes. The silver nanowires, with aspect ratio higher than 100, can achieve low electrical percolation threshold. The silver dendrite were prepared by a simple solution process with the capability for scalable production at low cost. The branched nano/microstructures can be delicately controlled by tuning the feeding speed and molar ratio of the silver precursor and reducing agent. Without any surface treatment, the bulk resistivity of the printed composite films was ~ 8×10-4 .cm at 70 wt% filler loading. The design of the conductive fillers within compatible elastomers show great potentials for portable and wearable electronic devices.
{"title":"Stretchable and Electrically Conductive Composites Fabricated from Polyurethane and Silver Nano/Microstructures","authors":"B. Song, K. Moon, C. Wong","doi":"10.1109/ECTC.2017.149","DOIUrl":"https://doi.org/10.1109/ECTC.2017.149","url":null,"abstract":"Stretchable conductive composites have received considerable research interest recently for high-end microelectronic applications. Here we report conductive and stretchable composites by incorporating various shape-modified silver fillers into polyurethane elastomer matrix. By selecting soft and hard segments of polyurethane, the polymer resin can not only provide sufficient stretchability/flexibility, but also serve to reduce the surfactants on silver surface due to the presence of hydroxyl groups. Three conductive fillers, including commercial silver flakes, synthesized silver nanowires and three-dimensional silver dendrites were employed. The conductive composites could achieve resistivity as low as 5×10-5 .cm at using 80 wt% of silver flakes. The silver nanowires, with aspect ratio higher than 100, can achieve low electrical percolation threshold. The silver dendrite were prepared by a simple solution process with the capability for scalable production at low cost. The branched nano/microstructures can be delicately controlled by tuning the feeding speed and molar ratio of the silver precursor and reducing agent. Without any surface treatment, the bulk resistivity of the printed composite films was ~ 8×10-4 .cm at 70 wt% filler loading. The design of the conductive fillers within compatible elastomers show great potentials for portable and wearable electronic devices.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"8 1","pages":"2181-2186"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86663625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ji-hye Kim, Tae-Ik Lee, Dal-Jin Yoon, Taek‐Soo Kim, K. Paik
The interest in wearable electronics has been rapidly increasing due to the high demands for various wearable devices such as smart glasses and smart watches which satisfy the needs of today's customers. Future wearable devices will require fully flexible chip packaging performance and also maintain stable electrical performance under repeatedly bending environment. To meet these requirements, ultra-thin silicon dies and flexible substrates will be used for flexible electronic packaging and assembly. In addition, among various electrical interconnection methods used in electronic package systems, ACFs interconnection methods will be considered as one of the most promising flexible interconnection methods due to its resilience against bending and flexing environments. ACFs consist of adhesive polymer resin with randomly distributed conductive balls, which form an electrical conduction between the bumps of chip and electrodes of flexible substrates. In our previous studies, ultra-thin chip-in-flex (CIF) packages using ACFs were introduced, and the bending properties have been evaluated in terms of ACF material properties such as adhesion strength and modulus of polymer resins. In this paper, effects of ACFs gap heights on the CIF bending reliability were investigated using polymer conductive balls with various diameters. The dynamic bending reliability of ACFs-assembled CIF packages were evaluated up to 160,000 bending cycles at 6 mm bending radius to determine the dynamic bending performance of CIF packages.
{"title":"Effects of Anisotropic Conductive Films (ACFs) Gap Heights on the Bending Reliability of Chip-In-Flex (CIF) Packages for Wearable Electronics Applications","authors":"Ji-hye Kim, Tae-Ik Lee, Dal-Jin Yoon, Taek‐Soo Kim, K. Paik","doi":"10.1109/ECTC.2017.118","DOIUrl":"https://doi.org/10.1109/ECTC.2017.118","url":null,"abstract":"The interest in wearable electronics has been rapidly increasing due to the high demands for various wearable devices such as smart glasses and smart watches which satisfy the needs of today's customers. Future wearable devices will require fully flexible chip packaging performance and also maintain stable electrical performance under repeatedly bending environment. To meet these requirements, ultra-thin silicon dies and flexible substrates will be used for flexible electronic packaging and assembly. In addition, among various electrical interconnection methods used in electronic package systems, ACFs interconnection methods will be considered as one of the most promising flexible interconnection methods due to its resilience against bending and flexing environments. ACFs consist of adhesive polymer resin with randomly distributed conductive balls, which form an electrical conduction between the bumps of chip and electrodes of flexible substrates. In our previous studies, ultra-thin chip-in-flex (CIF) packages using ACFs were introduced, and the bending properties have been evaluated in terms of ACF material properties such as adhesion strength and modulus of polymer resins. In this paper, effects of ACFs gap heights on the CIF bending reliability were investigated using polymer conductive balls with various diameters. The dynamic bending reliability of ACFs-assembled CIF packages were evaluated up to 160,000 bending cycles at 6 mm bending radius to determine the dynamic bending performance of CIF packages.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"5 1","pages":"2161-2167"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87404364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We developed a method based on cyclic voltammetrically measurements which allows corrosion sensitivity analyzes of typical metallization systems for substrates and electrical contacts in a very short time. Using a new electrolyte with innovative composition enables to combine the aggressive impact of the three standard tests in one procedure and initiates typical application related corrosion processes. Additionally the method allows quantitative results for the specimen tested. In this paper we will present and discuss the new method for corrosion testing in correlation to standard reliability tests, like mixed flow gas testing (MFG). Furthermore high resolution microstructural analyzes after standard reliability testing as well as after cyclic voltammetrically investigation are giving evidence for the running corrosion mechanism. We will show results of Scanning Electron Microscopy (SEM) and element analyzes (EDS) for samples after standard testing and after applying the new test method. Finally the corrosion processes induced by the different tests will be compared and discussed.
{"title":"A New Method for Prediction of Corrosion Processes in Metallization Systems for Substrates and Electrical Contacts","authors":"S. Klengel, Tino Stpehan, U. Spohn","doi":"10.1109/ECTC.2017.139","DOIUrl":"https://doi.org/10.1109/ECTC.2017.139","url":null,"abstract":"We developed a method based on cyclic voltammetrically measurements which allows corrosion sensitivity analyzes of typical metallization systems for substrates and electrical contacts in a very short time. Using a new electrolyte with innovative composition enables to combine the aggressive impact of the three standard tests in one procedure and initiates typical application related corrosion processes. Additionally the method allows quantitative results for the specimen tested. In this paper we will present and discuss the new method for corrosion testing in correlation to standard reliability tests, like mixed flow gas testing (MFG). Furthermore high resolution microstructural analyzes after standard reliability testing as well as after cyclic voltammetrically investigation are giving evidence for the running corrosion mechanism. We will show results of Scanning Electron Microscopy (SEM) and element analyzes (EDS) for samples after standard testing and after applying the new test method. Finally the corrosion processes induced by the different tests will be compared and discussed.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"2 1","pages":"1165-1170"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88653224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Lall, D. Zhang, Vikas Yadav, J. Suhling, David Locker
Transient dynamic loads in addition to prolonged periods of high temperature exposure are a part of number of high profile applications with high reliability needs. Examples include - electronics in automotive applications may be mounted under the hood or in the trunk of the car resulting in prolonged periods of high temperature exposure followed by operation under vibration while at environmental temperature extremes, and electronics in downhole drilling applications may be mounted close to the drill tip resulting in exposure to transient dynamic loads. High strain rates encountered subsequent to prolonged periods of non-operational high temperature storage encountered in downhole drilling, and automotive underhood applications require the development of computational tools and techniques for prediction of material deformation behavior and reliability. In this study, mechanical properties of lead free SAC105 and SAC305 has been measured for strain rates 1-100 per sec at elevated temperature 200°C after prolonged storage for periods up to 1-year. Stress-Strain curves have been plotted over a wide range of strain rates and temperatures for pristine specimen which have been fabricated using reflow profiles representative of solder-joint production assemblies. The fabricated SAC105 and SAC305 leadfree alloys specimen have been tested at strain rates of 10, 35, 50 and 75 per sec at various operating temperatures of 50°C, 75°C, 100°C, 125°C, 150°C, 175°C, and 200°C. Experimental data for the aged specimen has been fit to the ANAND's viscoplastic model.
{"title":"Effect of Prolonged Storage up to 1-Year on the High Strain Rate Properties of SAC Leadfree Alloys at Operating Temperatures up to 200 °C","authors":"P. Lall, D. Zhang, Vikas Yadav, J. Suhling, David Locker","doi":"10.1109/ECTC.2017.303","DOIUrl":"https://doi.org/10.1109/ECTC.2017.303","url":null,"abstract":"Transient dynamic loads in addition to prolonged periods of high temperature exposure are a part of number of high profile applications with high reliability needs. Examples include - electronics in automotive applications may be mounted under the hood or in the trunk of the car resulting in prolonged periods of high temperature exposure followed by operation under vibration while at environmental temperature extremes, and electronics in downhole drilling applications may be mounted close to the drill tip resulting in exposure to transient dynamic loads. High strain rates encountered subsequent to prolonged periods of non-operational high temperature storage encountered in downhole drilling, and automotive underhood applications require the development of computational tools and techniques for prediction of material deformation behavior and reliability. In this study, mechanical properties of lead free SAC105 and SAC305 has been measured for strain rates 1-100 per sec at elevated temperature 200°C after prolonged storage for periods up to 1-year. Stress-Strain curves have been plotted over a wide range of strain rates and temperatures for pristine specimen which have been fabricated using reflow profiles representative of solder-joint production assemblies. The fabricated SAC105 and SAC305 leadfree alloys specimen have been tested at strain rates of 10, 35, 50 and 75 per sec at various operating temperatures of 50°C, 75°C, 100°C, 125°C, 150°C, 175°C, and 200°C. Experimental data for the aged specimen has been fit to the ANAND's viscoplastic model.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"28 1","pages":"1219-1230"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83643965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xin Zhao, Yifan Jiang, Bo Gao, Kenji Nishiguchi, Y. Fukawa, D. Hopkins
Advanced power module packaging technology is currently being heavily investigated to take full advantage of Wide Band Gap (WBG) power semiconductor devices. As one of most widely applied power module technologies, intelligent power modules, typically for automotive industries, work well to achieve higher operating frequencies with lower losses by integrating gate driver circuits with power semiconductor devices. In this paper, a novel flexible polymer substrate-based intelligent power module is developed and characterized. By applying 80 µm-thick epoxy-resin based flexible dielectric as a substrate, the overall weight and volume of the power module is reduced, as well as the cost, compared with traditional direct bonded copper ceramic-based modules. The performance of the epoxy-resin based dielectric is investigated, and shows that the leakage current of the dielectric at >1.5 kV is less than 20 µA at 250 oC. Double-sided solderable 1.2 kV SiC MOSFETs and Schottky diodes are fabricated and applied in the module without bonding wires, significantly reducing the overall parasitic inductance to
为了充分利用宽带隙(WBG)功率半导体器件的优势，目前正在大力研究先进的功率模块封装技术。智能功率模块是应用最广泛的功率模块技术之一，通常用于汽车工业，通过将栅极驱动电路与功率半导体器件集成在一起，可以很好地实现更高的工作频率和更低的损耗。本文研制了一种基于柔性聚合物基板的智能电源模块。与传统的直接键合铜陶瓷模块相比，采用80 μ m厚的环氧树脂基柔性电介质作为衬底，降低了功率模块的整体重量和体积，降低了成本。研究了环氧树脂基介电材料的性能，结果表明，在250℃时，介电材料在>1.5 kV时的漏电流小于20µA。该模块采用双面可焊1.2 kV SiC mosfet和肖特基二极管，无需焊线，显著降低了整体寄生电感至
{"title":"Novel Polymer Substrate-Based 1.2 kV/40: A Double-Sided Intelligent Power Module","authors":"Xin Zhao, Yifan Jiang, Bo Gao, Kenji Nishiguchi, Y. Fukawa, D. Hopkins","doi":"10.1109/ECTC.2017.285","DOIUrl":"https://doi.org/10.1109/ECTC.2017.285","url":null,"abstract":"Advanced power module packaging technology is currently being heavily investigated to take full advantage of Wide Band Gap (WBG) power semiconductor devices. As one of most widely applied power module technologies, intelligent power modules, typically for automotive industries, work well to achieve higher operating frequencies with lower losses by integrating gate driver circuits with power semiconductor devices. In this paper, a novel flexible polymer substrate-based intelligent power module is developed and characterized. By applying 80 µm-thick epoxy-resin based flexible dielectric as a substrate, the overall weight and volume of the power module is reduced, as well as the cost, compared with traditional direct bonded copper ceramic-based modules. The performance of the epoxy-resin based dielectric is investigated, and shows that the leakage current of the dielectric at >1.5 kV is less than 20 µA at 250 oC. Double-sided solderable 1.2 kV SiC MOSFETs and Schottky diodes are fabricated and applied in the module without bonding wires, significantly reducing the overall parasitic inductance to","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"36 1","pages":"1461-1467"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76419285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Yamaguchi, Y. Fukuhara, Andy Behr, Hirohisa Hino, Yasuhiro Suzuki, Naomichi Ohashi
SAC305 solder paste is commonly used electronic assembly. This solder alloy consists of 96.5% tin, 3% silver, and 0.5% copper and melts at 219 °C. The peak reflow temperature range is typically 240 - 260 °C. With electronic devices such as smartphones, notebook PCs, and tablets becoming thinner, packaging substrates, such as ultra-thin flip chip ball grid arrays (FCBAs), and the printed circuit boards (PCBs) on which they are mounted are becoming thinner. The growing use of thinner substrates is creating manufacturing and reliability challenges. For example, it is increasingly difficult to control the warpage of CPU packages in notebook PCs during the solder reflow process. The result is greater numbers of solder joint defects, including Non-Wet Open (NWO) and Head-on-Pillow (HOP) defects caused by warpage of package substrates and PCBs. These issues have created a demand for low-temperature solders to help reduce warpage and improve SMT assembly yields by adopting lower soldering temperatures. Tin Bismuth (SnBi) eutectic solders have a desirably low melting point of 139 °C. However, the brittleness of the alloy limits commercial use. This situation prompted us to develop a solder paste material that combines low temperature SnBi solder with epoxy resin. This approach enables the concurrent formation of SiBn solder joints and a reinforcing polymer collar via a one pass reflow process. This paper describes the solder joint properties and reliability of this low temperature joint reinforced solder paste (JRP) developed by us, which consists of SnBi solder compounded with epoxy resin. We evaluated the influence of the epoxy resin component in the developed material (JRP) on solder joint reliability. We compared the joint properties of samples made SAC305 solder paste, unreinforced SnBi solder paste and JRP solder paste. The evaluation revealed that the JRP technology alleviates issues associated with the brittleness of SnBi solder by encasing the formed solder joints with a fully cured epoxy resin. Ball joint shear testing, BGA solder joint strength testing, temperature cycle testing, and drop shock testing revealed that low temperature JRP solder paste demonstrated equivalent or better joint properties than those made with SAC305 solder paste.
{"title":"The Influence of Resin Coverage on Reliability for Solder Joints Formed by One-Pass Reflow Using Resin Reinforced Low Temperature Solder Paste","authors":"A. Yamaguchi, Y. Fukuhara, Andy Behr, Hirohisa Hino, Yasuhiro Suzuki, Naomichi Ohashi","doi":"10.1109/ECTC.2017.105","DOIUrl":"https://doi.org/10.1109/ECTC.2017.105","url":null,"abstract":"SAC305 solder paste is commonly used electronic assembly. This solder alloy consists of 96.5% tin, 3% silver, and 0.5% copper and melts at 219 °C. The peak reflow temperature range is typically 240 - 260 °C. With electronic devices such as smartphones, notebook PCs, and tablets becoming thinner, packaging substrates, such as ultra-thin flip chip ball grid arrays (FCBAs), and the printed circuit boards (PCBs) on which they are mounted are becoming thinner. The growing use of thinner substrates is creating manufacturing and reliability challenges. For example, it is increasingly difficult to control the warpage of CPU packages in notebook PCs during the solder reflow process. The result is greater numbers of solder joint defects, including Non-Wet Open (NWO) and Head-on-Pillow (HOP) defects caused by warpage of package substrates and PCBs. These issues have created a demand for low-temperature solders to help reduce warpage and improve SMT assembly yields by adopting lower soldering temperatures. Tin Bismuth (SnBi) eutectic solders have a desirably low melting point of 139 °C. However, the brittleness of the alloy limits commercial use. This situation prompted us to develop a solder paste material that combines low temperature SnBi solder with epoxy resin. This approach enables the concurrent formation of SiBn solder joints and a reinforcing polymer collar via a one pass reflow process. This paper describes the solder joint properties and reliability of this low temperature joint reinforced solder paste (JRP) developed by us, which consists of SnBi solder compounded with epoxy resin. We evaluated the influence of the epoxy resin component in the developed material (JRP) on solder joint reliability. We compared the joint properties of samples made SAC305 solder paste, unreinforced SnBi solder paste and JRP solder paste. The evaluation revealed that the JRP technology alleviates issues associated with the brittleness of SnBi solder by encasing the formed solder joints with a fully cured epoxy resin. Ball joint shear testing, BGA solder joint strength testing, temperature cycle testing, and drop shock testing revealed that low temperature JRP solder paste demonstrated equivalent or better joint properties than those made with SAC305 solder paste.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"7 1","pages":"1398-1404"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84844028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This analysis focuses on two of the primary variations of fan-out wafer level packaging: die-first packaging in which the die are placed face down, and die-last packaging. These two technologies share many of the same activities, but those activities occur in a different order. One key factor setting these two process flows apart is yield. Even with the assumption that the same level of defects are introduced in each process flow, the resulting total yield differs. This paper analyzes the impact of defects on the die-first and die-last processes. Each process is evaluated separately, then the two processes are directly compared across a range of designs, defect density assumptions, and incoming die cost assumptions. The cost of the processing, cost of the incoming die, and the cost of processing and die lost to scrap are included.
{"title":"Yield Comparison of Die-First Face-Down and Die-Last Fan-Out Wafer Level Packaging","authors":"A. Lujan","doi":"10.1109/ECTC.2017.39","DOIUrl":"https://doi.org/10.1109/ECTC.2017.39","url":null,"abstract":"This analysis focuses on two of the primary variations of fan-out wafer level packaging: die-first packaging in which the die are placed face down, and die-last packaging. These two technologies share many of the same activities, but those activities occur in a different order. One key factor setting these two process flows apart is yield. Even with the assumption that the same level of defects are introduced in each process flow, the resulting total yield differs. This paper analyzes the impact of defects on the die-first and die-last processes. Each process is evaluated separately, then the two processes are directly compared across a range of designs, defect density assumptions, and incoming die cost assumptions. The cost of the processing, cost of the incoming die, and the cost of processing and die lost to scrap are included.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"52 1","pages":"1811-1816"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77124438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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