In recent years, continuing enhancement of highly-functional electronic devices, such as mobile terminal devices, has significantly increased the volume and speed of data transmission. This made high-frequency communication for data transmission between electronic devices essential. Thus, device component suppliers must offer products with low transmission loss in high-frequency range. An insulating adhesive film used for a semiconductor package substrate requires component materials which provide low dielectric property and low linear expansion coefficient to achieve higher data transmitting signal, eliminate chip delamination during the mounting process, and prevent internal copper wiring from breaking. Meanwhile, a recent trend of thinner, lighter electronic devices such as smartphones and tablets leads to more consideration of potential solutions including the use of: flexible printed circuit with softness and excellent flexibility, microwiring to better work for high-density wiring on circuit substrate, and a multilayer-thin-film substrate. Providing optimal low linear expansion coefficient is acknowledged as an additional requirement, by which reliable adhesion between layers of different materials in multilayer substrates is ensured. Previously, such insulating adhesive film had not been developed. We have successfully developed an insulating adhesive film for high frequency applications to ensure the following properties to meet the demand. Through our investigation, we attained low dielectric properties, dielectric constant (Dk) of 3.0 and dielectric loss tangent (Df) of 0.0025, by selecting the resin with low polarity molecular structure. Optimization of additives to resin ensured the new film to provide high peeling strength (7 N / cm with copper film) and low modulus (1 GPa or less). Low expansion coefficient (α1: 25 ppm, α2: 100 ppm) was also achieved through selection of a suitable inorganic filler, optimization of filler particle size, and dispersing filler uniformly. Thus, the highly uniform film thickness of the new film enables a multilayer-thin-film structure and also facilitates impedance matching. The developed film facilitates flexible wiring design owing to stable dielectric properties at a high-frequency range (1 to 20 GHz), lower transmission loss, and a lack of directional dependence of material properties. The film also adheres to a smooth copper conductor. This makes microwiring possible and lowers conductor loss (i.e., surface effect). In addition, the film's lower linear expansion coefficient ensures reliability of adhesion between layers of different materials in the package.
{"title":"High Performance Insulating Adhesive Film for High-Frequency Applications","authors":"Junya Sato, S. Teraki, Masaki Yoshida, H. Kondo","doi":"10.1109/ECTC.2017.94","DOIUrl":"https://doi.org/10.1109/ECTC.2017.94","url":null,"abstract":"In recent years, continuing enhancement of highly-functional electronic devices, such as mobile terminal devices, has significantly increased the volume and speed of data transmission. This made high-frequency communication for data transmission between electronic devices essential. Thus, device component suppliers must offer products with low transmission loss in high-frequency range. An insulating adhesive film used for a semiconductor package substrate requires component materials which provide low dielectric property and low linear expansion coefficient to achieve higher data transmitting signal, eliminate chip delamination during the mounting process, and prevent internal copper wiring from breaking. Meanwhile, a recent trend of thinner, lighter electronic devices such as smartphones and tablets leads to more consideration of potential solutions including the use of: flexible printed circuit with softness and excellent flexibility, microwiring to better work for high-density wiring on circuit substrate, and a multilayer-thin-film substrate. Providing optimal low linear expansion coefficient is acknowledged as an additional requirement, by which reliable adhesion between layers of different materials in multilayer substrates is ensured. Previously, such insulating adhesive film had not been developed. We have successfully developed an insulating adhesive film for high frequency applications to ensure the following properties to meet the demand. Through our investigation, we attained low dielectric properties, dielectric constant (Dk) of 3.0 and dielectric loss tangent (Df) of 0.0025, by selecting the resin with low polarity molecular structure. Optimization of additives to resin ensured the new film to provide high peeling strength (7 N / cm with copper film) and low modulus (1 GPa or less). Low expansion coefficient (α1: 25 ppm, α2: 100 ppm) was also achieved through selection of a suitable inorganic filler, optimization of filler particle size, and dispersing filler uniformly. Thus, the highly uniform film thickness of the new film enables a multilayer-thin-film structure and also facilitates impedance matching. The developed film facilitates flexible wiring design owing to stable dielectric properties at a high-frequency range (1 to 20 GHz), lower transmission loss, and a lack of directional dependence of material properties. The film also adheres to a smooth copper conductor. This makes microwiring possible and lowers conductor loss (i.e., surface effect). In addition, the film's lower linear expansion coefficient ensures reliability of adhesion between layers of different materials in the package.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"9 1","pages":"1322-1327"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85028814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yézouma D. Zonou, S. Bernabé, D. Fowler, M. Francou, O. Castany, P. Arguel
This paper studies the self-alignment properties between two chips that are stacked on top of each other with copper pillars micro-bumps. The chips feature alignment marks used for measuring the resulting offset after assembly. The accuracy of the alignment is found to be better than 0.5 µm in × and y directions, depending on the process. The chips also feature waveguides and vertical grating couplers (VGC) fabricated in the front-end-of-line (FEOL) and organized in order to realize an optical interconnection between the chips. The coupling of light between the chips is measured and compared to numerical simulation. This high accuracy self-alignment was obtained after studying the impact of flux and fluxless treatments on the wetting of the pads and the successful assembly yield. The composition of the bump surface was analyzed with Time-of-Flight Secondary Ions Mass Spectroscopy (ToF-SIMS) in order to understand the impact of each treatment. This study confirms that copper pillars micro-bumps can be used to self-align photonic integrated circuits (PIC) with another die (for example a microlens array) in order to achieve high throughput alignment of optical fiber to the PIC.
{"title":"Self-Alignment with Copper Pillars Micro-Bumps for Positioning Optical Devices at Submicronic Accuracy","authors":"Yézouma D. Zonou, S. Bernabé, D. Fowler, M. Francou, O. Castany, P. Arguel","doi":"10.1109/ECTC.2017.234","DOIUrl":"https://doi.org/10.1109/ECTC.2017.234","url":null,"abstract":"This paper studies the self-alignment properties between two chips that are stacked on top of each other with copper pillars micro-bumps. The chips feature alignment marks used for measuring the resulting offset after assembly. The accuracy of the alignment is found to be better than 0.5 µm in × and y directions, depending on the process. The chips also feature waveguides and vertical grating couplers (VGC) fabricated in the front-end-of-line (FEOL) and organized in order to realize an optical interconnection between the chips. The coupling of light between the chips is measured and compared to numerical simulation. This high accuracy self-alignment was obtained after studying the impact of flux and fluxless treatments on the wetting of the pads and the successful assembly yield. The composition of the bump surface was analyzed with Time-of-Flight Secondary Ions Mass Spectroscopy (ToF-SIMS) in order to understand the impact of each treatment. This study confirms that copper pillars micro-bumps can be used to self-align photonic integrated circuits (PIC) with another die (for example a microlens array) in order to achieve high throughput alignment of optical fiber to the PIC.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"17 1","pages":"557-562"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81869095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Wei, T. Tabuchi, T. Lazerand, Christopher Johnston, K. Mackenzie, M. Notarianni
Comprehensive investigations were conducted on identifying integration efforts needed to adapt plasma dicing technology in BEOL pre-production environments. First, the authors identified the suitable process flows. Within the process flow, laser grooving before plasma dicing was shown to be a key unit process to control resulting die sidewall quality. Significant improvement on laser grooving quality has been demonstrated. Through these efforts, extremely narrow kerfs and near ideal dies strengths were achieved on bare Si dies. Plasma dicing process generates fluorinated polymer residues on both Si die sidewalls and under the topography overhangs on wafer surfaces, such as under the solder balls or microbumps. Certain areas cannot be cleaned by in-chamber post-treatments. Multiple cleaning methods demonstrated process capability and compatibility to singulated dies-on-tape handling. Lastly, although many methods exist commercially for backmetal and DAF separations, the authors' investigation is still inconclusive on one preferred process for post-plasma dicing die separations.
{"title":"Plasma Dicing Fully Integrated Process-Flows Suitable for BEOL Advanced Packaging Fabrications","authors":"F. Wei, T. Tabuchi, T. Lazerand, Christopher Johnston, K. Mackenzie, M. Notarianni","doi":"10.1109/ECTC.2017.269","DOIUrl":"https://doi.org/10.1109/ECTC.2017.269","url":null,"abstract":"Comprehensive investigations were conducted on identifying integration efforts needed to adapt plasma dicing technology in BEOL pre-production environments. First, the authors identified the suitable process flows. Within the process flow, laser grooving before plasma dicing was shown to be a key unit process to control resulting die sidewall quality. Significant improvement on laser grooving quality has been demonstrated. Through these efforts, extremely narrow kerfs and near ideal dies strengths were achieved on bare Si dies. Plasma dicing process generates fluorinated polymer residues on both Si die sidewalls and under the topography overhangs on wafer surfaces, such as under the solder balls or microbumps. Certain areas cannot be cleaned by in-chamber post-treatments. Multiple cleaning methods demonstrated process capability and compatibility to singulated dies-on-tape handling. Lastly, although many methods exist commercially for backmetal and DAF separations, the authors' investigation is still inconclusive on one preferred process for post-plasma dicing die separations.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"104 1","pages":"350-357"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81898701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Chui, W. Loh, Xiangy-Yu Wang, Zhaohui Chen, Mingbin Yu
Significant stress is induced in the crystalline Si area around a Cu-filled Through Silicon Via (TSV) due to the large mismatch in the co-efficient of thermal expansion (CTE) between Si and Cu. As a result, CMOS devices fabricated within the stressed Si region will show undesired variations in their electrical performance. This paper reports a novel method to isolate the TSV-induced stress from active CMOS devices through the formation of embedded air-gaps. As the air-gaps are embedded in the Si, stress isolation can be done without compromising on the usable Si area. Formation of the air-gaps have been demonstrated experimentally using a high temperature anneal in a de-oxidizing ambient. Stress reduction in the Si lattice, in the presence of the embedded air-gaps, will be studied through thermo-mechanical stress simulation. Effect of the impact of air-gap design will also be discussed.
由于Si和Cu之间的热膨胀系数(CTE)的巨大不匹配，在Cu填充的Through Silicon Via (TSV)周围的晶体Si区域产生了显著的应力。因此，在应力Si区域内制造的CMOS器件将在其电气性能上显示出不希望的变化。本文报道了一种通过形成嵌入式气隙来隔离有源CMOS器件tsv诱导应力的新方法。由于气隙嵌入在硅中，因此可以在不影响可用硅面积的情况下进行应力隔离。气隙的形成已经在脱氧环境中用高温退火实验证明了。在嵌入气隙的情况下，Si晶格中的应力减小将通过热机械应力模拟进行研究。对气隙设计的影响也进行了讨论。
{"title":"A Novel Method for Air-Gap Formation around Via-Middle (VM) TSVs for Effective Reduction in Keep-Out Zones (KOZ)","authors":"K. Chui, W. Loh, Xiangy-Yu Wang, Zhaohui Chen, Mingbin Yu","doi":"10.1109/ECTC.2017.238","DOIUrl":"https://doi.org/10.1109/ECTC.2017.238","url":null,"abstract":"Significant stress is induced in the crystalline Si area around a Cu-filled Through Silicon Via (TSV) due to the large mismatch in the co-efficient of thermal expansion (CTE) between Si and Cu. As a result, CMOS devices fabricated within the stressed Si region will show undesired variations in their electrical performance. This paper reports a novel method to isolate the TSV-induced stress from active CMOS devices through the formation of embedded air-gaps. As the air-gaps are embedded in the Si, stress isolation can be done without compromising on the usable Si area. Formation of the air-gaps have been demonstrated experimentally using a high temperature anneal in a de-oxidizing ambient. Stress reduction in the Si lattice, in the presence of the embedded air-gaps, will be studied through thermo-mechanical stress simulation. Effect of the impact of air-gap design will also be discussed.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"2 1","pages":"1257-1262"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81990427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gerald Gourdin, O. Phillips, J. Schwartz, A. Engler, P. Kohl
Electronic devices that can physically or functionally disintegrate on-demand have applications as remote sensors, bioelectronics for diagnostics, and other multifunctional devices with temporal functional profiles. This emerging field requires materials, devices, and systems which effectively disappear, (i.e. vaporize), with little or no traceable remains. Prior efforts have achieved transience with devices either submerged in an aqueous solution, which degrades the materials over time, or by triggering an inundation of the materials with a liquid solution. Neither scenario allow for both control of the life cycle of the system and assurance that transience would be complete. Metastable polymers, which can be induced to depolymerize rapidly through a specific trigger, offers a more versatile approach to selecting materials and allows for more control over the device's lifetime. A triggerable, transient material which vaporizes on command was prepared by the addition of a photo-acid generator (PAG) to an acid-sensitive metastable polymer, where the rate of degradation can be controlled by the concentration of the PAG and the intensity of light irradiance. In this work, a transient electronic component, a multilayer interconnect board was fabricated using a PAG-loaded, cyclic poly(phthalaldehyde) substrate. The p(PHA) material used to fabricate the dielectric acts as the support substrate for the metal routing layers, where the conductive 'wiring' was composed of a silver nanoparticle-filled p(PHA) formulation. Elastic modulus, resistivity, connectivity, and conductor sheet resistance of the individual components were evaluated and transience was demonstrated.
{"title":"Phototriggerable, Fully Transient Electronics: Component and Device Fabrication","authors":"Gerald Gourdin, O. Phillips, J. Schwartz, A. Engler, P. Kohl","doi":"10.1109/ECTC.2017.129","DOIUrl":"https://doi.org/10.1109/ECTC.2017.129","url":null,"abstract":"Electronic devices that can physically or functionally disintegrate on-demand have applications as remote sensors, bioelectronics for diagnostics, and other multifunctional devices with temporal functional profiles. This emerging field requires materials, devices, and systems which effectively disappear, (i.e. vaporize), with little or no traceable remains. Prior efforts have achieved transience with devices either submerged in an aqueous solution, which degrades the materials over time, or by triggering an inundation of the materials with a liquid solution. Neither scenario allow for both control of the life cycle of the system and assurance that transience would be complete. Metastable polymers, which can be induced to depolymerize rapidly through a specific trigger, offers a more versatile approach to selecting materials and allows for more control over the device's lifetime. A triggerable, transient material which vaporizes on command was prepared by the addition of a photo-acid generator (PAG) to an acid-sensitive metastable polymer, where the rate of degradation can be controlled by the concentration of the PAG and the intensity of light irradiance. In this work, a transient electronic component, a multilayer interconnect board was fabricated using a PAG-loaded, cyclic poly(phthalaldehyde) substrate. The p(PHA) material used to fabricate the dielectric acts as the support substrate for the metal routing layers, where the conductive 'wiring' was composed of a silver nanoparticle-filled p(PHA) formulation. Elastic modulus, resistivity, connectivity, and conductor sheet resistance of the individual components were evaluated and transience was demonstrated.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"20 1","pages":"190-196"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82052801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Glass and fused silica are promising material used as a substrate for RF components because of good electrical properties such as low permittivity and low dielectric loss tangent. What's more, glass and fused silica have higher bulk resistance because of insulation material, and superior stabilities against environmental changes as packaging level. This study explores, firstly a methodology and measurement results of high frequency characteristic of glass and fused silica up to 110 GHz, secondly, microfabrication technologies for glass and fused silica and those demonstration work especially about through via formation and metallization in prospect of 3D integrated RF packaging. Lastly, future development subjects related to RF components using glass or fused silica are discussed.
{"title":"Development of High Frequency Device Using Glass or Fused Silica with 3D Integration","authors":"Shintaro Takahashi, Y. Sato, K. Horiuchi, M. Ono","doi":"10.1109/ECTC.2017.124","DOIUrl":"https://doi.org/10.1109/ECTC.2017.124","url":null,"abstract":"Glass and fused silica are promising material used as a substrate for RF components because of good electrical properties such as low permittivity and low dielectric loss tangent. What's more, glass and fused silica have higher bulk resistance because of insulation material, and superior stabilities against environmental changes as packaging level. This study explores, firstly a methodology and measurement results of high frequency characteristic of glass and fused silica up to 110 GHz, secondly, microfabrication technologies for glass and fused silica and those demonstration work especially about through via formation and metallization in prospect of 3D integrated RF packaging. Lastly, future development subjects related to RF components using glass or fused silica are discussed.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"14 1","pages":"758-763"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80174034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Wietstruck, S. Marschmeyer, M. Lisker, A. Krueger, D. Wolansky, P. Kulse, A. Goeritz, M. Inac, T. Voß, A. Mai, M. Kaynak
In this work, the development of engineered silicon substrates for a novel via-middle TSV integration concept is demonstrated. These substrates include 3D buried etch-stop layers which provide both an ideal vertical and lateral etch-stop for TSV trench etching thus enabling the simultaneous realization of different size of TSVs on the same silicon substrate. Beside standard BiCMOS and TSV fabrication steps, only a low-temperature fusion bonding process is applied and the integration concept is realized without adding an additional mask to the established BiCMOS via-middle TSV technology. As a result, the developed technique is very promising to realize different dimensions of TSVs on the same substrate for future smart system applications.
{"title":"Accurate Depth Control of Through-Silicon Vias by Substrate Integrated Etch Stop Layers","authors":"M. Wietstruck, S. Marschmeyer, M. Lisker, A. Krueger, D. Wolansky, P. Kulse, A. Goeritz, M. Inac, T. Voß, A. Mai, M. Kaynak","doi":"10.1109/ECTC.2017.120","DOIUrl":"https://doi.org/10.1109/ECTC.2017.120","url":null,"abstract":"In this work, the development of engineered silicon substrates for a novel via-middle TSV integration concept is demonstrated. These substrates include 3D buried etch-stop layers which provide both an ideal vertical and lateral etch-stop for TSV trench etching thus enabling the simultaneous realization of different size of TSVs on the same silicon substrate. Beside standard BiCMOS and TSV fabrication steps, only a low-temperature fusion bonding process is applied and the integration concept is realized without adding an additional mask to the established BiCMOS via-middle TSV technology. As a result, the developed technique is very promising to realize different dimensions of TSVs on the same substrate for future smart system applications.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"51 1 1","pages":"53-60"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76341298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tailong Shi, C. Buch, V. Smet, Y. Sato, L. Parthier, F. Wei, C. Lee, V. Sundaram, R. Tummala
Ultra-thin, panel-level glass fan-out packages (GFO) were demonstrated for next-generation fan-out packaging with high-density high-performance digital, analog, power, RF and mm-wave applications. The key advances with GFO include: 1) large area panel-scalable glass substrate processes with lower cost, 2) silicon-like RDL on large panels with 1-2 µm critical dimensions (CD), 3) lower interconnect loss and 4) improved board-level reliability enabled by the tailorability of the CTE of the glass panels and compliant interconnections. Daisy-chain test dies were used to emulate an embedded device with the size of 6.469 mm × 5.902 mm, thickness of 75 µm and pad pitch of 65 µm. Glass panels with 70 µm thickness and through-glass cavities were first fabricated, and then bonded onto a 50 µm thick glass panel carrier using adhesives. After glass-to-glass bonding, the test dies were assembled into the glass cavities using a high-speed placement tool. RDL polymers were then laminated onto both sides and cured to minimize the warpage of the ultra-thin package. A surface planar tool was then used to planarize the surface of the panel to expose the copper microbumps on the die, followed by a standard semi-additive process (SAP) for the fan-out RDL layer. The shift and warpage of the die were characterized during the multiple process steps. Initial modeling and measured results indicate the potential for less than 5 µm die shift and less than 10-15 µm warpage across a 300 mm × 300 mm panel size.
展示了超薄面板级玻璃扇出封装(GFO)，用于高密度高性能数字、模拟、功率、射频和毫米波应用的下一代扇出封装。GFO的关键进步包括:1)成本更低的大面积面板可扩展玻璃基板工艺，2)1-2微米临界尺寸(CD)的大型面板上的类硅RDL, 3)更低的互连损耗，4)通过玻璃面板的CTE可定制性和兼容互连提高了板级可靠性。采用雏菊链测试模对尺寸为6.469 mm × 5.902 mm、厚度为75µm、垫距为65µm的嵌入式器件进行仿真。首先制作厚度为70µm的玻璃板和透玻璃腔，然后使用粘合剂将其粘合到50µm厚的玻璃板载体上。在玻璃与玻璃粘合后，使用高速放置工具将测试模具组装到玻璃腔中。然后将RDL聚合物层压在两侧并固化，以尽量减少超薄封装的翘曲。然后使用表面平面工具将面板表面平面化，以暴露模具上的铜微凸起，然后使用标准的半添加工艺(SAP)进行扇出RDL层。在多个工艺步骤中，对模具的移位和翘曲进行了表征。初始建模和测量结果表明，在300 mm × 300 mm面板尺寸上，模移小于5 μ m，翘曲小于10-15 μ m。
{"title":"First Demonstration of Panel Glass Fan-Out (GFO) Packages for High I/O Density and High Frequency Multi-chip Integration","authors":"Tailong Shi, C. Buch, V. Smet, Y. Sato, L. Parthier, F. Wei, C. Lee, V. Sundaram, R. Tummala","doi":"10.1109/ECTC.2017.287","DOIUrl":"https://doi.org/10.1109/ECTC.2017.287","url":null,"abstract":"Ultra-thin, panel-level glass fan-out packages (GFO) were demonstrated for next-generation fan-out packaging with high-density high-performance digital, analog, power, RF and mm-wave applications. The key advances with GFO include: 1) large area panel-scalable glass substrate processes with lower cost, 2) silicon-like RDL on large panels with 1-2 µm critical dimensions (CD), 3) lower interconnect loss and 4) improved board-level reliability enabled by the tailorability of the CTE of the glass panels and compliant interconnections. Daisy-chain test dies were used to emulate an embedded device with the size of 6.469 mm × 5.902 mm, thickness of 75 µm and pad pitch of 65 µm. Glass panels with 70 µm thickness and through-glass cavities were first fabricated, and then bonded onto a 50 µm thick glass panel carrier using adhesives. After glass-to-glass bonding, the test dies were assembled into the glass cavities using a high-speed placement tool. RDL polymers were then laminated onto both sides and cured to minimize the warpage of the ultra-thin package. A surface planar tool was then used to planarize the surface of the panel to expose the copper microbumps on the die, followed by a standard semi-additive process (SAP) for the fan-out RDL layer. The shift and warpage of the die were characterized during the multiple process steps. Initial modeling and measured results indicate the potential for less than 5 µm die shift and less than 10-15 µm warpage across a 300 mm × 300 mm panel size.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"65 1","pages":"41-46"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75803256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shidong Li, Joseph Ross, Steven P. Ostrander, K. Sikka, Nicolas E. Pizzuti
Resin cracking is a common failure mechanism in electronic packaging using organic chip carrier. Chip carrier made of organic material has been industry standard for the past decade as they provide significant advantages over the ceramic dielectric-based predecessors in manufacturing cost and electrical performance. However, the CTE mismatch between the silicon chip and the organic laminate leads to substantial stress in the laminate particularly at the outmost fiber. Such stress when combined with the temperature fluctuation in field operation, causes low cycle fatigue in dielectric layer and eventually impairs the circuits in the laminate, which is known as dielectric resin cracking failure. During the evolution of organic laminate technology, the demands for high speed transmission drives the need for material with low dielectric loss, which usually is associated with low ductility and in turn makes dielectric resin cracking an even greater concern. A cost effective evaluation method for testing the resin cracking robustness of an interested material before building expensive laminate is therefore critical. This paper focuses on correlation of raw dielectric film material properties and the reliability performance of the corresponding electronic package. A fabricated in-house strain controlled fatigue testing machine will be introduced. The fatigue life vs strain of a typical dielectric material will be discussed. A flip chip package using this dielectric material will be described. Its resin cracking failure rate subjected to thermal cycling stress with various delta T will be illustrated. The thermal-mechanical modeling methodology will be outlined and verification of simulations with experimental results will be presented. A predictive model for correlation of dry film flex fatigue life and the corresponding resin cracking risk in a flip chip package will be proposed.
{"title":"Correlation of Dielectric Film Flex Fatigue Resistance and Package Resin Cracking Failure","authors":"Shidong Li, Joseph Ross, Steven P. Ostrander, K. Sikka, Nicolas E. Pizzuti","doi":"10.1109/ECTC.2017.259","DOIUrl":"https://doi.org/10.1109/ECTC.2017.259","url":null,"abstract":"Resin cracking is a common failure mechanism in electronic packaging using organic chip carrier. Chip carrier made of organic material has been industry standard for the past decade as they provide significant advantages over the ceramic dielectric-based predecessors in manufacturing cost and electrical performance. However, the CTE mismatch between the silicon chip and the organic laminate leads to substantial stress in the laminate particularly at the outmost fiber. Such stress when combined with the temperature fluctuation in field operation, causes low cycle fatigue in dielectric layer and eventually impairs the circuits in the laminate, which is known as dielectric resin cracking failure. During the evolution of organic laminate technology, the demands for high speed transmission drives the need for material with low dielectric loss, which usually is associated with low ductility and in turn makes dielectric resin cracking an even greater concern. A cost effective evaluation method for testing the resin cracking robustness of an interested material before building expensive laminate is therefore critical. This paper focuses on correlation of raw dielectric film material properties and the reliability performance of the corresponding electronic package. A fabricated in-house strain controlled fatigue testing machine will be introduced. The fatigue life vs strain of a typical dielectric material will be discussed. A flip chip package using this dielectric material will be described. Its resin cracking failure rate subjected to thermal cycling stress with various delta T will be illustrated. The thermal-mechanical modeling methodology will be outlined and verification of simulations with experimental results will be presented. A predictive model for correlation of dry film flex fatigue life and the corresponding resin cracking risk in a flip chip package will be proposed.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"2 1","pages":"491-496"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82239136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, a nanocomposite interconnect consisting of ferromagnetic and non-ferromagnetic materials is theoretically and experimentally investigated. The relative magnetic permeability of ferromagnetic nanofibers becomes negative above the ferromagnetic resonance frequency and induces eddy current in an opposite direction of that of non-ferromagnetic conductor, resulting in eddy current cancellation. This ultimately suppresses the skin effect contributing to the reduction of radio frequency resistance. For nanofiber fabrication, an alternating electrospinning technique is utilized to improve the nanofiber growth rate and increase the thickness of the nanofiber stack. Aligned nanofibers are obtained by dynamically rotating mandrel combined with alternating electrospinning. Nanoporous conductors with the composition of non-ferromagnetic and ferromagnetic conductors are realized by electrochemical deposition of copper with the ferromagnetic nanofiber stack as a plating template.
{"title":"Fabrication and Characterization of Nanoporous Metallic Interconnects Using Electrospun Nanofiber Template and Electrochemical Deposition","authors":"Sheng-Po Fang, Seahee Hwangbo, Hyowon An, Y. Yoon","doi":"10.1109/ECTC.2017.207","DOIUrl":"https://doi.org/10.1109/ECTC.2017.207","url":null,"abstract":"In this work, a nanocomposite interconnect consisting of ferromagnetic and non-ferromagnetic materials is theoretically and experimentally investigated. The relative magnetic permeability of ferromagnetic nanofibers becomes negative above the ferromagnetic resonance frequency and induces eddy current in an opposite direction of that of non-ferromagnetic conductor, resulting in eddy current cancellation. This ultimately suppresses the skin effect contributing to the reduction of radio frequency resistance. For nanofiber fabrication, an alternating electrospinning technique is utilized to improve the nanofiber growth rate and increase the thickness of the nanofiber stack. Aligned nanofibers are obtained by dynamically rotating mandrel combined with alternating electrospinning. Nanoporous conductors with the composition of non-ferromagnetic and ferromagnetic conductors are realized by electrochemical deposition of copper with the ferromagnetic nanofiber stack as a plating template.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"55 1","pages":"1578-1583"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78855993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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