Kisu Joo, Tae-Ryong Kim, Jung-Woo Hwang, Jin-Ho Yoon, Se Young Jeong, M. Yim
A variety of shaped Ag particles was tested to obtain optimized electrical resistivity and mechanical reliability. We also studied the effect of the spray machine's parameters such as pressure, speed, and droplet size on uniformity of sprayed conductive film. The resulting Ag paste containing flake shaped Ag particles showed about 1×10-7m electrical conductivity. The aspect ratio of top to side coating thickness of the resulting conductive films on EMC mold was 1:0.5~1:0.7, which could be controllable. We found that the best electrical conductivity and mechanical reliability was achieved when only flake shaped Ag were used. Finally, shield effectiveness of resulting EMI shielding film made of Ag and matrix is as high as 60dB, 65dB, 70dB at 5um, 10um, 20um-thick film, respectively by ASTM method.
{"title":"Package-Level EMI Shielding Technology with Silver Paste for Various Applications","authors":"Kisu Joo, Tae-Ryong Kim, Jung-Woo Hwang, Jin-Ho Yoon, Se Young Jeong, M. Yim","doi":"10.1109/ECTC.2017.327","DOIUrl":"https://doi.org/10.1109/ECTC.2017.327","url":null,"abstract":"A variety of shaped Ag particles was tested to obtain optimized electrical resistivity and mechanical reliability. We also studied the effect of the spray machine's parameters such as pressure, speed, and droplet size on uniformity of sprayed conductive film. The resulting Ag paste containing flake shaped Ag particles showed about 1×10-7m electrical conductivity. The aspect ratio of top to side coating thickness of the resulting conductive films on EMC mold was 1:0.5~1:0.7, which could be controllable. We found that the best electrical conductivity and mechanical reliability was achieved when only flake shaped Ag were used. Finally, shield effectiveness of resulting EMI shielding film made of Ag and matrix is as high as 60dB, 65dB, 70dB at 5um, 10um, 20um-thick film, respectively by ASTM method.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"10 1","pages":"1736-1741"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84725713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Zhong, N. Zhao, H. T. Ma, W. Dong, M. Huang, C. Wong
With regulations mandating industry toward Pb-free solders in all electronics, the development of interconnecting materials capable of withstanding harsh thermal conditions becomes one of the key technological elements for the development of next generation wide band-gap semiconductors. By reflowing Ni/Sn/Ni interconnects under temperature gradient, a new transient liquid phase (TLP) bonding process is proposed for high temperature packaging applications in this study. The evolution of the dominant Ni3Sn4 intermetallic compounds (IMCs) depends strongly on temperature gradient. The essential cause of such dependence is attributed to the different amounts of Ni atomic fluxes being introduced into the interfacial reaction between the new and conventional TLP bonding processes. Under the effect of temperature gradient, mass thermomigration of Ni atoms from the hot end toward the cold end promotes the total Ni atomic flux for interfacial reaction. As a result, the total growth of IMCs is significantly accelerated. The new TLP bonding process consumes limited cold end Ni substrate. The mechanism for the new TLP bonding process is discussed and experimentally verified in this study.
{"title":"Low Temperature Ni/Sn/Ni Transient Liquid Phase Bonding for High Temperature Packaging Applications by Imposing Temperature Gradient","authors":"Y. Zhong, N. Zhao, H. T. Ma, W. Dong, M. Huang, C. Wong","doi":"10.1109/ECTC.2017.267","DOIUrl":"https://doi.org/10.1109/ECTC.2017.267","url":null,"abstract":"With regulations mandating industry toward Pb-free solders in all electronics, the development of interconnecting materials capable of withstanding harsh thermal conditions becomes one of the key technological elements for the development of next generation wide band-gap semiconductors. By reflowing Ni/Sn/Ni interconnects under temperature gradient, a new transient liquid phase (TLP) bonding process is proposed for high temperature packaging applications in this study. The evolution of the dominant Ni3Sn4 intermetallic compounds (IMCs) depends strongly on temperature gradient. The essential cause of such dependence is attributed to the different amounts of Ni atomic fluxes being introduced into the interfacial reaction between the new and conventional TLP bonding processes. Under the effect of temperature gradient, mass thermomigration of Ni atoms from the hot end toward the cold end promotes the total Ni atomic flux for interfacial reaction. As a result, the total growth of IMCs is significantly accelerated. The new TLP bonding process consumes limited cold end Ni substrate. The mechanism for the new TLP bonding process is discussed and experimentally verified in this study.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"112 1","pages":"411-416"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80659290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ning Ge, Jarrid A. Wittkopf, S. Simske, S. Barcelo, R. Ionescu, D. Lazaroff, Kevin Dooley, A. Rogacs, H. Holder
Electroplating is a low cost process where metal ionsin a solution are reduced by an applied electric field onto aconductive substrate. This process has been studied extensively, but is still critical for modern technology and R&D. In the HPinkjet printing business, electroplating is primarily used in themanufacturing the orifice plate (OP) for integrated print-headproducts. To extend the OP functionality, a novel cost-effectivethree-dimensional (3D) OP has been developed to addressnumerous micro-electro-mechanical systems (MEMS) applications, including surface enhanced Raman spectroscopy(SERS).
{"title":"3D Monolithic Metal Orifice Plate for SERS Application: A Showcase of Low Cost MEMS Packaging","authors":"Ning Ge, Jarrid A. Wittkopf, S. Simske, S. Barcelo, R. Ionescu, D. Lazaroff, Kevin Dooley, A. Rogacs, H. Holder","doi":"10.1109/ECTC.2017.93","DOIUrl":"https://doi.org/10.1109/ECTC.2017.93","url":null,"abstract":"Electroplating is a low cost process where metal ionsin a solution are reduced by an applied electric field onto aconductive substrate. This process has been studied extensively, but is still critical for modern technology and R&D. In the HPinkjet printing business, electroplating is primarily used in themanufacturing the orifice plate (OP) for integrated print-headproducts. To extend the OP functionality, a novel cost-effectivethree-dimensional (3D) OP has been developed to addressnumerous micro-electro-mechanical systems (MEMS) applications, including surface enhanced Raman spectroscopy(SERS).","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"937-942"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88192927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Martin, S. Kamlapurkar, J. Nah, N. Marchack, T. Barwicz
Self-aligned flip-chip assembly with sub-micron accuracy is of particular importance to low-cost manufacturing of single-mode opto-electronic components. The concept of alignment via surface tension force of melted solder has been proposed over two decades ago and appears simple. Yet, its effective working into manufacturing requires solving a few fundamental issues. In prior work, we introduced the concept of solder reservoirs which provide a solder volume self-balancing mechanism to notably enhance self-alignment yield. In this paper, we show that the effectiveness of reservoirs is impeded when the solder wetting of pads or the solder mobility between pads and reservoirs is limited. We therefore studied a wide variety of metal stacks and identified candidates for substantial wetting and solder mobility improvement. We ranked the metal stacks for solder mobility using traditional wetting angles as well as speed of wetting along narrow tracks. First test parts, manufactured with the improved metal stacks, show the expected benefit in increased yield for chip alignment.
{"title":"Solder Mobility for High-Yield Self-Aligned Flip-Chip Assembly","authors":"Y. Martin, S. Kamlapurkar, J. Nah, N. Marchack, T. Barwicz","doi":"10.1109/ECTC.2017.203","DOIUrl":"https://doi.org/10.1109/ECTC.2017.203","url":null,"abstract":"Self-aligned flip-chip assembly with sub-micron accuracy is of particular importance to low-cost manufacturing of single-mode opto-electronic components. The concept of alignment via surface tension force of melted solder has been proposed over two decades ago and appears simple. Yet, its effective working into manufacturing requires solving a few fundamental issues. In prior work, we introduced the concept of solder reservoirs which provide a solder volume self-balancing mechanism to notably enhance self-alignment yield. In this paper, we show that the effectiveness of reservoirs is impeded when the solder wetting of pads or the solder mobility between pads and reservoirs is limited. We therefore studied a wide variety of metal stacks and identified candidates for substantial wetting and solder mobility improvement. We ranked the metal stacks for solder mobility using traditional wetting angles as well as speed of wetting along narrow tracks. First test parts, manufactured with the improved metal stacks, show the expected benefit in increased yield for chip alignment.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"19 1","pages":"667-674"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90372833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, carbon nanotube (CNT) and Ni-coating modified CNT (Ni-CNT) were compared as the reinforcing dopants in the Sn57.6Bi0.4Ag solder joints. The comparisons were made in three main aspects, including the dispersion of the dopants, the micromorphology evolution of the solder matrix and the reinforcement of reliability performance of the solder joints. The dispersion was evaluated via observing the agglomeration of dopants. Micromorphology changes in the ball grid array (BGA) solder joints were detected via optical and scanning electron microscopy. Ball shear testing was applied to assess the bonding strength of the doped solder joints. Thermal shock testing was used to estimate the reliability performance. According to the results, the dispersion process of the CNT is greatly optimized by applying Ni coating, eliminating the agglomeration of CNT in the solder joints. Furthermore, the mechanical performance of the solder joints containing Ni-CNT performed better. However, the reliability performance became worse as the amount of doping increased. This work contributes to a better understanding on the impact of the CNT dispersion and the effectiveness of nickel-coating modified CNTs in the solder joints.
{"title":"Effect of Nickel-Coating Modified CNTs on the Dopant Dispersion and Performance of BGA Solder Joints","authors":"Huayu Sun, Xiao Hu, Y. Chan, Fengshun Wu","doi":"10.1109/ECTC.2017.21","DOIUrl":"https://doi.org/10.1109/ECTC.2017.21","url":null,"abstract":"In this paper, carbon nanotube (CNT) and Ni-coating modified CNT (Ni-CNT) were compared as the reinforcing dopants in the Sn57.6Bi0.4Ag solder joints. The comparisons were made in three main aspects, including the dispersion of the dopants, the micromorphology evolution of the solder matrix and the reinforcement of reliability performance of the solder joints. The dispersion was evaluated via observing the agglomeration of dopants. Micromorphology changes in the ball grid array (BGA) solder joints were detected via optical and scanning electron microscopy. Ball shear testing was applied to assess the bonding strength of the doped solder joints. Thermal shock testing was used to estimate the reliability performance. According to the results, the dispersion process of the CNT is greatly optimized by applying Ni coating, eliminating the agglomeration of CNT in the solder joints. Furthermore, the mechanical performance of the solder joints containing Ni-CNT performed better. However, the reliability performance became worse as the amount of doping increased. This work contributes to a better understanding on the impact of the CNT dispersion and the effectiveness of nickel-coating modified CNTs in the solder joints.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"401 1","pages":"1981-1986"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76695487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recently, silver solid solution phase with indium, (Ag)-xxIn, has been demonstrated to be one of potential candidates of metallic packaging material for future high-power electronics bonding and interconnection applications due to its great anti-tarnishing property and superior mechanical properties, such as high ductility and high ultimate tensile strength. To further explore and utilize its great potential for electronic packaging applications, the authors have studied the methodology in fabricating silver solid solution thin film layer on copper substrates as its coating layer, using E-beam evaporation deposition. The grazing incidence X-ray diffraction (GIXRD) and X-ray photoelectron spectra (XPS) were used in couple to study the surface composition and thin film quality of the silver-indium solid solution layer on copper substrates. High quality homogenous coating layers with various compositions have been successfully fabricated on copper substrates. It is worthwhile noticing that additional annealing steps are not needed to achieve the homogenous silver-indium solid solution layers. Subsequent solid-state bonding experiments have shown the good bondability of the resulting coating layer of silver-indium solid solution with their cross-sectional optical and scanning electron microscope (SEM) images. Accordingly, the resulting copper substrates with silver-indium solid solution coatings should have a great potential to be used as a highly conductive bondable substrate for high-power electronics and photonics applications.
{"title":"Bondable Copper Substrates with Silver Solid Solution Coatings for High-Power Electronic Applications","authors":"Yongjun Huo, Chin C. Lee","doi":"10.1109/ECTC.2017.188","DOIUrl":"https://doi.org/10.1109/ECTC.2017.188","url":null,"abstract":"Recently, silver solid solution phase with indium, (Ag)-xxIn, has been demonstrated to be one of potential candidates of metallic packaging material for future high-power electronics bonding and interconnection applications due to its great anti-tarnishing property and superior mechanical properties, such as high ductility and high ultimate tensile strength. To further explore and utilize its great potential for electronic packaging applications, the authors have studied the methodology in fabricating silver solid solution thin film layer on copper substrates as its coating layer, using E-beam evaporation deposition. The grazing incidence X-ray diffraction (GIXRD) and X-ray photoelectron spectra (XPS) were used in couple to study the surface composition and thin film quality of the silver-indium solid solution layer on copper substrates. High quality homogenous coating layers with various compositions have been successfully fabricated on copper substrates. It is worthwhile noticing that additional annealing steps are not needed to achieve the homogenous silver-indium solid solution layers. Subsequent solid-state bonding experiments have shown the good bondability of the resulting coating layer of silver-indium solid solution with their cross-sectional optical and scanning electron microscope (SEM) images. Accordingly, the resulting copper substrates with silver-indium solid solution coatings should have a great potential to be used as a highly conductive bondable substrate for high-power electronics and photonics applications.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"496 1","pages":"166-172"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77026322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
All electronic packages involve with a multi-material system, in which many of the materials or films are susceptible to moisture absorption. Despite dissimilar material properties, moisture transports in a multi-material system from a high "water activity" region to a low one, where water activity is a measure of water energy in a specific substance. This, however, has not been well recognized in electronic packaging industry. Furthermore, moisture concentration gradient is often deemed as the driving force for moisture transport, which inevitably poses a challenging discontinuity issue at interface for moisture diffusion in multi-material systems. Even though several normalization schemes have been developed in the literature, much confusion has existed on the fundamental principle of moisture diffusion. This paper derived an activity-based diffusion model using the concepts of chemical potential and water activity. We showed that the continuity of water activity at interface in dissimilar materials is warranted, and furthermore, many nonlinear water sorption isotherms can be applied in the activity-based model by using a new property called "generalized solubility". The activity-based model thus is capable to study complex moisture diffusion in multi-material system. Moreover, in this paper, the activity-based model was used to unify the different normalization theories, such as solubility-based and the so-called wetness normalization approaches. We also discussed how water sorption isotherm would affect the conventional moisture diffusivity, finding that only for some limiting cases (e.g., Henry sorption isotherm), the "effective moisture diffusivity" becomes independent of moisture concentration. We pointed out that the generalized solubility that are needed to solve the diffusion can be obtained using conventional terms such as saturated moisture concentration and solubility. As demonstration, a numerical example was performed in commercial finite element software to study the moisture diffusion through a bi-material interface under dynamic temperature and humidity conditions. The results from different nonlinear sorption isotherms were compared to demonstrate the capability and versatility of the model. We concluded that the activity-based moisture diffusion model is a unified and versatile approach to study and understand the moisture diffusion mechanism in IC packages.
{"title":"A Unified and Versatile Model Study for Moisture Diffusion","authors":"Liangbiao Chen, Jenny Zhou, H. Chu, Xuejun Fan","doi":"10.1109/ECTC.2017.239","DOIUrl":"https://doi.org/10.1109/ECTC.2017.239","url":null,"abstract":"All electronic packages involve with a multi-material system, in which many of the materials or films are susceptible to moisture absorption. Despite dissimilar material properties, moisture transports in a multi-material system from a high \"water activity\" region to a low one, where water activity is a measure of water energy in a specific substance. This, however, has not been well recognized in electronic packaging industry. Furthermore, moisture concentration gradient is often deemed as the driving force for moisture transport, which inevitably poses a challenging discontinuity issue at interface for moisture diffusion in multi-material systems. Even though several normalization schemes have been developed in the literature, much confusion has existed on the fundamental principle of moisture diffusion. This paper derived an activity-based diffusion model using the concepts of chemical potential and water activity. We showed that the continuity of water activity at interface in dissimilar materials is warranted, and furthermore, many nonlinear water sorption isotherms can be applied in the activity-based model by using a new property called \"generalized solubility\". The activity-based model thus is capable to study complex moisture diffusion in multi-material system. Moreover, in this paper, the activity-based model was used to unify the different normalization theories, such as solubility-based and the so-called wetness normalization approaches. We also discussed how water sorption isotherm would affect the conventional moisture diffusivity, finding that only for some limiting cases (e.g., Henry sorption isotherm), the \"effective moisture diffusivity\" becomes independent of moisture concentration. We pointed out that the generalized solubility that are needed to solve the diffusion can be obtained using conventional terms such as saturated moisture concentration and solubility. As demonstration, a numerical example was performed in commercial finite element software to study the moisture diffusion through a bi-material interface under dynamic temperature and humidity conditions. The results from different nonlinear sorption isotherms were compared to demonstrate the capability and versatility of the model. We concluded that the activity-based moisture diffusion model is a unified and versatile approach to study and understand the moisture diffusion mechanism in IC packages.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"13 1","pages":"1660-1667"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72860687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Pei, Sibasish Mukherjee, Nitin Uppal, M. Vujosevic
This study focuses on the understanding of moisture diffusion physics under use conditions (UC) and its impact on definition of qualification requirements. It uses computational modeling and detailed measurements of UC to challenge some long held assumptions used in moisture risk assessments. It introduces the quantity called "Stable Wetness" to account for moisture amount present in the package under UC, and couples it with Peck's empirical function to define the accelerated test duration (the qualification requirement). It concludes that due to the competing mechanisms of moisture and temperature there exist a "critical user", given in terms of ON-time per day that maximizes the requirements. It is this user that determines the qualification requirements, as opposed to, commonly assumed, the longest OFF-time user. The study also provides a simple equation for the computation of Stable Wetness, thus enabling an easy application of the proposed concepts in practical applications.
{"title":"Use Condition Risk Assessment for Moisture Related Failures","authors":"M. Pei, Sibasish Mukherjee, Nitin Uppal, M. Vujosevic","doi":"10.1109/ECTC.2017.162","DOIUrl":"https://doi.org/10.1109/ECTC.2017.162","url":null,"abstract":"This study focuses on the understanding of moisture diffusion physics under use conditions (UC) and its impact on definition of qualification requirements. It uses computational modeling and detailed measurements of UC to challenge some long held assumptions used in moisture risk assessments. It introduces the quantity called \"Stable Wetness\" to account for moisture amount present in the package under UC, and couples it with Peck's empirical function to define the accelerated test duration (the qualification requirement). It concludes that due to the competing mechanisms of moisture and temperature there exist a \"critical user\", given in terms of ON-time per day that maximizes the requirements. It is this user that determines the qualification requirements, as opposed to, commonly assumed, the longest OFF-time user. The study also provides a simple equation for the computation of Stable Wetness, thus enabling an easy application of the proposed concepts in practical applications.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"15 1","pages":"1187-1195"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74487652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The introduction of Chip Scale Package (CSP) has become one of the key packaging solutions in the recent semiconductor industry. With the advantages of reducing the package size and stacking capability for higher interconnects, CSP's are continuously evolving into many different types of CSP's packages. One of the key innovative package solutions is the molded wafer level CSP (M-WLCSP)1,2 due to the robust 5 sided or 6 sided protection of the devices with epoxy mold compound (EMC). The advantages of this application include, prevention of chipping and handling damage, sort screening capability due to its form factor at the wafer level, and the enhancement in board level reliability.3 The current singulation method that is the mechanical blade dicing process is encountering many challenges including yield loss, blade lifetime, productivity and its' limitation to achieve a narrow kerf width). In this paper we will share the results of the various studies done to develop a full cut laser dicing process for M-WLCSP and the impact of various parameters on the process flow, quality, productivity and cost. Together with an end customer reliability testing has been done on laser diced M-WLCSP packages of which the results will demonstrate that all criteria are met.
{"title":"Laser Multi Beam Full Cut Dicing of Wafer Level Chip-Scale Packages","authors":"J. V. Borkulo, Eric Tan, R. D. Stam","doi":"10.1109/ECTC.2017.76","DOIUrl":"https://doi.org/10.1109/ECTC.2017.76","url":null,"abstract":"The introduction of Chip Scale Package (CSP) has become one of the key packaging solutions in the recent semiconductor industry. With the advantages of reducing the package size and stacking capability for higher interconnects, CSP's are continuously evolving into many different types of CSP's packages. One of the key innovative package solutions is the molded wafer level CSP (M-WLCSP)1,2 due to the robust 5 sided or 6 sided protection of the devices with epoxy mold compound (EMC). The advantages of this application include, prevention of chipping and handling damage, sort screening capability due to its form factor at the wafer level, and the enhancement in board level reliability.3 The current singulation method that is the mechanical blade dicing process is encountering many challenges including yield loss, blade lifetime, productivity and its' limitation to achieve a narrow kerf width). In this paper we will share the results of the various studies done to develop a full cut laser dicing process for M-WLCSP and the impact of various parameters on the process flow, quality, productivity and cost. Together with an end customer reliability testing has been done on laser diced M-WLCSP packages of which the results will demonstrate that all criteria are met.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"8 1","pages":"337-342"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74439290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ying-Chih Lee, W. Lai, Ian Hu, M. Shih, C. Kao, D. Tarng, C. Hung
Fan-Out (FO) chip on substrate is one of the fan-out solution for package integration. This solution brings the short interconnection between die to die for excellent electrical performance. Fan-Out chip on substrate device provides excellent electrical performance in multi-die connection,. The multiple re-distribution layer (RDL) processing is implemented in advance multi-dies FO chip on substrate device for die to die connection meeting higher density electronic connection need. And for complex function request, the area of side-by-side silicon dies size are very close to FO multi-dies chip size, there is narrow die gap between these side-by-side dies. A large coefficient of thermal expansion (CTE) mismatch between epoxy molding compound (EMC) and silicon dies is a significant contributor to the origin of warpage, and will lead to high thermal-mechanical strain and stress at narrow area of side-by-side die gap. The redistribution layer could be high stress risk site by the high thermal-mechanical stress on narrow side-by-side dies gap area. This study is to build a fan-out chip on substrate package numerical simulation model by finite element method (FEM) and get good warpage and thermal-mechanical strain correlation between simulation and real package measurement result by advance Metrology Analyzer (aMA) system. Then we used this equivalent numerical model to compare the thermal-mechanical performance for different redistribution layer pattern design. Finally, generalizing the redistribution layer pattern design guideline and to enhance the package level reliability performance, especially under temperature cycling test (TCT) condition, of fan-out chip on substrate package. The new redistribution layer pattern layout can pass 1000 temperature cycling test cycles and there is lower stress risk on redistribution layer.
{"title":"Fan-Out Chip on Substrate Device Interconnection Reliability Analysis","authors":"Ying-Chih Lee, W. Lai, Ian Hu, M. Shih, C. Kao, D. Tarng, C. Hung","doi":"10.1109/ECTC.2017.104","DOIUrl":"https://doi.org/10.1109/ECTC.2017.104","url":null,"abstract":"Fan-Out (FO) chip on substrate is one of the fan-out solution for package integration. This solution brings the short interconnection between die to die for excellent electrical performance. Fan-Out chip on substrate device provides excellent electrical performance in multi-die connection,. The multiple re-distribution layer (RDL) processing is implemented in advance multi-dies FO chip on substrate device for die to die connection meeting higher density electronic connection need. And for complex function request, the area of side-by-side silicon dies size are very close to FO multi-dies chip size, there is narrow die gap between these side-by-side dies. A large coefficient of thermal expansion (CTE) mismatch between epoxy molding compound (EMC) and silicon dies is a significant contributor to the origin of warpage, and will lead to high thermal-mechanical strain and stress at narrow area of side-by-side die gap. The redistribution layer could be high stress risk site by the high thermal-mechanical stress on narrow side-by-side dies gap area. This study is to build a fan-out chip on substrate package numerical simulation model by finite element method (FEM) and get good warpage and thermal-mechanical strain correlation between simulation and real package measurement result by advance Metrology Analyzer (aMA) system. Then we used this equivalent numerical model to compare the thermal-mechanical performance for different redistribution layer pattern design. Finally, generalizing the redistribution layer pattern design guideline and to enhance the package level reliability performance, especially under temperature cycling test (TCT) condition, of fan-out chip on substrate package. The new redistribution layer pattern layout can pass 1000 temperature cycling test cycles and there is lower stress risk on redistribution layer.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"20 1","pages":"22-27"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85000721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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