Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338411
Xue Wu, K. Sengupta
In this paper, a scalable architecture is presented which can generate and radiate reconfigurable periodic waveforms in free-space with picosecond time-widths. This is achieved by allowing radiated electromagnetic-fields of fundamental and multiple harmonic frequencies to combine in free-space with the right amplitudes and delays, and quasi-optically construct the time-domain waveform in the desired direction. In this paper, a 4-element array with integrated antennas is presented which is demonstrated to radiate pulse trains of 2.6 ps time-widths as well as pure tones and harmonic frequencies at 107.5 GHz (EIRP=4.5 dBm), 215 GHz (EIRP=5.0 dBm) and any combination of amplitudes and delays of these two harmonics to generate a set of reconfigurable waveforms in free space. No silicon lens or substrate thinning was employed. To the best of the authors' knowledge, this is the sharpest radiated pulses demonstrated in any IC technology. The chip is fabricated in 65nm LP CMOS process.
{"title":"Dynamic waveform shaping for reconfigurable radiated periodic signal generation with picosecond time-widths","authors":"Xue Wu, K. Sengupta","doi":"10.1109/CICC.2015.7338411","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338411","url":null,"abstract":"In this paper, a scalable architecture is presented which can generate and radiate reconfigurable periodic waveforms in free-space with picosecond time-widths. This is achieved by allowing radiated electromagnetic-fields of fundamental and multiple harmonic frequencies to combine in free-space with the right amplitudes and delays, and quasi-optically construct the time-domain waveform in the desired direction. In this paper, a 4-element array with integrated antennas is presented which is demonstrated to radiate pulse trains of 2.6 ps time-widths as well as pure tones and harmonic frequencies at 107.5 GHz (EIRP=4.5 dBm), 215 GHz (EIRP=5.0 dBm) and any combination of amplitudes and delays of these two harmonics to generate a set of reconfigurable waveforms in free space. No silicon lens or substrate thinning was employed. To the best of the authors' knowledge, this is the sharpest radiated pulses demonstrated in any IC technology. The chip is fabricated in 65nm LP CMOS process.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"6 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89987110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338456
Jintao Zhang, Liechao Huang, Zhuo Wang, N. Verma
This paper presents a seizure-detection system wherein the accuracy required of the analog frontend is substantially relaxed. Typically, readout of electroencephalogram (EEG) signals would dominate the energy of such a system, due to the precision (noise, linearity) requirements. The presented system performs data conversion and analog multiplication for EEG feature extraction via simple circuits to demonstrate that feature errors can be overcome by appropriate retraining of a classification model, using a machine-learning algorithm. This precludes the need to design a high-precision frontend. The prototype, in 32nm CMOS, results in features whose RMS error normalized to their ideal values is 1.16 (i.e. errors are larger than ideal values). An ideal implementation of the seizure detector exhibits sensitivity, latency, false alarms of 5/5, 2.0 sec., 8, respectively. The feature errors degrade this to 5/5, 3.6 sec., 443, causing high false alarms; but retraining of the classification model restores this to 5/5, 3.4 sec., 4.
{"title":"A seizure-detection IC employing machine learning to overcome data-conversion and analog-processing non-idealities","authors":"Jintao Zhang, Liechao Huang, Zhuo Wang, N. Verma","doi":"10.1109/CICC.2015.7338456","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338456","url":null,"abstract":"This paper presents a seizure-detection system wherein the accuracy required of the analog frontend is substantially relaxed. Typically, readout of electroencephalogram (EEG) signals would dominate the energy of such a system, due to the precision (noise, linearity) requirements. The presented system performs data conversion and analog multiplication for EEG feature extraction via simple circuits to demonstrate that feature errors can be overcome by appropriate retraining of a classification model, using a machine-learning algorithm. This precludes the need to design a high-precision frontend. The prototype, in 32nm CMOS, results in features whose RMS error normalized to their ideal values is 1.16 (i.e. errors are larger than ideal values). An ideal implementation of the seizure detector exhibits sensitivity, latency, false alarms of 5/5, 2.0 sec., 8, respectively. The feature errors degrade this to 5/5, 3.6 sec., 443, causing high false alarms; but retraining of the classification model restores this to 5/5, 3.4 sec., 4.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"77 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78775132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338484
Dongseok Shin, S. Raman, Kwang-Jin Koh
This paper presents a six-phase VCO using a superharmonic coupling technique. Three VCOs are coupled by an inductive network in their tail nodes to generate six-phase outputs. This network also serves as a tail noise filter in each VCO. Therefore, the proposed six-phase VCO can achieve better phase noise performance than typical multiphase topologies. The proposed VCO is implemented in 32nm SOI CMOS process with core area of 0.6×0.5mm2. The VCO can be tuned from 29.24 GHz to 31.56 GHz, a frequency tuning range of 7.6% at 0.6V supply. With each VCO consuming 1.52 mW DC power (4.56 mW total), the measured phase noise is -128 dBc/Hz at 10 MHz offset when VCO output frequency is 31.43 GHz, resulting in -191 dBc/Hz of FOM.
{"title":"A 0.6-V, 30-GHz six-phase VCO with superharmonic coupling in 32-nm SOI CMOS technology","authors":"Dongseok Shin, S. Raman, Kwang-Jin Koh","doi":"10.1109/CICC.2015.7338484","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338484","url":null,"abstract":"This paper presents a six-phase VCO using a superharmonic coupling technique. Three VCOs are coupled by an inductive network in their tail nodes to generate six-phase outputs. This network also serves as a tail noise filter in each VCO. Therefore, the proposed six-phase VCO can achieve better phase noise performance than typical multiphase topologies. The proposed VCO is implemented in 32nm SOI CMOS process with core area of 0.6×0.5mm2. The VCO can be tuned from 29.24 GHz to 31.56 GHz, a frequency tuning range of 7.6% at 0.6V supply. With each VCO consuming 1.52 mW DC power (4.56 mW total), the measured phase noise is -128 dBc/Hz at 10 MHz offset when VCO output frequency is 31.43 GHz, resulting in -191 dBc/Hz of FOM.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89142866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338372
Joon-Yeong Lee, Kwangseok Han, Taeho Kim, Sangeun Lee, Jeong-Sup Lee, Taehun Yoon, Jinho Park, Hyeon-Min Bae
A phase interpolator (PI)-based 10 × 10 Gb/s bootstrap transceiver for reference-less and lane-independent operation is presented. PI output clock signals that are phase locked to the input data are used for the voltage-controlled oscillator (VCO) frequency locking. The VCO clock signal is then redistributed to the PIs, which triggers bootstrapping between the VCO and PIs. Entire lanes operate independently as in VCO-based parallel reference-less designs, but without performance penalties and with power and area savings. The measured recovered-data jitter in each lane is 0.93 psrms and the transceiver passes the OC-192 jitter-tolerance specification. A flip-chip packaged test chip is fabricated in a 40 nm CMOS technology, having receiver and transmitter figure-of-merits (mW/Gb/s) of 2.03 and 2.13, respectively.
{"title":"A power-and-area efficient 10 × 10 Gb/s bootstrap transceiver in 40 nm CMOS for reference-less and lane-independent operation","authors":"Joon-Yeong Lee, Kwangseok Han, Taeho Kim, Sangeun Lee, Jeong-Sup Lee, Taehun Yoon, Jinho Park, Hyeon-Min Bae","doi":"10.1109/CICC.2015.7338372","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338372","url":null,"abstract":"A phase interpolator (PI)-based 10 × 10 Gb/s bootstrap transceiver for reference-less and lane-independent operation is presented. PI output clock signals that are phase locked to the input data are used for the voltage-controlled oscillator (VCO) frequency locking. The VCO clock signal is then redistributed to the PIs, which triggers bootstrapping between the VCO and PIs. Entire lanes operate independently as in VCO-based parallel reference-less designs, but without performance penalties and with power and area savings. The measured recovered-data jitter in each lane is 0.93 psrms and the transceiver passes the OC-192 jitter-tolerance specification. A flip-chip packaged test chip is fabricated in a 40 nm CMOS technology, having receiver and transmitter figure-of-merits (mW/Gb/s) of 2.03 and 2.13, respectively.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"55 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74900606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338396
Shanshan Dai, J. Rosenstein
This paper presents a novel ultra-low-power dual-phase current-mode relaxation oscillator, which produces a 122 kHz digital clock and has total power consumption of 14.4 nW at 0.6 V. Its frequency dependence is 327 ppm/°C over a temperature range of -20° C to 100° C, and its supply voltage coefficient is ±3.0%/V from 0.6 V to 1.8 V. The proposed oscillator is fabricated in 0.18 μm CMOS technology and occupies 0.03 mm2. At room temperature it achieves a figure of merit of 120 pW/kHz, making it one of the most efficient relaxation oscillators reported to date.
{"title":"A 14.4nW 122KHz dual-phase current-mode relaxation oscillator for near-zero-power sensors","authors":"Shanshan Dai, J. Rosenstein","doi":"10.1109/CICC.2015.7338396","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338396","url":null,"abstract":"This paper presents a novel ultra-low-power dual-phase current-mode relaxation oscillator, which produces a 122 kHz digital clock and has total power consumption of 14.4 nW at 0.6 V. Its frequency dependence is 327 ppm/°C over a temperature range of -20° C to 100° C, and its supply voltage coefficient is ±3.0%/V from 0.6 V to 1.8 V. The proposed oscillator is fabricated in 0.18 μm CMOS technology and occupies 0.03 mm2. At room temperature it achieves a figure of merit of 120 pW/kHz, making it one of the most efficient relaxation oscillators reported to date.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"10 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75540501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338363
Junlei Zhao, M. Bassi, A. Mazzanti, F. Svelto
Generation of broadband power at mm-wave frequencies with high efficiency is challenging, because of the low gain of CMOS devices and the trade-off between efficiency and gain-bandwidth product (GBW). Power amplifiers (PAs) with multiple paths, leveraging power splitters and combiners are the most popular choice to achieve high output power, but tradeoff between efficiency and GBW still exists. In fact, most of the high-efficiency PAs have a relatively narrow bandwidth, not adequate for applications such as IEEE820.15 or Wigig. Since PAs' bandwidth is limited by the large parasitic capacitors at the input and output of the gain stages, design techniques for power splitters, combiners and interstage networks play a key role in achieving wide bandwidth without sacrificing gain and efficiency. In this work, coupled resonators networks are exploited to achieve more than 2x enhancement of GBW. A design technique to embed the classical coupled resonators networks into power splitters and combiners is presented for the first time. By applying this technique to a 3-stages 2-way power combining PA, measured prototypes show broadband operation from 58.5 to 73.5 GHz with 30dB gain, 20dBm output power and a remarkable 22% PAE.
{"title":"A 15 GHz-bandwidth 20dBm PSAT power amplifier with 22% PAE in 65nm CMOS","authors":"Junlei Zhao, M. Bassi, A. Mazzanti, F. Svelto","doi":"10.1109/CICC.2015.7338363","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338363","url":null,"abstract":"Generation of broadband power at mm-wave frequencies with high efficiency is challenging, because of the low gain of CMOS devices and the trade-off between efficiency and gain-bandwidth product (GBW). Power amplifiers (PAs) with multiple paths, leveraging power splitters and combiners are the most popular choice to achieve high output power, but tradeoff between efficiency and GBW still exists. In fact, most of the high-efficiency PAs have a relatively narrow bandwidth, not adequate for applications such as IEEE820.15 or Wigig. Since PAs' bandwidth is limited by the large parasitic capacitors at the input and output of the gain stages, design techniques for power splitters, combiners and interstage networks play a key role in achieving wide bandwidth without sacrificing gain and efficiency. In this work, coupled resonators networks are exploited to achieve more than 2x enhancement of GBW. A design technique to embed the classical coupled resonators networks into power splitters and combiners is presented for the first time. By applying this technique to a 3-stages 2-way power combining PA, measured prototypes show broadband operation from 58.5 to 73.5 GHz with 30dB gain, 20dBm output power and a remarkable 22% PAE.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"12 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86285001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338395
Hui Wang, P. Mercier
This paper presents a gate-leakage-based Hz-range oscillator that achieves ultra-low-power frequency-stable operation in a small area via a capacitive-discharging architecture. By pre-charging two capacitors to VDD, and then allowing one to discharge through a temperature stable discharging path, an accurate clock period is generated independent of VDD and without a power-expensive reference. By exploiting the opposite temperature dependencies of different gate-leakage transistors, a stable oscillation frequency is achieved. Implemented in a 65 nm CMOS process, the proposed oscillator consumes 51 pW at 2.8 Hz. Across a temperature range of -40 °C to 60 °C, the oscillator deviates down to ±0.05% /°C, enabling an accurate, low-cost, low-power timing solution at Hz-range frequency.
{"title":"A 51 pW reference-free capacitive-discharging oscillator architecture operating at 2.8 Hz","authors":"Hui Wang, P. Mercier","doi":"10.1109/CICC.2015.7338395","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338395","url":null,"abstract":"This paper presents a gate-leakage-based Hz-range oscillator that achieves ultra-low-power frequency-stable operation in a small area via a capacitive-discharging architecture. By pre-charging two capacitors to VDD, and then allowing one to discharge through a temperature stable discharging path, an accurate clock period is generated independent of VDD and without a power-expensive reference. By exploiting the opposite temperature dependencies of different gate-leakage transistors, a stable oscillation frequency is achieved. Implemented in a 65 nm CMOS process, the proposed oscillator consumes 51 pW at 2.8 Hz. Across a temperature range of -40 °C to 60 °C, the oscillator deviates down to ±0.05% /°C, enabling an accurate, low-cost, low-power timing solution at Hz-range frequency.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"40 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86386146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338449
A. Banerjee, R. Hezar, Lei Ding
Integration of RF power amplifier (PA) in CMOS technology can help to reduce total solution cost and achieve small form factor in modern communication systems. To improve overall efficiency of the power amplifier supporting modulated signals with very high peak-to-average power ratio (PAPR), new transmitter and PA architectures are being explored by researchers. This paper reviews some of our recent developments in CMOS based PA architectures including PWM based digital transmitter and outphasing power amplifier and presents a new multi-mode outphasing PA designed in 45 nm CMOS.
{"title":"Efficiency improvement techniques for RF power amplifiers in deep submicron CMOS","authors":"A. Banerjee, R. Hezar, Lei Ding","doi":"10.1109/CICC.2015.7338449","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338449","url":null,"abstract":"Integration of RF power amplifier (PA) in CMOS technology can help to reduce total solution cost and achieve small form factor in modern communication systems. To improve overall efficiency of the power amplifier supporting modulated signals with very high peak-to-average power ratio (PAPR), new transmitter and PA architectures are being explored by researchers. This paper reviews some of our recent developments in CMOS based PA architectures including PWM based digital transmitter and outphasing power amplifier and presents a new multi-mode outphasing PA designed in 45 nm CMOS.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"7 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77836175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338377
P. Raghavan, M. Bardon, D. Jang, P. Schuddinck, D. Yakimets, J. Ryckaert, A. Mercha, N. Horiguchi, N. Collaert, A. Mocuta, D. Mocuta, Z. Tokei, D. Verkest, A. Thean, A. Steegen
In this paper, we review the conditions at which FinFETs could meet system requirements at the 7nm node. We explore the key enablers to meet the power performance targets for 7nm node. We show that the device parasitics is the biggest performance detractor as we scale down. We illustrate the device design space that allows to meet speed and power targets, then explore the optimization of the geometry in combination with disruptive solutions such as air gap spacers and wrapped contacts, the benefits and drawbacks of increased fin height, and the design level solutions such as fin depopulation.
{"title":"Holisitic device exploration for 7nm node","authors":"P. Raghavan, M. Bardon, D. Jang, P. Schuddinck, D. Yakimets, J. Ryckaert, A. Mercha, N. Horiguchi, N. Collaert, A. Mocuta, D. Mocuta, Z. Tokei, D. Verkest, A. Thean, A. Steegen","doi":"10.1109/CICC.2015.7338377","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338377","url":null,"abstract":"In this paper, we review the conditions at which FinFETs could meet system requirements at the 7nm node. We explore the key enablers to meet the power performance targets for 7nm node. We show that the device parasitics is the biggest performance detractor as we scale down. We illustrate the device design space that allows to meet speed and power targets, then explore the optimization of the geometry in combination with disruptive solutions such as air gap spacers and wrapped contacts, the benefits and drawbacks of increased fin height, and the design level solutions such as fin depopulation.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"12 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78088386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338394
P. Kinget
Analog circuits provide the critical interfaces between the digital world inside today's integrated circuits and the physical world. Semiconductor technology scaling driven by `Moore's Law' has resulted in a phenomenal scaling of the performance of digital processors and memory. Continuing design innovations have enabled the scaling of analog interfaces onto scaled CMOS technologies, even though device scaling is a mixed blessing for the analog designer. This paper reviews the scaling challenges for analog circuits ranging from fundamental to practical challenges. Design strategies are outlined that in principle can overcome the challenges and can help guide the search for new circuit paradigms. Several examples of innovative analog design paradigms are reviewed and the opportunities in highly scaled CMOS technologies are outlined.
{"title":"Scaling analog circuits into deep nanoscale CMOS: Obstacles and ways to overcome them","authors":"P. Kinget","doi":"10.1109/CICC.2015.7338394","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338394","url":null,"abstract":"Analog circuits provide the critical interfaces between the digital world inside today's integrated circuits and the physical world. Semiconductor technology scaling driven by `Moore's Law' has resulted in a phenomenal scaling of the performance of digital processors and memory. Continuing design innovations have enabled the scaling of analog interfaces onto scaled CMOS technologies, even though device scaling is a mixed blessing for the analog designer. This paper reviews the scaling challenges for analog circuits ranging from fundamental to practical challenges. Design strategies are outlined that in principle can overcome the challenges and can help guide the search for new circuit paradigms. Several examples of innovative analog design paradigms are reviewed and the opportunities in highly scaled CMOS technologies are outlined.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"204 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80303271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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