Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245235
N. Tu, S. R. Ricky Lee
This paper describes a method to inkjet print Poly (ethylenedioxythiophene): polystyrene sulphonate (PEODT: PSS) without coffee ring effect. PEDOT: PSS is a unique long-chain polymer with conductivity and transparency properties that are mainly used in the packaging process of quantum dot light emitting displays and solar cells. Due to the ability to increase the transparency and conductivity of PEDOT: PSS in recent years, flexibility becomes another advantage of PEDOT: PSS. Therefore, the flexible electronic device such as the flexible quantum dot light emitting diode display, and the flexible solar cell is another exciting application of PEDOT: PSS. In order to save materials and reduce the manufacturing cost, inkjet printing is applied to fabricate the PEDOT: PSS thin film. The uniformity of PEDOT: PSS thin film is the crucial point for the flexible quantum dot light emitting diode display by inkjet printing. While the critical factor to have a uniform and flat PEDOT: PSS thin film is to reduce the coffee ring effect. The coffee ring effect caused by the fast evaporation rate at the edge of the droplet, which results in a higher degree of diffusion freedom at the edge of the droplet; then the capillary forms from the center to the edge, to supply the solvent for evaporation loss. However, the supplied solvent also brings solute to the edge and the solute despite to the edge, which causes the ring shape at the edge of the droplet. In this paper, the coffee ring effect was reduced significantly by adding co-solvent with high boiling point and high viscosity to the primary solvent. The high boiling point of the co-solvent reduces the driving force of the capillary flow, while the high viscosity of the co-solvent increase resistance of the capillary flow as well. What’s more, the surface tension properties of the substrate was modified to increase the wettability of PEDOT: PSS. Thus, PEDOT: PSS thin film with improved uniformity can be obtained due to the reduction of coffee ring effect, which can apply for the packaging process of flexible quantum dot light emitting diode display.
{"title":"Inkjet Printing PEDOT:PSS without Coffee Ring Effect for QLED Applicaitons","authors":"N. Tu, S. R. Ricky Lee","doi":"10.1109/ICEPT47577.2019.245235","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245235","url":null,"abstract":"This paper describes a method to inkjet print Poly (ethylenedioxythiophene): polystyrene sulphonate (PEODT: PSS) without coffee ring effect. PEDOT: PSS is a unique long-chain polymer with conductivity and transparency properties that are mainly used in the packaging process of quantum dot light emitting displays and solar cells. Due to the ability to increase the transparency and conductivity of PEDOT: PSS in recent years, flexibility becomes another advantage of PEDOT: PSS. Therefore, the flexible electronic device such as the flexible quantum dot light emitting diode display, and the flexible solar cell is another exciting application of PEDOT: PSS. In order to save materials and reduce the manufacturing cost, inkjet printing is applied to fabricate the PEDOT: PSS thin film. The uniformity of PEDOT: PSS thin film is the crucial point for the flexible quantum dot light emitting diode display by inkjet printing. While the critical factor to have a uniform and flat PEDOT: PSS thin film is to reduce the coffee ring effect. The coffee ring effect caused by the fast evaporation rate at the edge of the droplet, which results in a higher degree of diffusion freedom at the edge of the droplet; then the capillary forms from the center to the edge, to supply the solvent for evaporation loss. However, the supplied solvent also brings solute to the edge and the solute despite to the edge, which causes the ring shape at the edge of the droplet. In this paper, the coffee ring effect was reduced significantly by adding co-solvent with high boiling point and high viscosity to the primary solvent. The high boiling point of the co-solvent reduces the driving force of the capillary flow, while the high viscosity of the co-solvent increase resistance of the capillary flow as well. What’s more, the surface tension properties of the substrate was modified to increase the wettability of PEDOT: PSS. Thus, PEDOT: PSS thin film with improved uniformity can be obtained due to the reduction of coffee ring effect, which can apply for the packaging process of flexible quantum dot light emitting diode display.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"8 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89860580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245348
Wei Wu, Xianbing Li, Liang Wang, Zhongkang Lin
Insulated Gate Bipolar Transistor (IGBT) is one of the most advanced power electronic devices to realize power conversion and control, which has a strong current processing capability. It is applied more and more widely. In the service process, high current, high voltage and high switching frequency will cause IGBT module to produce greater power losses, resulting in module temperature rise. Temperature has a great influence on the reliability of IGBT. In this paper, the electrothermal finite element analysis of IGBT module under sinusoidal current load is carried out by means of finite element numerical simulation. The temperature distribution and current density distribution of IGBT module are obtained. In order to compare the difference of temperature distribution between sinusoidal current load and direct current load, the electro-thermal analysis under direct current load is also carried out. The results show that the main heat producing area of IGBT module is IGBT chip. In the process of electrical-thermal analysis, the Joule heat generated by IGBT chips conducts downward and eventually dissipates from the base plate to the outside. The current density distribution on the surface of IGBT chips is uneven. The current density near the Al bonding wires is larger, while the current density at the center and edge of the chips is smaller. By comparing the results of electro-thermal analysis under sinusoidal current load and direct current load, it is found that the temperature rise rate, the temperature fluctuation range, the time to reach the maximum temperature and the current density change are quite different under different current waveforms.
{"title":"Electro-thermal finite element analysis of IGBT module under sinusoidal current load","authors":"Wei Wu, Xianbing Li, Liang Wang, Zhongkang Lin","doi":"10.1109/ICEPT47577.2019.245348","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245348","url":null,"abstract":"Insulated Gate Bipolar Transistor (IGBT) is one of the most advanced power electronic devices to realize power conversion and control, which has a strong current processing capability. It is applied more and more widely. In the service process, high current, high voltage and high switching frequency will cause IGBT module to produce greater power losses, resulting in module temperature rise. Temperature has a great influence on the reliability of IGBT. In this paper, the electrothermal finite element analysis of IGBT module under sinusoidal current load is carried out by means of finite element numerical simulation. The temperature distribution and current density distribution of IGBT module are obtained. In order to compare the difference of temperature distribution between sinusoidal current load and direct current load, the electro-thermal analysis under direct current load is also carried out. The results show that the main heat producing area of IGBT module is IGBT chip. In the process of electrical-thermal analysis, the Joule heat generated by IGBT chips conducts downward and eventually dissipates from the base plate to the outside. The current density distribution on the surface of IGBT chips is uneven. The current density near the Al bonding wires is larger, while the current density at the center and edge of the chips is smaller. By comparing the results of electro-thermal analysis under sinusoidal current load and direct current load, it is found that the temperature rise rate, the temperature fluctuation range, the time to reach the maximum temperature and the current density change are quite different under different current waveforms.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"1 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81276914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245299
Min Wang, Shengyu Hu, Songyang Su, Xuanyu Wang, Jiaxing Liu, Cheng Yang
Flexible supercapacitors are considered as a promising candidate for power supplementation in wearable electronics due to their high power density. However, effectively fabricate flexible and low-cost supercapacitor electrodes in a big scale is still a key challenge. Herein we demonstrate a scalable fabrication method for hierarchical electrodes via metalizing air-laid paper and loading with MnO2 as cathode active materials. To be specific, we coat a thin layer of Ni on air-laid paper by magnetron sputtering, then deposit Ni nanocone arrays (NNAs) on the Ni sputtered paper and finally deposit MnO2 on the NNAs to obtain the NNAs@MnO2 paper electrode. The as-prepared paper-based electrode possesses high conductivity and fine wettability, which facilitates the electrons and ions transporting through the conductive network. Additionally, this electrode provides large specific surface area with a hierarchical architecture. Thus the electrode shows high capacitance (451 F/g) and favorable cycle performance (92.9% capacity retention after cycling for 5000 times). By coupling with activated carbon (AC) coated on the NNAs conductive paper as anode, an NNAs paper-based asymmetric supercapacitor is constructed. Benefiting from the high mechanical durability and the 3D hierarchical architecture of the electrodes, the asymmetric supercapacitor exhibits excellent mechanical flexibility and high energy density (26.9 μWh/cm2 at 1.08 mW/cm2). This method can be easily scaled up to produce lightweight and low-cost conductive paper electrodes, making it promising for the application of flexible supercapacitors in wearable electronics.
{"title":"MnO2@Nickel Nanocone Arrays Coated Paper Electrode for Flexible Supercapacitors","authors":"Min Wang, Shengyu Hu, Songyang Su, Xuanyu Wang, Jiaxing Liu, Cheng Yang","doi":"10.1109/ICEPT47577.2019.245299","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245299","url":null,"abstract":"Flexible supercapacitors are considered as a promising candidate for power supplementation in wearable electronics due to their high power density. However, effectively fabricate flexible and low-cost supercapacitor electrodes in a big scale is still a key challenge. Herein we demonstrate a scalable fabrication method for hierarchical electrodes via metalizing air-laid paper and loading with MnO2 as cathode active materials. To be specific, we coat a thin layer of Ni on air-laid paper by magnetron sputtering, then deposit Ni nanocone arrays (NNAs) on the Ni sputtered paper and finally deposit MnO2 on the NNAs to obtain the NNAs@MnO2 paper electrode. The as-prepared paper-based electrode possesses high conductivity and fine wettability, which facilitates the electrons and ions transporting through the conductive network. Additionally, this electrode provides large specific surface area with a hierarchical architecture. Thus the electrode shows high capacitance (451 F/g) and favorable cycle performance (92.9% capacity retention after cycling for 5000 times). By coupling with activated carbon (AC) coated on the NNAs conductive paper as anode, an NNAs paper-based asymmetric supercapacitor is constructed. Benefiting from the high mechanical durability and the 3D hierarchical architecture of the electrodes, the asymmetric supercapacitor exhibits excellent mechanical flexibility and high energy density (26.9 μWh/cm2 at 1.08 mW/cm2). This method can be easily scaled up to produce lightweight and low-cost conductive paper electrodes, making it promising for the application of flexible supercapacitors in wearable electronics.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"901 ","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91546520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The interconnecting joint of space cables get smaller and smaller, when the installation space of assembly is smaller, which is easy lead to wire stress and wire breakage. The purpose of encapsulating of the connector is to protect the cable interconnecting, including crimping and soldering joints, and to reduce the weight of the cables at the same time. In this study, the connectors were injection molded, potted without back shells, and potted with back shells in extravehicular cables. The space accelerated tests including mechanical vibration, mechanical impact, bending, and temperature cycle tests were performed on encapsulated cables. The study on tensile strength, metallography, and Scanning electron microscopy (SEM.) of the interconnecting joints showed that, the electrical performance was good with all three kinds of encapsulating process. Crack and delamination defects were not found in the interface of soldering or crimping joint. The three encapsulating method can effectively protect the interconnecting joint of space cable.
{"title":"Reliability study on the encapsulated space cable assembly under accelerated tests","authors":"Yarong Chen, Zhenming Zhang, Minghua Zhang, Meng Yang, Zhanjun Xia, Cuiping Yuan","doi":"10.1109/ICEPT47577.2019.245341","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245341","url":null,"abstract":"The interconnecting joint of space cables get smaller and smaller, when the installation space of assembly is smaller, which is easy lead to wire stress and wire breakage. The purpose of encapsulating of the connector is to protect the cable interconnecting, including crimping and soldering joints, and to reduce the weight of the cables at the same time. In this study, the connectors were injection molded, potted without back shells, and potted with back shells in extravehicular cables. The space accelerated tests including mechanical vibration, mechanical impact, bending, and temperature cycle tests were performed on encapsulated cables. The study on tensile strength, metallography, and Scanning electron microscopy (SEM.) of the interconnecting joints showed that, the electrical performance was good with all three kinds of encapsulating process. Crack and delamination defects were not found in the interface of soldering or crimping joint. The three encapsulating method can effectively protect the interconnecting joint of space cable.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"35 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90920376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245776
Jing Chen, Lei Ding, Weipeng Ren, Tao Chen, Lichun Wang, Tao Zhao
Considering the requirements of Microsystems miniaturization integration for high-performance film-forming substrates, the key technologies of multilayer BCB/Cu thin film interconnection based on LTCC substrates and the related process controls were studied. A high reliability "T" interface interconnection method for thin film magnetron sputtering Cr/Cu/Cr and Cr/Pd/Au composite membrane structure and its preparation method were proposed. The effects of the interface defect and roughness of LTCC-thin film, the control of residual photoresist quantity in BCB film through holes and the stress of metallization of dielectric membrane on the quality of thick thin film composite substrate were studied. The prepared 12-layer thick thin film mixed substrate(10 layers LTCC substrate, 2 layers of thin film wiring) 60 pieces, all passed the GJB2438 C. 2.7 film substrate evaluation standard. Compared to the LTCC substrate, the wiring density is increased by 4 times, size reduced by 40 %.
{"title":"Research on BCB/Cu thin film multilayer interconnection technology based on LTCC substrate for Microsystem Integration","authors":"Jing Chen, Lei Ding, Weipeng Ren, Tao Chen, Lichun Wang, Tao Zhao","doi":"10.1109/ICEPT47577.2019.245776","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245776","url":null,"abstract":"Considering the requirements of Microsystems miniaturization integration for high-performance film-forming substrates, the key technologies of multilayer BCB/Cu thin film interconnection based on LTCC substrates and the related process controls were studied. A high reliability \"T\" interface interconnection method for thin film magnetron sputtering Cr/Cu/Cr and Cr/Pd/Au composite membrane structure and its preparation method were proposed. The effects of the interface defect and roughness of LTCC-thin film, the control of residual photoresist quantity in BCB film through holes and the stress of metallization of dielectric membrane on the quality of thick thin film composite substrate were studied. The prepared 12-layer thick thin film mixed substrate(10 layers LTCC substrate, 2 layers of thin film wiring) 60 pieces, all passed the GJB2438 C. 2.7 film substrate evaluation standard. Compared to the LTCC substrate, the wiring density is increased by 4 times, size reduced by 40 %.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"57 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73360941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245730
Xinru Li, Huiyu Yu, Zhenyu Wang
Compared with other heat dissipation systems, flat plate heat pipe (FPHP) can be manufactured in a thin plate shape, which is useful for microelectronics cooling system. Considering the SiC substrate has the same high thermal conductivity and the matched thermal expansion as the SiC-based devices, a SiC micropillar wick thin flat plate heat pipe (FPHP) architecture is proposed here for heat dissipation of SiC power devices. To compensate the requirements of bonding strength and etching uniformity, the hexagon micropillar wick architecture was fabricated inside the FPHPs. Meanwhile, the identical Si-Glass FPHPs were fabricated for comparison. The accurate and comprehensive analysis and comparison of SiC-Glass FPHP and Si-Glass FPHP were conducted utilizing the infrared (IR), Raman and high-speed camera equipment. During experiments, the maximum boiling zone of liquid inside SiC-Glass FPHP was much larger than that of Si one due to the specific heat capacity difference. The SiC-Glass FPHP CHF was close to 120 W/cm2, with a maximum 11 mm diameter boiling range. The Si-Glass one was only 55 W/cm2, with a maximum 6 mm diameter nucleate boiling range. Apparently, the SiC-Glass FPHP had a higher thermal dissipation efficiency than Si one.
{"title":"A SiC Based Integrated Micropillar Array Wick Thin Plate Heat Pipe Investigation","authors":"Xinru Li, Huiyu Yu, Zhenyu Wang","doi":"10.1109/ICEPT47577.2019.245730","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245730","url":null,"abstract":"Compared with other heat dissipation systems, flat plate heat pipe (FPHP) can be manufactured in a thin plate shape, which is useful for microelectronics cooling system. Considering the SiC substrate has the same high thermal conductivity and the matched thermal expansion as the SiC-based devices, a SiC micropillar wick thin flat plate heat pipe (FPHP) architecture is proposed here for heat dissipation of SiC power devices. To compensate the requirements of bonding strength and etching uniformity, the hexagon micropillar wick architecture was fabricated inside the FPHPs. Meanwhile, the identical Si-Glass FPHPs were fabricated for comparison. The accurate and comprehensive analysis and comparison of SiC-Glass FPHP and Si-Glass FPHP were conducted utilizing the infrared (IR), Raman and high-speed camera equipment. During experiments, the maximum boiling zone of liquid inside SiC-Glass FPHP was much larger than that of Si one due to the specific heat capacity difference. The SiC-Glass FPHP CHF was close to 120 W/cm2, with a maximum 11 mm diameter boiling range. The Si-Glass one was only 55 W/cm2, with a maximum 6 mm diameter nucleate boiling range. Apparently, the SiC-Glass FPHP had a higher thermal dissipation efficiency than Si one.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"60 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76590129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The finite element analysis model of residual stress after reflow soldering of QFN lead-free solder joints is established in this paper, and the residual stress after reflow soldering was analyzed under thermal structural coupling conditions. With the solder joint height, lead pitch, chip thickness and PCB thickness as design factors, 9 solder joints model of QFN with different levels combination were designed and the maximum residual stress values of the 9 solder joints model of QFN were obtained by simulation analysis. And carried out the range analysis for structural parameters of the QFN solder joints model. The results show that the residual stress of QFN solder joints is unevenly distributed. The maximum residual stress appears in the contact point between the solder joints and the chip and farthest from the chip center. The order of the influence for residual stress after reflow soldering from large to small is solder joint height, chip thickness, PCB thickness and lead pitch. Provides theoretical guidance for controlling residual stress after reflow soldering of QFN.
{"title":"Analysis of residual stress after reflow soldering of QFN package","authors":"Sheng-jun Zhao, Chunyue Huang, Xiang-qiong Tang, Ying Liang","doi":"10.1109/ICEPT47577.2019.245833","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245833","url":null,"abstract":"The finite element analysis model of residual stress after reflow soldering of QFN lead-free solder joints is established in this paper, and the residual stress after reflow soldering was analyzed under thermal structural coupling conditions. With the solder joint height, lead pitch, chip thickness and PCB thickness as design factors, 9 solder joints model of QFN with different levels combination were designed and the maximum residual stress values of the 9 solder joints model of QFN were obtained by simulation analysis. And carried out the range analysis for structural parameters of the QFN solder joints model. The results show that the residual stress of QFN solder joints is unevenly distributed. The maximum residual stress appears in the contact point between the solder joints and the chip and farthest from the chip center. The order of the influence for residual stress after reflow soldering from large to small is solder joint height, chip thickness, PCB thickness and lead pitch. Provides theoretical guidance for controlling residual stress after reflow soldering of QFN.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"58 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80027498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245775
Zizhou Yang, Yang Peng, Hao-Chun Cheng, Chen Liu, Mingxiang Chen
In this work, three dimensional direct plated copper (3DPC) ceramic substrate prepared by repeated ultraviolet (UV) depth lithography and electroforming is proposed. The effects of different electroforming parameters including current density, stirring speed, and temperature were evaluated by internal stress and electroforming rate using a L9(34) orthogonal experiment. Range analysis and analysis of variance (ANOVA) were employed to estimate the contribution of each factor to the overall response. The optimal electrodeposition parameters were the current density of 4 ASD, the stirring speed of 1200 rpm, and the temperature of 50 °C. Furthermore, the microstructure, hermeticity, and thermal reliability of 3DPC substrate were researched. The results showed the 3DPC substrate had excellent hermeticity and the strong bonding strength between dam and flat DPC substrate even after 30 thermal cycles. The above results demonstrated that 3DPC substrate could be considered as a reliable substrate for UV-LED hermetic packaging.
{"title":"Three-dimensional ceramic substrate prepared by repeated lithography and electroforming","authors":"Zizhou Yang, Yang Peng, Hao-Chun Cheng, Chen Liu, Mingxiang Chen","doi":"10.1109/ICEPT47577.2019.245775","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245775","url":null,"abstract":"In this work, three dimensional direct plated copper (3DPC) ceramic substrate prepared by repeated ultraviolet (UV) depth lithography and electroforming is proposed. The effects of different electroforming parameters including current density, stirring speed, and temperature were evaluated by internal stress and electroforming rate using a L9(34) orthogonal experiment. Range analysis and analysis of variance (ANOVA) were employed to estimate the contribution of each factor to the overall response. The optimal electrodeposition parameters were the current density of 4 ASD, the stirring speed of 1200 rpm, and the temperature of 50 °C. Furthermore, the microstructure, hermeticity, and thermal reliability of 3DPC substrate were researched. The results showed the 3DPC substrate had excellent hermeticity and the strong bonding strength between dam and flat DPC substrate even after 30 thermal cycles. The above results demonstrated that 3DPC substrate could be considered as a reliable substrate for UV-LED hermetic packaging.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"52 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83129198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
2.5D glass interposer technology based on through glass via (TGV) becomes a hot research topic on account of good electrical property and CTE (coefficient of thermal expansion) mismatch [1]. In this paper, the Laser-Induced Deep Etching (LIDE) technology is used to manufacture TGVs on glass substrate. The LIDE process can be mainly divided into two steps: Initially, picosecond laser is used to modified the glass substrate. Then, using 10% HF etch the modified glass substrate. On account of denaturation of the laser irradiation area, the area where is exposed to the laser will be etched more quickly than unexposed area in the process of wet etching. In consideration of the properties of various glass, SCHOTT AF 32® eco glass and CORNING HPFS 7980 fused silica glass is selected as the substrate of this study. The result show that the LIDE process is a promising high-speed TGVs manufacturing process which can fabricate TGV of high verticality (the taper angle is approximately 9° on AF 32® eco glass and 1° on CORNING HPFS 7980 fused silica glass) at a high speed (289 TGV/s). Ultimately, the stability of the break strength of the LIDE processed glass substrates is verified by the results of ANSYS simulation and three-point bending test.
基于透玻璃通孔(TGV)的2.5D玻璃中间体技术因其良好的电性能和热膨胀系数(CTE)失配而成为研究热点[1]。本文采用激光诱导深度刻蚀(LIDE)技术在玻璃基板上制备tgv。LIDE工艺主要分为两个步骤:首先，使用皮秒激光对玻璃基板进行修饰。然后，用10% HF蚀刻改性玻璃基板。在湿法蚀刻过程中，由于激光照射区域的变性，激光照射区域的蚀刻速度比未照射区域快。考虑到各种玻璃的性能，我们选择SCHOTT AF 32®生态玻璃和康宁HPFS 7980熔融石英玻璃作为本研究的基板。结果表明，LIDE工艺是一种很有前途的高速TGV制造工艺，可在高速(289 TGV/s)下制造高垂直度TGV (AF 32®生态玻璃的锥度角约为9°，康宁HPFS 7980熔融石英玻璃的锥度角约为1°)。最后，通过ANSYS仿真和三点弯曲试验结果验证了LIDE加工玻璃基板断裂强度的稳定性。
{"title":"Development of Laser-Induced Deep Etching Process for Through Glass Via","authors":"Li Chen, Heng Wu, Mingchuan Zhang, Feng Jiang, Tian Yu, Daquan Yu","doi":"10.1109/ICEPT47577.2019.245208","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245208","url":null,"abstract":"2.5D glass interposer technology based on through glass via (TGV) becomes a hot research topic on account of good electrical property and CTE (coefficient of thermal expansion) mismatch [1]. In this paper, the Laser-Induced Deep Etching (LIDE) technology is used to manufacture TGVs on glass substrate. The LIDE process can be mainly divided into two steps: Initially, picosecond laser is used to modified the glass substrate. Then, using 10% HF etch the modified glass substrate. On account of denaturation of the laser irradiation area, the area where is exposed to the laser will be etched more quickly than unexposed area in the process of wet etching. In consideration of the properties of various glass, SCHOTT AF 32® eco glass and CORNING HPFS 7980 fused silica glass is selected as the substrate of this study. The result show that the LIDE process is a promising high-speed TGVs manufacturing process which can fabricate TGV of high verticality (the taper angle is approximately 9° on AF 32® eco glass and 1° on CORNING HPFS 7980 fused silica glass) at a high speed (289 TGV/s). Ultimately, the stability of the break strength of the LIDE processed glass substrates is verified by the results of ANSYS simulation and three-point bending test.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"28 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82928288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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