Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245235
N. Tu, S. R. Ricky Lee
This paper describes a method to inkjet print Poly (ethylenedioxythiophene): polystyrene sulphonate (PEODT: PSS) without coffee ring effect. PEDOT: PSS is a unique long-chain polymer with conductivity and transparency properties that are mainly used in the packaging process of quantum dot light emitting displays and solar cells. Due to the ability to increase the transparency and conductivity of PEDOT: PSS in recent years, flexibility becomes another advantage of PEDOT: PSS. Therefore, the flexible electronic device such as the flexible quantum dot light emitting diode display, and the flexible solar cell is another exciting application of PEDOT: PSS. In order to save materials and reduce the manufacturing cost, inkjet printing is applied to fabricate the PEDOT: PSS thin film. The uniformity of PEDOT: PSS thin film is the crucial point for the flexible quantum dot light emitting diode display by inkjet printing. While the critical factor to have a uniform and flat PEDOT: PSS thin film is to reduce the coffee ring effect. The coffee ring effect caused by the fast evaporation rate at the edge of the droplet, which results in a higher degree of diffusion freedom at the edge of the droplet; then the capillary forms from the center to the edge, to supply the solvent for evaporation loss. However, the supplied solvent also brings solute to the edge and the solute despite to the edge, which causes the ring shape at the edge of the droplet. In this paper, the coffee ring effect was reduced significantly by adding co-solvent with high boiling point and high viscosity to the primary solvent. The high boiling point of the co-solvent reduces the driving force of the capillary flow, while the high viscosity of the co-solvent increase resistance of the capillary flow as well. What’s more, the surface tension properties of the substrate was modified to increase the wettability of PEDOT: PSS. Thus, PEDOT: PSS thin film with improved uniformity can be obtained due to the reduction of coffee ring effect, which can apply for the packaging process of flexible quantum dot light emitting diode display.
{"title":"Inkjet Printing PEDOT:PSS without Coffee Ring Effect for QLED Applicaitons","authors":"N. Tu, S. R. Ricky Lee","doi":"10.1109/ICEPT47577.2019.245235","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245235","url":null,"abstract":"This paper describes a method to inkjet print Poly (ethylenedioxythiophene): polystyrene sulphonate (PEODT: PSS) without coffee ring effect. PEDOT: PSS is a unique long-chain polymer with conductivity and transparency properties that are mainly used in the packaging process of quantum dot light emitting displays and solar cells. Due to the ability to increase the transparency and conductivity of PEDOT: PSS in recent years, flexibility becomes another advantage of PEDOT: PSS. Therefore, the flexible electronic device such as the flexible quantum dot light emitting diode display, and the flexible solar cell is another exciting application of PEDOT: PSS. In order to save materials and reduce the manufacturing cost, inkjet printing is applied to fabricate the PEDOT: PSS thin film. The uniformity of PEDOT: PSS thin film is the crucial point for the flexible quantum dot light emitting diode display by inkjet printing. While the critical factor to have a uniform and flat PEDOT: PSS thin film is to reduce the coffee ring effect. The coffee ring effect caused by the fast evaporation rate at the edge of the droplet, which results in a higher degree of diffusion freedom at the edge of the droplet; then the capillary forms from the center to the edge, to supply the solvent for evaporation loss. However, the supplied solvent also brings solute to the edge and the solute despite to the edge, which causes the ring shape at the edge of the droplet. In this paper, the coffee ring effect was reduced significantly by adding co-solvent with high boiling point and high viscosity to the primary solvent. The high boiling point of the co-solvent reduces the driving force of the capillary flow, while the high viscosity of the co-solvent increase resistance of the capillary flow as well. What’s more, the surface tension properties of the substrate was modified to increase the wettability of PEDOT: PSS. Thus, PEDOT: PSS thin film with improved uniformity can be obtained due to the reduction of coffee ring effect, which can apply for the packaging process of flexible quantum dot light emitting diode display.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"8 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89860580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245348
Wei Wu, Xianbing Li, Liang Wang, Zhongkang Lin
Insulated Gate Bipolar Transistor (IGBT) is one of the most advanced power electronic devices to realize power conversion and control, which has a strong current processing capability. It is applied more and more widely. In the service process, high current, high voltage and high switching frequency will cause IGBT module to produce greater power losses, resulting in module temperature rise. Temperature has a great influence on the reliability of IGBT. In this paper, the electrothermal finite element analysis of IGBT module under sinusoidal current load is carried out by means of finite element numerical simulation. The temperature distribution and current density distribution of IGBT module are obtained. In order to compare the difference of temperature distribution between sinusoidal current load and direct current load, the electro-thermal analysis under direct current load is also carried out. The results show that the main heat producing area of IGBT module is IGBT chip. In the process of electrical-thermal analysis, the Joule heat generated by IGBT chips conducts downward and eventually dissipates from the base plate to the outside. The current density distribution on the surface of IGBT chips is uneven. The current density near the Al bonding wires is larger, while the current density at the center and edge of the chips is smaller. By comparing the results of electro-thermal analysis under sinusoidal current load and direct current load, it is found that the temperature rise rate, the temperature fluctuation range, the time to reach the maximum temperature and the current density change are quite different under different current waveforms.
{"title":"Electro-thermal finite element analysis of IGBT module under sinusoidal current load","authors":"Wei Wu, Xianbing Li, Liang Wang, Zhongkang Lin","doi":"10.1109/ICEPT47577.2019.245348","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245348","url":null,"abstract":"Insulated Gate Bipolar Transistor (IGBT) is one of the most advanced power electronic devices to realize power conversion and control, which has a strong current processing capability. It is applied more and more widely. In the service process, high current, high voltage and high switching frequency will cause IGBT module to produce greater power losses, resulting in module temperature rise. Temperature has a great influence on the reliability of IGBT. In this paper, the electrothermal finite element analysis of IGBT module under sinusoidal current load is carried out by means of finite element numerical simulation. The temperature distribution and current density distribution of IGBT module are obtained. In order to compare the difference of temperature distribution between sinusoidal current load and direct current load, the electro-thermal analysis under direct current load is also carried out. The results show that the main heat producing area of IGBT module is IGBT chip. In the process of electrical-thermal analysis, the Joule heat generated by IGBT chips conducts downward and eventually dissipates from the base plate to the outside. The current density distribution on the surface of IGBT chips is uneven. The current density near the Al bonding wires is larger, while the current density at the center and edge of the chips is smaller. By comparing the results of electro-thermal analysis under sinusoidal current load and direct current load, it is found that the temperature rise rate, the temperature fluctuation range, the time to reach the maximum temperature and the current density change are quite different under different current waveforms.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"1 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81276914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245299
Min Wang, Shengyu Hu, Songyang Su, Xuanyu Wang, Jiaxing Liu, Cheng Yang
Flexible supercapacitors are considered as a promising candidate for power supplementation in wearable electronics due to their high power density. However, effectively fabricate flexible and low-cost supercapacitor electrodes in a big scale is still a key challenge. Herein we demonstrate a scalable fabrication method for hierarchical electrodes via metalizing air-laid paper and loading with MnO2 as cathode active materials. To be specific, we coat a thin layer of Ni on air-laid paper by magnetron sputtering, then deposit Ni nanocone arrays (NNAs) on the Ni sputtered paper and finally deposit MnO2 on the NNAs to obtain the NNAs@MnO2 paper electrode. The as-prepared paper-based electrode possesses high conductivity and fine wettability, which facilitates the electrons and ions transporting through the conductive network. Additionally, this electrode provides large specific surface area with a hierarchical architecture. Thus the electrode shows high capacitance (451 F/g) and favorable cycle performance (92.9% capacity retention after cycling for 5000 times). By coupling with activated carbon (AC) coated on the NNAs conductive paper as anode, an NNAs paper-based asymmetric supercapacitor is constructed. Benefiting from the high mechanical durability and the 3D hierarchical architecture of the electrodes, the asymmetric supercapacitor exhibits excellent mechanical flexibility and high energy density (26.9 μWh/cm2 at 1.08 mW/cm2). This method can be easily scaled up to produce lightweight and low-cost conductive paper electrodes, making it promising for the application of flexible supercapacitors in wearable electronics.
{"title":"MnO2@Nickel Nanocone Arrays Coated Paper Electrode for Flexible Supercapacitors","authors":"Min Wang, Shengyu Hu, Songyang Su, Xuanyu Wang, Jiaxing Liu, Cheng Yang","doi":"10.1109/ICEPT47577.2019.245299","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245299","url":null,"abstract":"Flexible supercapacitors are considered as a promising candidate for power supplementation in wearable electronics due to their high power density. However, effectively fabricate flexible and low-cost supercapacitor electrodes in a big scale is still a key challenge. Herein we demonstrate a scalable fabrication method for hierarchical electrodes via metalizing air-laid paper and loading with MnO2 as cathode active materials. To be specific, we coat a thin layer of Ni on air-laid paper by magnetron sputtering, then deposit Ni nanocone arrays (NNAs) on the Ni sputtered paper and finally deposit MnO2 on the NNAs to obtain the NNAs@MnO2 paper electrode. The as-prepared paper-based electrode possesses high conductivity and fine wettability, which facilitates the electrons and ions transporting through the conductive network. Additionally, this electrode provides large specific surface area with a hierarchical architecture. Thus the electrode shows high capacitance (451 F/g) and favorable cycle performance (92.9% capacity retention after cycling for 5000 times). By coupling with activated carbon (AC) coated on the NNAs conductive paper as anode, an NNAs paper-based asymmetric supercapacitor is constructed. Benefiting from the high mechanical durability and the 3D hierarchical architecture of the electrodes, the asymmetric supercapacitor exhibits excellent mechanical flexibility and high energy density (26.9 μWh/cm2 at 1.08 mW/cm2). This method can be easily scaled up to produce lightweight and low-cost conductive paper electrodes, making it promising for the application of flexible supercapacitors in wearable electronics.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"901 ","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91546520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The interconnecting joint of space cables get smaller and smaller, when the installation space of assembly is smaller, which is easy lead to wire stress and wire breakage. The purpose of encapsulating of the connector is to protect the cable interconnecting, including crimping and soldering joints, and to reduce the weight of the cables at the same time. In this study, the connectors were injection molded, potted without back shells, and potted with back shells in extravehicular cables. The space accelerated tests including mechanical vibration, mechanical impact, bending, and temperature cycle tests were performed on encapsulated cables. The study on tensile strength, metallography, and Scanning electron microscopy (SEM.) of the interconnecting joints showed that, the electrical performance was good with all three kinds of encapsulating process. Crack and delamination defects were not found in the interface of soldering or crimping joint. The three encapsulating method can effectively protect the interconnecting joint of space cable.
{"title":"Reliability study on the encapsulated space cable assembly under accelerated tests","authors":"Yarong Chen, Zhenming Zhang, Minghua Zhang, Meng Yang, Zhanjun Xia, Cuiping Yuan","doi":"10.1109/ICEPT47577.2019.245341","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245341","url":null,"abstract":"The interconnecting joint of space cables get smaller and smaller, when the installation space of assembly is smaller, which is easy lead to wire stress and wire breakage. The purpose of encapsulating of the connector is to protect the cable interconnecting, including crimping and soldering joints, and to reduce the weight of the cables at the same time. In this study, the connectors were injection molded, potted without back shells, and potted with back shells in extravehicular cables. The space accelerated tests including mechanical vibration, mechanical impact, bending, and temperature cycle tests were performed on encapsulated cables. The study on tensile strength, metallography, and Scanning electron microscopy (SEM.) of the interconnecting joints showed that, the electrical performance was good with all three kinds of encapsulating process. Crack and delamination defects were not found in the interface of soldering or crimping joint. The three encapsulating method can effectively protect the interconnecting joint of space cable.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"35 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90920376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245740
Wenhao Li, Jianrui Xue, Ming Li, Liming Gao
For the study of thermal management of power devices, a typical approach is to use the RC model to describe the thermal state inside the module [1]-[5]. However, there are several limits on the current common practice: First, such RC models are usually one-dimensional, that is, the RC nodes are distributed from top to bottom. However, there is no in-depth study of the state of the node plane; second, the thermal coupling between the chips in the model is not considered, which is different from the actual situation. [6]In this paper, a three-dimensional RC model is built for IGBT module based on the data provided by the finite element simulation method, the module consists of IGBT chip, package and heatsink. Meanwhile, the thermal coupling between the adjacent chips has also been studied, which can numerically reflect the thermal contribution of one chip to another.
{"title":"A 3-D Thermal Model including thermal coupling for Insulated Gate Bipolar Transistor Module","authors":"Wenhao Li, Jianrui Xue, Ming Li, Liming Gao","doi":"10.1109/ICEPT47577.2019.245740","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245740","url":null,"abstract":"For the study of thermal management of power devices, a typical approach is to use the RC model to describe the thermal state inside the module [1]-[5]. However, there are several limits on the current common practice: First, such RC models are usually one-dimensional, that is, the RC nodes are distributed from top to bottom. However, there is no in-depth study of the state of the node plane; second, the thermal coupling between the chips in the model is not considered, which is different from the actual situation. [6]In this paper, a three-dimensional RC model is built for IGBT module based on the data provided by the finite element simulation method, the module consists of IGBT chip, package and heatsink. Meanwhile, the thermal coupling between the adjacent chips has also been studied, which can numerically reflect the thermal contribution of one chip to another.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"3 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89704223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245224
Pei Chen, Zhiwei Zhang, F. Qin
Three-dimensional integration technology using TSV interconnections has emerged as a promising solution to improve the performance of microelectronic devices. It is necessary to study the effect of strain rate and work temperature on the interfacial strength of Cu/Ta interface for microelectronic devices reliability. In this work, to investigate the effect of the temperature and strain rate on the Cu/Ta interfacial properties, a series of large-scale molecular dynamic (MD) simulations were performed. The stress-strain curves and the deformation processes of Cu/Ta interface were obtained. The results showed that the interfacial tensile strength and interfacial shear strength of Cu(010)/Ta(010) interface are 5.56 GPa and 0.465 GPa, respectively, when the strain rate is 109/s and temperature is 300 K. And the location of failure for Cu/Ta interface is closer to the monocrystalline Cu parts. Then, the effects of strain rate and temperature on the interfacial tensile and shear strength were discussed, and the results indicated that the interfacial strength decrease with the decrease of strain rate from 109/s to 107/s. Similarly, the strongest correlation was seen to be between the interfacial strength and temperature, it can be seen that the interfacial tensile and shear strength decrease with increasing of the temperature.
{"title":"Study of interfacial tensile and shear strength for Cu/Ta interface by molecular dynamic simulation","authors":"Pei Chen, Zhiwei Zhang, F. Qin","doi":"10.1109/ICEPT47577.2019.245224","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245224","url":null,"abstract":"Three-dimensional integration technology using TSV interconnections has emerged as a promising solution to improve the performance of microelectronic devices. It is necessary to study the effect of strain rate and work temperature on the interfacial strength of Cu/Ta interface for microelectronic devices reliability. In this work, to investigate the effect of the temperature and strain rate on the Cu/Ta interfacial properties, a series of large-scale molecular dynamic (MD) simulations were performed. The stress-strain curves and the deformation processes of Cu/Ta interface were obtained. The results showed that the interfacial tensile strength and interfacial shear strength of Cu(010)/Ta(010) interface are 5.56 GPa and 0.465 GPa, respectively, when the strain rate is 109/s and temperature is 300 K. And the location of failure for Cu/Ta interface is closer to the monocrystalline Cu parts. Then, the effects of strain rate and temperature on the interfacial tensile and shear strength were discussed, and the results indicated that the interfacial strength decrease with the decrease of strain rate from 109/s to 107/s. Similarly, the strongest correlation was seen to be between the interfacial strength and temperature, it can be seen that the interfacial tensile and shear strength decrease with increasing of the temperature.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"17 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87249491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245814
Weikang Si, Libing Zheng, Shuhua Wei
The shrinking in feature size and the increasing operation frequency of integrated devices make temperature characterization and thermal management a crucial aspect of integrated circuit performance and design. To address these challenges, accurate information of temperature distribution or thermal properties at submicron scale is required. There are diverse methods to measure temperature distribution of devices. Infrared thermal imaging is a common method. However, its spatial resolution is limited to several micrometers due to diffraction effect. And its temporal resolution is limited to 2 ms. As a new emerging technique, thermoreflectance imaging is non-contact, nondestructive and has advantages in high temporal and spatial resolution which is useful for hot spot detection and thermal failures prediction. This paper gives an overview of thermoreflectance thermal imaging technique and a description of a home-made setup. The parameter thermoreflectance coefficient is critical for the technique, as it is material and wavelength dependent. This paper provides a general way to acquire thermoreflectance coefficient. In order to demonstrate the advantages of the technique, transient thermal measurement on a micro-resistor is undertaken using this setup.
{"title":"Thermal distribution measurement upon micro-resistance lines using Thermoreflectance technique","authors":"Weikang Si, Libing Zheng, Shuhua Wei","doi":"10.1109/ICEPT47577.2019.245814","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245814","url":null,"abstract":"The shrinking in feature size and the increasing operation frequency of integrated devices make temperature characterization and thermal management a crucial aspect of integrated circuit performance and design. To address these challenges, accurate information of temperature distribution or thermal properties at submicron scale is required. There are diverse methods to measure temperature distribution of devices. Infrared thermal imaging is a common method. However, its spatial resolution is limited to several micrometers due to diffraction effect. And its temporal resolution is limited to 2 ms. As a new emerging technique, thermoreflectance imaging is non-contact, nondestructive and has advantages in high temporal and spatial resolution which is useful for hot spot detection and thermal failures prediction. This paper gives an overview of thermoreflectance thermal imaging technique and a description of a home-made setup. The parameter thermoreflectance coefficient is critical for the technique, as it is material and wavelength dependent. This paper provides a general way to acquire thermoreflectance coefficient. In order to demonstrate the advantages of the technique, transient thermal measurement on a micro-resistor is undertaken using this setup.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"29 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88283490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245093
Brian Shieh, Fangyun Zeng, Guoming Yang, Fanny Zhao, C. Sher, S. R. Ricky Lee
An IR vertical-cavity surface-emitting laser (VCSEL) with a peak wavelength 940nm for ToF/Flood applications is characterized by the empirical modelling. This paper presents a novel approach to predict pulsed junction temperature rise of VCSELs using T3ster to extend the time-resolved measuring with a constant bias current based on the JESD51-14. For different DC bias currents, it is found the normalized junction temperature rise and drop curves with a reflectional symmetry suggest the same thermal model for simplifying the measurement. For the pulse bias, the thermal behavior of VCSEL due to frequency, duty and pulse number is studied. And an algorithm predicting the pulsed junction temperature rise and fluctuation were proposed and showing a good consistent result with the measurement of the T3ster at the first few pulses with low duties. The result also shown the pulsed optical power output was reduced due to the increase of the junction temperature rise in the pulse duty.
{"title":"Empirical Modeling and measurement of the Pulsed Junction Temperature of VCSEL","authors":"Brian Shieh, Fangyun Zeng, Guoming Yang, Fanny Zhao, C. Sher, S. R. Ricky Lee","doi":"10.1109/ICEPT47577.2019.245093","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245093","url":null,"abstract":"An IR vertical-cavity surface-emitting laser (VCSEL) with a peak wavelength 940nm for ToF/Flood applications is characterized by the empirical modelling. This paper presents a novel approach to predict pulsed junction temperature rise of VCSELs using T3ster to extend the time-resolved measuring with a constant bias current based on the JESD51-14. For different DC bias currents, it is found the normalized junction temperature rise and drop curves with a reflectional symmetry suggest the same thermal model for simplifying the measurement. For the pulse bias, the thermal behavior of VCSEL due to frequency, duty and pulse number is studied. And an algorithm predicting the pulsed junction temperature rise and fluctuation were proposed and showing a good consistent result with the measurement of the T3ster at the first few pulses with low duties. The result also shown the pulsed optical power output was reduced due to the increase of the junction temperature rise in the pulse duty.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"44 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88232759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245331
Liyou Zhao, Zebin Kong
Aerospace applications require high performance and reliability of products. Whether the solderability of components is good or not before welding determines directly the welding quality of products. In this paper, the author classified and analyzed the cases of poor solderability of outer lead of aerospace components which we experienced in recent years. The quality assurance method of solderability is discussed. Failure causes related to poor solderability include organics adsorption, porosity and crack of coating, insufficient thickness of coating, selection of coating materials, coating damage. This paper is of great significance to the improvement of solderability of aerospace components, and has important reference value for the application of civil components.
{"title":"Poor solderability analysis of outer lead of aerospace components","authors":"Liyou Zhao, Zebin Kong","doi":"10.1109/ICEPT47577.2019.245331","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245331","url":null,"abstract":"Aerospace applications require high performance and reliability of products. Whether the solderability of components is good or not before welding determines directly the welding quality of products. In this paper, the author classified and analyzed the cases of poor solderability of outer lead of aerospace components which we experienced in recent years. The quality assurance method of solderability is discussed. Failure causes related to poor solderability include organics adsorption, porosity and crack of coating, insufficient thickness of coating, selection of coating materials, coating damage. This paper is of great significance to the improvement of solderability of aerospace components, and has important reference value for the application of civil components.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"66 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86677751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The influence of different stress methods on Metal-Oxide-Nitride-Oxide-Silicon (MONOS) layer breakdown was investigated. In this paper, two different stress modes, DC and AC stress, were applied to systematically study stress condition effects on MONOS breakdown. According to the electrical failure analysis (EFA) results, MONOS layer is more vulnerable to dielectric breakdown under AC stress due to its higher defects generation efficiency. Besides, the physical failure analysis (PFA) revealed different breakdown mechanisms for DC and AC stress modes. These results help understand different stress methods impact on 3D NAND flash reliability.
{"title":"The Effect of Different Stress Conditions on MONOS Breakdown for 3D NAND Flash Memory","authors":"Junpeng He, X. Tian, Hekun Zhang, Zhe Song, Qianqian Yu, Liang Li, Ming Li, Liming Gao","doi":"10.1109/ICEPT47577.2019.245807","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245807","url":null,"abstract":"The influence of different stress methods on Metal-Oxide-Nitride-Oxide-Silicon (MONOS) layer breakdown was investigated. In this paper, two different stress modes, DC and AC stress, were applied to systematically study stress condition effects on MONOS breakdown. According to the electrical failure analysis (EFA) results, MONOS layer is more vulnerable to dielectric breakdown under AC stress due to its higher defects generation efficiency. Besides, the physical failure analysis (PFA) revealed different breakdown mechanisms for DC and AC stress modes. These results help understand different stress methods impact on 3D NAND flash reliability.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"72 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85705089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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