Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245775
Zizhou Yang, Yang Peng, Hao-Chun Cheng, Chen Liu, Mingxiang Chen
In this work, three dimensional direct plated copper (3DPC) ceramic substrate prepared by repeated ultraviolet (UV) depth lithography and electroforming is proposed. The effects of different electroforming parameters including current density, stirring speed, and temperature were evaluated by internal stress and electroforming rate using a L9(34) orthogonal experiment. Range analysis and analysis of variance (ANOVA) were employed to estimate the contribution of each factor to the overall response. The optimal electrodeposition parameters were the current density of 4 ASD, the stirring speed of 1200 rpm, and the temperature of 50 °C. Furthermore, the microstructure, hermeticity, and thermal reliability of 3DPC substrate were researched. The results showed the 3DPC substrate had excellent hermeticity and the strong bonding strength between dam and flat DPC substrate even after 30 thermal cycles. The above results demonstrated that 3DPC substrate could be considered as a reliable substrate for UV-LED hermetic packaging.
{"title":"Three-dimensional ceramic substrate prepared by repeated lithography and electroforming","authors":"Zizhou Yang, Yang Peng, Hao-Chun Cheng, Chen Liu, Mingxiang Chen","doi":"10.1109/ICEPT47577.2019.245775","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245775","url":null,"abstract":"In this work, three dimensional direct plated copper (3DPC) ceramic substrate prepared by repeated ultraviolet (UV) depth lithography and electroforming is proposed. The effects of different electroforming parameters including current density, stirring speed, and temperature were evaluated by internal stress and electroforming rate using a L9(34) orthogonal experiment. Range analysis and analysis of variance (ANOVA) were employed to estimate the contribution of each factor to the overall response. The optimal electrodeposition parameters were the current density of 4 ASD, the stirring speed of 1200 rpm, and the temperature of 50 °C. Furthermore, the microstructure, hermeticity, and thermal reliability of 3DPC substrate were researched. The results showed the 3DPC substrate had excellent hermeticity and the strong bonding strength between dam and flat DPC substrate even after 30 thermal cycles. The above results demonstrated that 3DPC substrate could be considered as a reliable substrate for UV-LED hermetic packaging.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"52 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83129198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The finite element analysis model of residual stress after reflow soldering of QFN lead-free solder joints is established in this paper, and the residual stress after reflow soldering was analyzed under thermal structural coupling conditions. With the solder joint height, lead pitch, chip thickness and PCB thickness as design factors, 9 solder joints model of QFN with different levels combination were designed and the maximum residual stress values of the 9 solder joints model of QFN were obtained by simulation analysis. And carried out the range analysis for structural parameters of the QFN solder joints model. The results show that the residual stress of QFN solder joints is unevenly distributed. The maximum residual stress appears in the contact point between the solder joints and the chip and farthest from the chip center. The order of the influence for residual stress after reflow soldering from large to small is solder joint height, chip thickness, PCB thickness and lead pitch. Provides theoretical guidance for controlling residual stress after reflow soldering of QFN.
{"title":"Analysis of residual stress after reflow soldering of QFN package","authors":"Sheng-jun Zhao, Chunyue Huang, Xiang-qiong Tang, Ying Liang","doi":"10.1109/ICEPT47577.2019.245833","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245833","url":null,"abstract":"The finite element analysis model of residual stress after reflow soldering of QFN lead-free solder joints is established in this paper, and the residual stress after reflow soldering was analyzed under thermal structural coupling conditions. With the solder joint height, lead pitch, chip thickness and PCB thickness as design factors, 9 solder joints model of QFN with different levels combination were designed and the maximum residual stress values of the 9 solder joints model of QFN were obtained by simulation analysis. And carried out the range analysis for structural parameters of the QFN solder joints model. The results show that the residual stress of QFN solder joints is unevenly distributed. The maximum residual stress appears in the contact point between the solder joints and the chip and farthest from the chip center. The order of the influence for residual stress after reflow soldering from large to small is solder joint height, chip thickness, PCB thickness and lead pitch. Provides theoretical guidance for controlling residual stress after reflow soldering of QFN.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"58 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80027498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
2.5D glass interposer technology based on through glass via (TGV) becomes a hot research topic on account of good electrical property and CTE (coefficient of thermal expansion) mismatch [1]. In this paper, the Laser-Induced Deep Etching (LIDE) technology is used to manufacture TGVs on glass substrate. The LIDE process can be mainly divided into two steps: Initially, picosecond laser is used to modified the glass substrate. Then, using 10% HF etch the modified glass substrate. On account of denaturation of the laser irradiation area, the area where is exposed to the laser will be etched more quickly than unexposed area in the process of wet etching. In consideration of the properties of various glass, SCHOTT AF 32® eco glass and CORNING HPFS 7980 fused silica glass is selected as the substrate of this study. The result show that the LIDE process is a promising high-speed TGVs manufacturing process which can fabricate TGV of high verticality (the taper angle is approximately 9° on AF 32® eco glass and 1° on CORNING HPFS 7980 fused silica glass) at a high speed (289 TGV/s). Ultimately, the stability of the break strength of the LIDE processed glass substrates is verified by the results of ANSYS simulation and three-point bending test.
基于透玻璃通孔(TGV)的2.5D玻璃中间体技术因其良好的电性能和热膨胀系数(CTE)失配而成为研究热点[1]。本文采用激光诱导深度刻蚀(LIDE)技术在玻璃基板上制备tgv。LIDE工艺主要分为两个步骤:首先，使用皮秒激光对玻璃基板进行修饰。然后，用10% HF蚀刻改性玻璃基板。在湿法蚀刻过程中，由于激光照射区域的变性，激光照射区域的蚀刻速度比未照射区域快。考虑到各种玻璃的性能，我们选择SCHOTT AF 32®生态玻璃和康宁HPFS 7980熔融石英玻璃作为本研究的基板。结果表明，LIDE工艺是一种很有前途的高速TGV制造工艺，可在高速(289 TGV/s)下制造高垂直度TGV (AF 32®生态玻璃的锥度角约为9°，康宁HPFS 7980熔融石英玻璃的锥度角约为1°)。最后，通过ANSYS仿真和三点弯曲试验结果验证了LIDE加工玻璃基板断裂强度的稳定性。
{"title":"Development of Laser-Induced Deep Etching Process for Through Glass Via","authors":"Li Chen, Heng Wu, Mingchuan Zhang, Feng Jiang, Tian Yu, Daquan Yu","doi":"10.1109/ICEPT47577.2019.245208","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245208","url":null,"abstract":"2.5D glass interposer technology based on through glass via (TGV) becomes a hot research topic on account of good electrical property and CTE (coefficient of thermal expansion) mismatch [1]. In this paper, the Laser-Induced Deep Etching (LIDE) technology is used to manufacture TGVs on glass substrate. The LIDE process can be mainly divided into two steps: Initially, picosecond laser is used to modified the glass substrate. Then, using 10% HF etch the modified glass substrate. On account of denaturation of the laser irradiation area, the area where is exposed to the laser will be etched more quickly than unexposed area in the process of wet etching. In consideration of the properties of various glass, SCHOTT AF 32® eco glass and CORNING HPFS 7980 fused silica glass is selected as the substrate of this study. The result show that the LIDE process is a promising high-speed TGVs manufacturing process which can fabricate TGV of high verticality (the taper angle is approximately 9° on AF 32® eco glass and 1° on CORNING HPFS 7980 fused silica glass) at a high speed (289 TGV/s). Ultimately, the stability of the break strength of the LIDE processed glass substrates is verified by the results of ANSYS simulation and three-point bending test.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"28 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82928288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245146
Lin Daotan, Wang Yong, Xie Zhenfeng, Wu Qin, He Shengzong
Thin film resistor as a passive component, is widely used in automotive electronics, because of its smaller size, lower cost, high precision and low temperature coefficient. With the continuous development of new energy vehicle, the reliability of automotive electronics comes to be a focus. As a result, the stability and reliability of thin film resistor is being paid more and more attention nowadays. In this paper, the structure and manufacturing process of thin film resistor would be briefly introduced. The common failure modes of thin film resistor would be summarized. Moreover, a case study would be presented in this paper to show the effect of thin resistive film’s structure on the reliability of automotive electronics applications. In this case, the voltage of resistor under different working conditions was tested, and the generation of abnormal voltage in circuit was explained. According to the case, with the decrease of the number of resistor unit, the reliability of the resistor decreased. In order to improve the reliability of thin film resistor, the structural consistency of resistive film should be emphasized.
{"title":"Study on the Effect of Thin Resistive Film’s Structure on the Reliability of Automotive Electronics","authors":"Lin Daotan, Wang Yong, Xie Zhenfeng, Wu Qin, He Shengzong","doi":"10.1109/ICEPT47577.2019.245146","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245146","url":null,"abstract":"Thin film resistor as a passive component, is widely used in automotive electronics, because of its smaller size, lower cost, high precision and low temperature coefficient. With the continuous development of new energy vehicle, the reliability of automotive electronics comes to be a focus. As a result, the stability and reliability of thin film resistor is being paid more and more attention nowadays. In this paper, the structure and manufacturing process of thin film resistor would be briefly introduced. The common failure modes of thin film resistor would be summarized. Moreover, a case study would be presented in this paper to show the effect of thin resistive film’s structure on the reliability of automotive electronics applications. In this case, the voltage of resistor under different working conditions was tested, and the generation of abnormal voltage in circuit was explained. According to the case, with the decrease of the number of resistor unit, the reliability of the resistor decreased. In order to improve the reliability of thin film resistor, the structural consistency of resistive film should be emphasized.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"55 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83742125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245269
Xiao Jun, Yi Wenshuang, Zhang Yuming, Yang Xiaoqiang, Huang Cheng, Ye Da
With the continuous development of IC (Integrated Circuit) technology, it has been widely used in all aspects of manufacture, production, consumption and so on, and IC filter as an important part of its production testing is directly related to the quality of IC, and with the wide application of automatic separating system of IC, production testing efficiency and quality was improved greatly. Domestic and international industrial separating systems are mainly developed for mass production and are suitable for civilian products in a single package. Due to its special requirements such as small batch size, multiple varieties, and data traceability, the research institutes ASIC(application-speciflc integrated circuit) is difficult to directly use industrial separating system. At the present time, package ID(identification) number was mainly detected by the naked eye and manual separating method was basically used in China. Therefore, there are many disadvantages such as low efficiency, error-prone, high cost, and the influence of human factors on the quality of IC.Due to the characteristics of the research institutes ASIC production, there are a large number of problems in product separating. In order to improve the production test efficiency and ensure the product quality, an automatic production test separating system of ASIC with package ID number detection has been developed. The system is based on the architecture of the embedded system platform and is mainly composed of the upper computer, the lower computer and the mechanical implementation. First of all, the upper computer software is implemented by the Virtual Basic language in the Virtual Studio platform. Secondly, The lower computer is based on the STM32F407IGH6 of ARM7 architecture, and is implemented by μC/OS III embedded OS(operating system) for mechanical part controlling and host computer interaction. At last, the mechanical part guarantees the test separating of different types of IC through high-magnification cameras, highresolution servo motors and high-precision screw mechanisms. Specially the package ID number detection system is implemented the detection algorithm through the NI-VDM module.Practical application has proved that the system is very stable and reliable, which greatly facilitates the detection of package ID number of IC, greatly reduces or avoids the occurrence of ASIC quality problems, greatly improves the efficiency of production testing, greatly meet the requirements of production, and has far-reaching practical significance.
{"title":"Automatic production test separating system of ASIC with package ID detection","authors":"Xiao Jun, Yi Wenshuang, Zhang Yuming, Yang Xiaoqiang, Huang Cheng, Ye Da","doi":"10.1109/ICEPT47577.2019.245269","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245269","url":null,"abstract":"With the continuous development of IC (Integrated Circuit) technology, it has been widely used in all aspects of manufacture, production, consumption and so on, and IC filter as an important part of its production testing is directly related to the quality of IC, and with the wide application of automatic separating system of IC, production testing efficiency and quality was improved greatly. Domestic and international industrial separating systems are mainly developed for mass production and are suitable for civilian products in a single package. Due to its special requirements such as small batch size, multiple varieties, and data traceability, the research institutes ASIC(application-speciflc integrated circuit) is difficult to directly use industrial separating system. At the present time, package ID(identification) number was mainly detected by the naked eye and manual separating method was basically used in China. Therefore, there are many disadvantages such as low efficiency, error-prone, high cost, and the influence of human factors on the quality of IC.Due to the characteristics of the research institutes ASIC production, there are a large number of problems in product separating. In order to improve the production test efficiency and ensure the product quality, an automatic production test separating system of ASIC with package ID number detection has been developed. The system is based on the architecture of the embedded system platform and is mainly composed of the upper computer, the lower computer and the mechanical implementation. First of all, the upper computer software is implemented by the Virtual Basic language in the Virtual Studio platform. Secondly, The lower computer is based on the STM32F407IGH6 of ARM7 architecture, and is implemented by μC/OS III embedded OS(operating system) for mechanical part controlling and host computer interaction. At last, the mechanical part guarantees the test separating of different types of IC through high-magnification cameras, highresolution servo motors and high-precision screw mechanisms. Specially the package ID number detection system is implemented the detection algorithm through the NI-VDM module.Practical application has proved that the system is very stable and reliable, which greatly facilitates the detection of package ID number of IC, greatly reduces or avoids the occurrence of ASIC quality problems, greatly improves the efficiency of production testing, greatly meet the requirements of production, and has far-reaching practical significance.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"62 2 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89811162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Excellent material properties of gallium nitride (GaN) make it have broad application prospects in the fields of medium and low voltage consumer power, new energy vehicles, charging piles. The conventional GaN high electron mobility transistor (GaN HEMT) is in the ON-state at zero gate bias, which is inconsistent with the actual application requirements. So the regulation of the threshold voltage of GaN devices is currently the research hotspot. Among the existing methods, the p-GaN structure is relatively mature and has been applied in practical products, but there are still many problems in related research. This paper mainly studies the influence of some structural parameters of the device on its threshold voltage and saturation current. The structural parameters considered in this paper mainly include the barrier layer Al composition and the length of the p-GaN layer. The breakdown characteristics of the device after optimizing the structural parameters are simulated. The optimized device threshold voltage is 1.4V and the breakdown voltage is 650V.
{"title":"Gate and barrier layer design of E-mode GaN HEMT with p-GaN gate structure","authors":"Wanjie Li, Xianping Chen, Liming Wang, Xu Zhang, Xian-dong Li, Luqi Tao","doi":"10.1109/ICEPT47577.2019.245737","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245737","url":null,"abstract":"Excellent material properties of gallium nitride (GaN) make it have broad application prospects in the fields of medium and low voltage consumer power, new energy vehicles, charging piles. The conventional GaN high electron mobility transistor (GaN HEMT) is in the ON-state at zero gate bias, which is inconsistent with the actual application requirements. So the regulation of the threshold voltage of GaN devices is currently the research hotspot. Among the existing methods, the p-GaN structure is relatively mature and has been applied in practical products, but there are still many problems in related research. This paper mainly studies the influence of some structural parameters of the device on its threshold voltage and saturation current. The structural parameters considered in this paper mainly include the barrier layer Al composition and the length of the p-GaN layer. The breakdown characteristics of the device after optimizing the structural parameters are simulated. The optimized device threshold voltage is 1.4V and the breakdown voltage is 650V.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"60 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90230262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
AlN is considered to be a promising substrate and packaging material for high power integrated circuits because of its high thermal conductivity, low dielectric constant, and thermal expansion coefficient close to that of silicon. In this paper, AlN green tape was manufactured by tape casting method. The effect of Er2O3 on the phase composition, thermal conductivity, microstructure and mechanical properties of AlN ceramics has been studied. X-ray diffraction was employed to identify the phases formed during sintering. The results showed that Er2O3 promoted the densification of AlN ceramics due to the formation of liquid phase Er3Al5O12 and ErAlO3. As the sintering temperature increased, one of the second phases Er3Al5O12 disappeared, reacting with Er2O3, and left the other second phase ErAlO3. AlN ceramics, sintered at 1820°C for 3h, presented improved thermal conductivity of 181W/(m•K) and bending strength up to 402MPa.
{"title":"Effect of Er2O3 on the properties of AlN ceramics by tape casting","authors":"Hong-bo Bai, Xiao-hui Zhang, Ya-guang Wu, Yi-zheng Zhang, D. Zhao, Ling-su Gao","doi":"10.1109/ICEPT47577.2019.245173","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245173","url":null,"abstract":"AlN is considered to be a promising substrate and packaging material for high power integrated circuits because of its high thermal conductivity, low dielectric constant, and thermal expansion coefficient close to that of silicon. In this paper, AlN green tape was manufactured by tape casting method. The effect of Er<inf>2</inf>O<inf>3</inf> on the phase composition, thermal conductivity, microstructure and mechanical properties of AlN ceramics has been studied. X-ray diffraction was employed to identify the phases formed during sintering. The results showed that Er<inf>2</inf>O<inf>3</inf> promoted the densification of AlN ceramics due to the formation of liquid phase Er<inf>3</inf>Al<inf>5</inf>O<inf>12</inf> and ErAlO<inf>3</inf>. As the sintering temperature increased, one of the second phases Er<inf>3</inf>Al<inf>5</inf>O<inf>12</inf> disappeared, reacting with Er<inf>2</inf>O<inf>3</inf>, and left the other second phase ErAlO<inf>3</inf>. AlN ceramics, sintered at 1820°C for 3h, presented improved thermal conductivity of 181W/(m•K) and bending strength up to 402MPa.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"39 23","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91404912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245830
Dongjin Kim, Chuantong Chen, K. Suganuma
This study was carried out to evaluate the high-temperature and long-term reliability of a GaN/DBA die-attached module with Ag sinter joining and with high temperature solder in a harsh thermal aging process. And its performance compared with high temperature Pb-5Sn solder. A GaN die was structurally sound bonded on a DBA substrate by using a micron/submicron Ag sinter paste and a high content lead solder, respectively. The assembled specimens were subjected to a thermal aging test up to 500 storage hours at 250 °C, then die-shear tested. The initial shear strength of the Ag sinter joint achieved above 42 MPa, the Pb-5Sn joint was above 37MPa. In case of the sintered Ag structure sustained durable die shear strength after 250 hours of the thermal aging. On the other hand, the Pb-5Sn joints exhibited significantly decreased shear strength after 250 and 500 hours of the thermal aging by 60%. Consequently, the Ag sinter joints strengthen during isothermal aging with a necking growth without any defects. Pb-5Sn solder joints formed the NixSnx IMCs by thermal aging. These microstructure characteristics have an important influence on the fracture mechanism, the tendency of fracture path was investigated by SEM-EDX. The thermal aging behavior of a GaN/DBA die-attached module will be addressed further in this paper.
{"title":"Microstructural and mechanical reliability of a GaN/DBA die-attached module with Ag sinter joining in harsh thermal environments","authors":"Dongjin Kim, Chuantong Chen, K. Suganuma","doi":"10.1109/ICEPT47577.2019.245830","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245830","url":null,"abstract":"This study was carried out to evaluate the high-temperature and long-term reliability of a GaN/DBA die-attached module with Ag sinter joining and with high temperature solder in a harsh thermal aging process. And its performance compared with high temperature Pb-5Sn solder. A GaN die was structurally sound bonded on a DBA substrate by using a micron/submicron Ag sinter paste and a high content lead solder, respectively. The assembled specimens were subjected to a thermal aging test up to 500 storage hours at 250 °C, then die-shear tested. The initial shear strength of the Ag sinter joint achieved above 42 MPa, the Pb-5Sn joint was above 37MPa. In case of the sintered Ag structure sustained durable die shear strength after 250 hours of the thermal aging. On the other hand, the Pb-5Sn joints exhibited significantly decreased shear strength after 250 and 500 hours of the thermal aging by 60%. Consequently, the Ag sinter joints strengthen during isothermal aging with a necking growth without any defects. Pb-5Sn solder joints formed the NixSnx IMCs by thermal aging. These microstructure characteristics have an important influence on the fracture mechanism, the tendency of fracture path was investigated by SEM-EDX. The thermal aging behavior of a GaN/DBA die-attached module will be addressed further in this paper.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"27 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82174093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245160
Cunjiang Song, Xuewei Du, Jie Xuan, Zongtao Li, Jiasheng Li, Xinrui Ding
Quantum dots (QDs) have broad application prospects in display such as full color light-emitting diode (LED) devices due to their narrow emission half-peak width and high quantum yield. However, an ultra-high concentration of QD is required to eliminate the pumping light (typical blue light with short wavelength) for achieving high color purity, leading to significant reduction in the optical power of QDs. In this paper, we have introduced the blue light absorber (BLA) in green quantum dot-light emitting diodes (GQD-LEDs) to adjust the color coordinates. Results indicate that the increase of the QD concentration can eliminate the blue light and increase the color purity, while it simultaneously decreases of the optical power of QDs owing the reabsorption loss. The BLA layer has high absorption for short-wavelength light (less than 460 nm), which greatly reduces the optical power of blue light by 74% and leads to a large shift in the color coordinates from (0.17, 0.22) to (0.18, 0.47). Moreover, the BLA layer has a high transmittance for the long-wavelength light, thereby ensuring a high green optical power for BLA devices. Consequently, the proposed method has great potential for the future application of QD-LED in full color display.
{"title":"Color Purity Enhancement of Green Quantum Dot Light-Emitting Diodes Using the Blue Light Absorber Packaging Structure","authors":"Cunjiang Song, Xuewei Du, Jie Xuan, Zongtao Li, Jiasheng Li, Xinrui Ding","doi":"10.1109/ICEPT47577.2019.245160","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245160","url":null,"abstract":"Quantum dots (QDs) have broad application prospects in display such as full color light-emitting diode (LED) devices due to their narrow emission half-peak width and high quantum yield. However, an ultra-high concentration of QD is required to eliminate the pumping light (typical blue light with short wavelength) for achieving high color purity, leading to significant reduction in the optical power of QDs. In this paper, we have introduced the blue light absorber (BLA) in green quantum dot-light emitting diodes (GQD-LEDs) to adjust the color coordinates. Results indicate that the increase of the QD concentration can eliminate the blue light and increase the color purity, while it simultaneously decreases of the optical power of QDs owing the reabsorption loss. The BLA layer has high absorption for short-wavelength light (less than 460 nm), which greatly reduces the optical power of blue light by 74% and leads to a large shift in the color coordinates from (0.17, 0.22) to (0.18, 0.47). Moreover, the BLA layer has a high transmittance for the long-wavelength light, thereby ensuring a high green optical power for BLA devices. Consequently, the proposed method has great potential for the future application of QD-LED in full color display.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"7 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78432120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245827
T. Egawa, Hao Zhang, Takanori Kobatake, Yasuyuki Akai, Chuantong Chen, K. Suganuma
Silver sinter joining paste has been seen as the most promising candidate for die-attachment materials of next-generation power devices. However, there are still technique issues to be overcome before its actual utilization such as sinterability under various atmosphere and the lack of rapid sintering ability. In this research, on the basis of reported silver hybrid paste, an optimized paste composition which is composed of silver micron flakes, silver submicron particles, silver nanoparticles and ether-type solvent has been established. The newly developed paste has proper viscosity which can inhibit the leakage tendency of solvent during mask-printing. Its sintering property has been systematically evaluated and an omnipotent sinterability under various atmosphere has been observed. Moreover, the rapid sintering property drastically shorten the sintering temperature from at least 30 min to 10 min. These results suggest that the modified silver hybrid sinter joining paste can accelerate the further application of next-generation power devices owing to its obvious process advantage and excellent performance.
{"title":"Sinterability improvement of hybrid silver sinter joining paste by adding silver nanoparticles","authors":"T. Egawa, Hao Zhang, Takanori Kobatake, Yasuyuki Akai, Chuantong Chen, K. Suganuma","doi":"10.1109/ICEPT47577.2019.245827","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245827","url":null,"abstract":"Silver sinter joining paste has been seen as the most promising candidate for die-attachment materials of next-generation power devices. However, there are still technique issues to be overcome before its actual utilization such as sinterability under various atmosphere and the lack of rapid sintering ability. In this research, on the basis of reported silver hybrid paste, an optimized paste composition which is composed of silver micron flakes, silver submicron particles, silver nanoparticles and ether-type solvent has been established. The newly developed paste has proper viscosity which can inhibit the leakage tendency of solvent during mask-printing. Its sintering property has been systematically evaluated and an omnipotent sinterability under various atmosphere has been observed. Moreover, the rapid sintering property drastically shorten the sintering temperature from at least 30 min to 10 min. These results suggest that the modified silver hybrid sinter joining paste can accelerate the further application of next-generation power devices owing to its obvious process advantage and excellent performance.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"9 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78776687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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