Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245096
Pengfei Yin, Yujie Li, Peng Zhang, Gang Xiao, Hai Yuan
In a system-in-package (SiP), a large number of devices with different functions are integrated in a single package. A good cooling system is crucial for the performance of the SiP, especially when high-power devices are included. In this work, cooling for high-power SiP modules with low temperature co-fired ceramic (LTCC) substrates were studied. Metal pillar arrays as well as microfluidic cooling channels were embedded in the LTCC substrates to enhance the heat transfer process both passively and actively. The finite element method was used to perform multi-physics coupling simulations. The temperature distribution throughout the substrate and the chip as well as the fluid flow field distribution in the microchannel was analyzed. Various cooling strategies for the SiP were compared. When metal pillar arrays with a simple square-shaped microchannel were embedded in the substrate, the most efficient cooling was achieved under a hybrid cooling mechanism including high-efficiency heat conduction and liquid convection.
{"title":"On-chip heat dissipation design for high-power SiP modules with LTCC substrates","authors":"Pengfei Yin, Yujie Li, Peng Zhang, Gang Xiao, Hai Yuan","doi":"10.1109/ICEPT47577.2019.245096","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245096","url":null,"abstract":"In a system-in-package (SiP), a large number of devices with different functions are integrated in a single package. A good cooling system is crucial for the performance of the SiP, especially when high-power devices are included. In this work, cooling for high-power SiP modules with low temperature co-fired ceramic (LTCC) substrates were studied. Metal pillar arrays as well as microfluidic cooling channels were embedded in the LTCC substrates to enhance the heat transfer process both passively and actively. The finite element method was used to perform multi-physics coupling simulations. The temperature distribution throughout the substrate and the chip as well as the fluid flow field distribution in the microchannel was analyzed. Various cooling strategies for the SiP were compared. When metal pillar arrays with a simple square-shaped microchannel were embedded in the substrate, the most efficient cooling was achieved under a hybrid cooling mechanism including high-efficiency heat conduction and liquid convection.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"32 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84400975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245195
Wang-yun Li, Guanghua Peng, Tianwen Cheng, H. Qin, Jia-Qiang Huang, Dao-Guo Yang
Shear deformation and fracture behavior of microscale BGA structure Cu/Sn-3.0Ag-0.5Cu/Cu joints with a pad diameter 320 μm and a joint height 220 μm and different solder ball diameters 600, 500 and 400 μm (i.e., different solder volumes) were investigated at a temperature from 25 to -120 ºC in this study. Results show that, when the solder ball diameter of the solder joint is 600 μm, the shear strength increases with the descending temperature; while, as the solder ball diameter of the solder joint decreases to 500 and 400 μm, a peak shear strength appeared at -100 and -80 ºC, respectively. Moreover, the fracture behavior of all the joints is temperature dependent. Regardless of the solder ball diameter, the joint fracture position keeps in the solder matrix at a higher temperature, which shifts to the interface between the solder and the interfacial Cu6Sn5 layer at a lower temperature, and the fracture mode shows a ductile-to-brittle transition with the descending temperature. Moreover, the temperature of the ductile-to-brittle transition is joint size dependent, which is lowered as the solder ball diameter decreases.
{"title":"Shear performance of microscale BGA structure Cu/Sn-3.0Ag-0.5Cu/Cu joints with shrinking volume at low and cryogenic temperatures","authors":"Wang-yun Li, Guanghua Peng, Tianwen Cheng, H. Qin, Jia-Qiang Huang, Dao-Guo Yang","doi":"10.1109/ICEPT47577.2019.245195","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245195","url":null,"abstract":"Shear deformation and fracture behavior of microscale BGA structure Cu/Sn-3.0Ag-0.5Cu/Cu joints with a pad diameter 320 μm and a joint height 220 μm and different solder ball diameters 600, 500 and 400 μm (i.e., different solder volumes) were investigated at a temperature from 25 to -120 ºC in this study. Results show that, when the solder ball diameter of the solder joint is 600 μm, the shear strength increases with the descending temperature; while, as the solder ball diameter of the solder joint decreases to 500 and 400 μm, a peak shear strength appeared at -100 and -80 ºC, respectively. Moreover, the fracture behavior of all the joints is temperature dependent. Regardless of the solder ball diameter, the joint fracture position keeps in the solder matrix at a higher temperature, which shifts to the interface between the solder and the interfacial Cu6Sn5 layer at a lower temperature, and the fracture mode shows a ductile-to-brittle transition with the descending temperature. Moreover, the temperature of the ductile-to-brittle transition is joint size dependent, which is lowered as the solder ball diameter decreases.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"79 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85480335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245794
Jack Q. Zhao
In this paper, typical plasma applications for WLP, such as improving Cu-PI interface adhesion, increasing the PI surface roughness, reducing the current leakage in WLP, the oxide removal from bump surface, avoiding microvoids between Cu seed layer and electric Cu plating layer, TSV cleaning, EMC removal from solder balls on wafer, and wafer-on-frame treatment, are mentioned. Some first-hand data are shown and discussed in the part 1 of this paper. The results indicate that plasma treatment is the recommended process for enhancing interface adhesion, roughening the surface, removing oxide on bumps, and avoiding microvoids in WLP.
{"title":"Plasma Applications for Wafer Level Packaging Part 1","authors":"Jack Q. Zhao","doi":"10.1109/ICEPT47577.2019.245794","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245794","url":null,"abstract":"In this paper, typical plasma applications for WLP, such as improving Cu-PI interface adhesion, increasing the PI surface roughness, reducing the current leakage in WLP, the oxide removal from bump surface, avoiding microvoids between Cu seed layer and electric Cu plating layer, TSV cleaning, EMC removal from solder balls on wafer, and wafer-on-frame treatment, are mentioned. Some first-hand data are shown and discussed in the part 1 of this paper. The results indicate that plasma treatment is the recommended process for enhancing interface adhesion, roughening the surface, removing oxide on bumps, and avoiding microvoids in WLP.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"25 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80808526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245115
S. F. Han, X. Tang, D. J. Li, Y. Guan, B. Li, X. Y. Wang, D. Yang
The package of the High-end Relay Protection Chip is Wire Bonding BGA (WBBGA) with 257 inputs/outputs (I/Os). This paper investigated the thermal performance of the High-end Relay Protection Chip using a computational fluid dynamics (CFD) tool. Firstly, according to the initial thermal simulation results, the junction temperature of the package was 115.29 °C appeared on the Relay Protection chip as the environment temperature was 25 C. Then a parametric study was performed to investigate the junction temperatures. We analysed the influence of different parameters on the thermal performance, including Via count, Via coating thickness, Substrate area, Copper coating rate of substrate, Printed Circuit Board (PCB) area, Heat transfer coefficient of epoxy molding compound (EMC) and die attach (DA). Finally, an orthogonal experiment was designed. It’s found that the heat transfer coefficient of DA was the most significant factor on the thermal performance by variance analysis, in addition, an optimal collocation of the package structure and material parameters was obtained by range analysis. The junction temperature of the optimal package was reduced to 95.69 °C by 17%. The results of these simulations give a reasonable indication of how the package would perform in a Relay Protection equipments
{"title":"Thermal simulation and analysis of WBBGA packaging High-end Relay Protection Chip","authors":"S. F. Han, X. Tang, D. J. Li, Y. Guan, B. Li, X. Y. Wang, D. Yang","doi":"10.1109/ICEPT47577.2019.245115","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245115","url":null,"abstract":"The package of the High-end Relay Protection Chip is Wire Bonding BGA (WBBGA) with 257 inputs/outputs (I/Os). This paper investigated the thermal performance of the High-end Relay Protection Chip using a computational fluid dynamics (CFD) tool. Firstly, according to the initial thermal simulation results, the junction temperature of the package was 115.29 °C appeared on the Relay Protection chip as the environment temperature was 25 C. Then a parametric study was performed to investigate the junction temperatures. We analysed the influence of different parameters on the thermal performance, including Via count, Via coating thickness, Substrate area, Copper coating rate of substrate, Printed Circuit Board (PCB) area, Heat transfer coefficient of epoxy molding compound (EMC) and die attach (DA). Finally, an orthogonal experiment was designed. It’s found that the heat transfer coefficient of DA was the most significant factor on the thermal performance by variance analysis, in addition, an optimal collocation of the package structure and material parameters was obtained by range analysis. The junction temperature of the optimal package was reduced to 95.69 °C by 17%. The results of these simulations give a reasonable indication of how the package would perform in a Relay Protection equipments","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"118 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80308552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245260
Zhen-tao Yang, Bo Peng, Ling Gao
During the reliability experiment, the stress will be transferred to the ceramic package through the elastic deformation of the cover plate, because of the large size of the cover plate of the ceramic package for system in package, resulting in an obvious stress concentration phenomenon on the side wall of the package. The reliability test of the ceramic package after sealed was simulated and analyzed by using the finite element method. the material and the structure of cover plate for influence on the package structure reliability was studied , analyzed the influence of different plate structure on the form and distribution of stress of the ceramic package, evaluated the cover plate structure on the influence of the package structure reliability. It provides a reliable theoretical basis for the design of the cover plate of this kind of package. The problems such as porcelain crack of package or device failure caused by cover plate deformation due to unreasonable cover plate design are avoided. Reasonable cover plate structure plays an important role in solving the failure problem in reliability test and improving the reliability of devices.
{"title":"Research on the influence of cover plate on structural reliability of the ceramic package for packaging SIP","authors":"Zhen-tao Yang, Bo Peng, Ling Gao","doi":"10.1109/ICEPT47577.2019.245260","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245260","url":null,"abstract":"During the reliability experiment, the stress will be transferred to the ceramic package through the elastic deformation of the cover plate, because of the large size of the cover plate of the ceramic package for system in package, resulting in an obvious stress concentration phenomenon on the side wall of the package. The reliability test of the ceramic package after sealed was simulated and analyzed by using the finite element method. the material and the structure of cover plate for influence on the package structure reliability was studied , analyzed the influence of different plate structure on the form and distribution of stress of the ceramic package, evaluated the cover plate structure on the influence of the package structure reliability. It provides a reliable theoretical basis for the design of the cover plate of this kind of package. The problems such as porcelain crack of package or device failure caused by cover plate deformation due to unreasonable cover plate design are avoided. Reasonable cover plate structure plays an important role in solving the failure problem in reliability test and improving the reliability of devices.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"44 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82245179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245181
Xiaohui Du, Shuai Liu, Minjie Zhu
This paper reports a batch-mode preparation process of nano glass-particles for high density through glass via application. Compared to the state of the through glass via art, this preparation process allows the electrodes and the packaged structure to be same material, as well as the gap between the packaging electrodes to be less than 1 μm in theory. This process produces nano glass-particles in batches with wet ball grinding technology, and the purity of nano glass-particles can reach to be over 95%. The glass particles are filled in 20 μm electrodes gaps, and a high temperature step reflows the glass particles to a bulk. A high-density silicon column array is hermetically sealed to illustrate application of the process.
{"title":"Research on Preparation Technology of Nano Glass-Particles for High Density TGV Application","authors":"Xiaohui Du, Shuai Liu, Minjie Zhu","doi":"10.1109/ICEPT47577.2019.245181","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245181","url":null,"abstract":"This paper reports a batch-mode preparation process of nano glass-particles for high density through glass via application. Compared to the state of the through glass via art, this preparation process allows the electrodes and the packaged structure to be same material, as well as the gap between the packaging electrodes to be less than 1 μm in theory. This process produces nano glass-particles in batches with wet ball grinding technology, and the purity of nano glass-particles can reach to be over 95%. The glass particles are filled in 20 μm electrodes gaps, and a high temperature step reflows the glass particles to a bulk. A high-density silicon column array is hermetically sealed to illustrate application of the process.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"21 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81370576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
SiC VDMOSFET is a kind of significant power device in the supply system of spacecraft. However, it is very susceptible to space radiation particles causing catastrophic single-event burnout (SEB) occurred. In this paper, we present the 2D numerical simulation results of the SEB failure mechanism, influence factors and the most sensitive region to SEB in SiC VDMOSFET. The results show that when the transient current generated by collision ionization is large enough the SEB will occur. The magnitude of the transient current is related to the incident point, linear energy transfer (LET) and drain voltage. The occurrence of SEB increases with the LET and the drain voltage. The middle of the gate is the most sensitive region to SEB in 4H-SiC VDMOSFET.
SiC VDMOSFET是航天器供电系统中一种重要的功率器件。然而，它很容易受到空间辐射粒子的影响，造成灾难性的单次烧毁(SEB)。本文给出了SiC VDMOSFET中SEB失效机理、影响因素和SEB最敏感区域的二维数值模拟结果。结果表明，当碰撞电离产生的瞬态电流足够大时，就会发生SEB。瞬态电流的大小与入射点、线性能量转移(LET)和漏极电压有关。SEB的发生随着LET和漏极电压的增加而增加。栅极中间是4H-SiC VDMOSFET中对SEB最敏感的区域。
{"title":"Study on single-event burnout of SiC VDMOSFET: failure mechanism and influence factors","authors":"Qiumei Li, Xianping Chen, Houcai Luo, Xian-dong Li, Xiaosong Ma, Luqi Tao, Jing Qian, Chun-Jian Tan","doi":"10.1109/ICEPT47577.2019.245733","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245733","url":null,"abstract":"SiC VDMOSFET is a kind of significant power device in the supply system of spacecraft. However, it is very susceptible to space radiation particles causing catastrophic single-event burnout (SEB) occurred. In this paper, we present the 2D numerical simulation results of the SEB failure mechanism, influence factors and the most sensitive region to SEB in SiC VDMOSFET. The results show that when the transient current generated by collision ionization is large enough the SEB will occur. The magnitude of the transient current is related to the incident point, linear energy transfer (LET) and drain voltage. The occurrence of SEB increases with the LET and the drain voltage. The middle of the gate is the most sensitive region to SEB in 4H-SiC VDMOSFET.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"29 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81398347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To verify whether the results of rapid thermal fatigue of solder joint are consistent with that of the conventional fatigue method, the repeated thermal cycling condition of alternating temperature should be created. In this paper, an experiment, which heat rapidly a metal boss under the single solder joint in 10 seconds by the induced eddy current effect of electromagnetic field and then stop to heat it at the same time in sequence, was implemented. That is to say, the single solder joint above the boss was heated and cooled through heat conduction of the boss where the heat quantity is generated by the electromagnetic induction heating. The condition of rapid thermal cycle was realized by this method. When the single solder joint was subjected to rapid thermal cycling, the interfacial microstructure between the solder ball and Cu substrate was observed and analyzed by SEM. The results indicated that this method supplying rapid heat source by induction heating is feasible to investigate the rapid thermal fatigue behavior of single solder joint. This method can provide more experience for fatigue failure to effectively improve the reliability of the electronic packaging devices.
{"title":"Analysis on the Thermal Fatigue Behavior of Single SnAgCu Solder Joint","authors":"Jibing Chen, Yuandan Xie, Zhanwen He, Nong Wan, Yiping Wu","doi":"10.1109/ICEPT47577.2019.245143","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245143","url":null,"abstract":"To verify whether the results of rapid thermal fatigue of solder joint are consistent with that of the conventional fatigue method, the repeated thermal cycling condition of alternating temperature should be created. In this paper, an experiment, which heat rapidly a metal boss under the single solder joint in 10 seconds by the induced eddy current effect of electromagnetic field and then stop to heat it at the same time in sequence, was implemented. That is to say, the single solder joint above the boss was heated and cooled through heat conduction of the boss where the heat quantity is generated by the electromagnetic induction heating. The condition of rapid thermal cycle was realized by this method. When the single solder joint was subjected to rapid thermal cycling, the interfacial microstructure between the solder ball and Cu substrate was observed and analyzed by SEM. The results indicated that this method supplying rapid heat source by induction heating is feasible to investigate the rapid thermal fatigue behavior of single solder joint. This method can provide more experience for fatigue failure to effectively improve the reliability of the electronic packaging devices.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"8 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82383942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245778
Hangting Shao, Ming Li, A. Hu
In electronic packaging, the interface reaction between solder and substrate directly determines the reliability of the solder joint. An interfacial reaction occurs at the interface between solder and substrate to form an interfacial intermetallic compound (IMC). The growth of the interface IMC has a positive effect on improving the strength of the solder joints, preventing solder diffusion and oxidation, However, if the interface IMC is overmuch, the non-uniform distribution of IMC will adversely affect the performance of the solder joint. Researches have shown that adding nanoparticles to the Sn-Ag-Cu alloy can improve the structure and slow the growth of interfacial IMC, which benefits the performance of the solder. In our work, Sn-3.0Ag-0.5Cu solder was selected as the matrix, and nano-Ag3Sn and Cu3Sn particles were used as additive components. The composite solder paste with different content of nanoparticles was prepared and reflowed. The growth of IMC was observed by Hitachi TM-3000 benchtop scanning electron microscope and FEI Sirion 200 scanning electron microscope (SEM). The morphology of IMC was observed to study the effect of additive nanoparticles on IMC growth. The results show that the addition of 0.3% nano-Ag3Sn and Cu3Sn particles to Sn-3.0Ag-0.5Cu alloy solder can improve the growth of IMC at the solder joint interface, making the IMC morphology of the scallop body shape gentler and more uniform, while adding an excessive amount of Ag3Sn nanoparticles makes the IMC morphology non-uniform.
{"title":"The effect of Ag3Sn and Cu3Sn nanoparticles on the IMC morphology of Sn-3.0Ag-0.5Cu solder","authors":"Hangting Shao, Ming Li, A. Hu","doi":"10.1109/ICEPT47577.2019.245778","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245778","url":null,"abstract":"In electronic packaging, the interface reaction between solder and substrate directly determines the reliability of the solder joint. An interfacial reaction occurs at the interface between solder and substrate to form an interfacial intermetallic compound (IMC). The growth of the interface IMC has a positive effect on improving the strength of the solder joints, preventing solder diffusion and oxidation, However, if the interface IMC is overmuch, the non-uniform distribution of IMC will adversely affect the performance of the solder joint. Researches have shown that adding nanoparticles to the Sn-Ag-Cu alloy can improve the structure and slow the growth of interfacial IMC, which benefits the performance of the solder. In our work, Sn-3.0Ag-0.5Cu solder was selected as the matrix, and nano-Ag3Sn and Cu3Sn particles were used as additive components. The composite solder paste with different content of nanoparticles was prepared and reflowed. The growth of IMC was observed by Hitachi TM-3000 benchtop scanning electron microscope and FEI Sirion 200 scanning electron microscope (SEM). The morphology of IMC was observed to study the effect of additive nanoparticles on IMC growth. The results show that the addition of 0.3% nano-Ag3Sn and Cu3Sn particles to Sn-3.0Ag-0.5Cu alloy solder can improve the growth of IMC at the solder joint interface, making the IMC morphology of the scallop body shape gentler and more uniform, while adding an excessive amount of Ag3Sn nanoparticles makes the IMC morphology non-uniform.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90739491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245774
Xiaorong Wang, Guoqing Yong, Yan Zhang, Yunfei Chen
Due to the rapid development of the miniature microwave module, package-on-package (PoP) configuration is extensively used. The interconnection providing both signal and mechanical support is the significant area to investigate. This paper focuses on the relationship between the arrangement of solder joints and the reliability of vertical interconnection concatenating two low temperature co-fired ceramic (LTCC) substrates at the cooling stage of the reflow soldering. A thermal-mechanical model is established, while the technology of "Element Birth and Death" is applied for simulating the phase change of solders. It is found that the arrangement of solder joints matters in the temperature and thermal stress response of the microwave module. The results show that arranging some solder joints in the middle of substrates and distributing solder joints uniformly are benificial for the reliabilty of interconnection.
{"title":"Reliability and Simulation of composite BGA solder joint connecting LTCC substrates","authors":"Xiaorong Wang, Guoqing Yong, Yan Zhang, Yunfei Chen","doi":"10.1109/ICEPT47577.2019.245774","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245774","url":null,"abstract":"Due to the rapid development of the miniature microwave module, package-on-package (PoP) configuration is extensively used. The interconnection providing both signal and mechanical support is the significant area to investigate. This paper focuses on the relationship between the arrangement of solder joints and the reliability of vertical interconnection concatenating two low temperature co-fired ceramic (LTCC) substrates at the cooling stage of the reflow soldering. A thermal-mechanical model is established, while the technology of \"Element Birth and Death\" is applied for simulating the phase change of solders. It is found that the arrangement of solder joints matters in the temperature and thermal stress response of the microwave module. The results show that arranging some solder joints in the middle of substrates and distributing solder joints uniformly are benificial for the reliabilty of interconnection.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"63 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89217645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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