The heat interface thermal resistance between the dielectric layer (Cu) and the barrier layer (Ti) in the Through-silicon via (TSV) are studied with molecular dynamics (MD) methods. The Cu/Ti interface thermal resistance is temperature dependent. Within the temperature from 293 K to 693 K, the resistance increases as the temperature rises. The increase in temperature causes an increase in atomic vacancy defects at the interface, and the interfacial voids degrade the heat transfer performance. However, when the temperature is higher than 693 K, the vacancies transfer from the interface to the second nearest or further neighbor on the adjacent atomic layers, which reduces the lattice mismatches at high temperatures. Besides, the single Ti atoms cross through the interface to match the Cu lattice vacancy when the temperature is higher than 693 K. As a result, interface thermal resistance decreases as temperature rises from 693 K to 1093 K.
{"title":"Investigation on the Interface Thermal Resistance of Copper-Titanium","authors":"Yixin Xu, F. Zhu, Miaocao Wang, Zilin Lu, Jianxiong Hu, Pengjun Zeng","doi":"10.1109/ICEPT47577.2019.245729","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245729","url":null,"abstract":"The heat interface thermal resistance between the dielectric layer (Cu) and the barrier layer (Ti) in the Through-silicon via (TSV) are studied with molecular dynamics (MD) methods. The Cu/Ti interface thermal resistance is temperature dependent. Within the temperature from 293 K to 693 K, the resistance increases as the temperature rises. The increase in temperature causes an increase in atomic vacancy defects at the interface, and the interfacial voids degrade the heat transfer performance. However, when the temperature is higher than 693 K, the vacancies transfer from the interface to the second nearest or further neighbor on the adjacent atomic layers, which reduces the lattice mismatches at high temperatures. Besides, the single Ti atoms cross through the interface to match the Cu lattice vacancy when the temperature is higher than 693 K. As a result, interface thermal resistance decreases as temperature rises from 693 K to 1093 K.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"47 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86025066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245342
Tao Chen, Jun Zhang, Jing-ming Fei, Bin-bin Zhang, Xiaofeng Sun, Nana Rong
Insulated Gate Bipolar Transistor (IGBT)module is the core device of power electronics which integrates Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and Giant Transistor(GTR)together. It has fast switching speed, reduced saturation voltage, soft-off characteristics and short-circuit resistance. IGBT has been widely used in industrial, aerospace, defense and military industries and rail transit, smart grid and new energy vehicles. As the power density of IGBTs continues to increase, the reliability requirements for IGBT packages are becoming higher and higher, and any failure may cause paralysis of the entire system. The soldering process of the MOSFET and GTR and the substrate is important to the IGBT module packaging. A high quality soldering process can reduce the interface thermal resistance and increase the welding strength and the long-term reliablility. The defects of the solder layer may lead to the increasing of the interface thermal resistance and reducing the product life. At the same time, the defective solder layer will easily cause fatigue failure such as solder layer peeling, chip and substrate crack under the action of ambient temperature cycle and power cycle.This paper is mainly studying the vacuumsoldering process of IGBT module .Using the vacuum soldering process with solder pre-form and formic acid, the low-cavity soldering layer can be achieved. Through material pretreatment, tooling fixture and solder selection, the precise positioning of two sintering and chip, DBC (Direct Bonding Copper) substrate and copper substrate is solved. The control of temperature curve in different temperature zones is optimized, and the vacuum in the soldering process is ensured. Temperature, vacuum rate, vacuum holding time control accuracy, while systematic research on formic acid concentration, activation time, activation temperature control, etc., and non-wetting, soldering, solder overflow, chip substrate Evasion methods such as offset and hole exceeding the standard are proposed. Finally, the high strength, low void rate and position consistency of the soldering interface are realized through the visual inspection, X-ray photography and shear force test to which are shown that the IGBT soldering process has high reliability. (Abstract)
{"title":"Research on Vacuum Soldering Technology of Military IGBT Module","authors":"Tao Chen, Jun Zhang, Jing-ming Fei, Bin-bin Zhang, Xiaofeng Sun, Nana Rong","doi":"10.1109/ICEPT47577.2019.245342","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245342","url":null,"abstract":"Insulated Gate Bipolar Transistor (IGBT)module is the core device of power electronics which integrates Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and Giant Transistor(GTR)together. It has fast switching speed, reduced saturation voltage, soft-off characteristics and short-circuit resistance. IGBT has been widely used in industrial, aerospace, defense and military industries and rail transit, smart grid and new energy vehicles. As the power density of IGBTs continues to increase, the reliability requirements for IGBT packages are becoming higher and higher, and any failure may cause paralysis of the entire system. The soldering process of the MOSFET and GTR and the substrate is important to the IGBT module packaging. A high quality soldering process can reduce the interface thermal resistance and increase the welding strength and the long-term reliablility. The defects of the solder layer may lead to the increasing of the interface thermal resistance and reducing the product life. At the same time, the defective solder layer will easily cause fatigue failure such as solder layer peeling, chip and substrate crack under the action of ambient temperature cycle and power cycle.This paper is mainly studying the vacuumsoldering process of IGBT module .Using the vacuum soldering process with solder pre-form and formic acid, the low-cavity soldering layer can be achieved. Through material pretreatment, tooling fixture and solder selection, the precise positioning of two sintering and chip, DBC (Direct Bonding Copper) substrate and copper substrate is solved. The control of temperature curve in different temperature zones is optimized, and the vacuum in the soldering process is ensured. Temperature, vacuum rate, vacuum holding time control accuracy, while systematic research on formic acid concentration, activation time, activation temperature control, etc., and non-wetting, soldering, solder overflow, chip substrate Evasion methods such as offset and hole exceeding the standard are proposed. Finally, the high strength, low void rate and position consistency of the soldering interface are realized through the visual inspection, X-ray photography and shear force test to which are shown that the IGBT soldering process has high reliability. (Abstract)","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"25 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77849968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245281
Shuai Zhao, F. Qin, Mengke Yang, Min Xiang, Daquan Yu
Wafer warpage has been an important problem to affect the manufacturability and reliability in Wafer Level Chip Scale package (WLCSP). In this paper, wafer warpage evolution is studied for a six-side molded WLCSP using finite element model. A method to mimic the actual fabricating process is presented based on the "Element birth & death" and "Restart" technology. Key process such as topside molding, backside grinding and backside molding is taken into account and the results match with the experiment well. The effect of the parameters and structural parameters on wafer warpage characteristics is analyzed.
{"title":"Study on warpage evolution for six-side molded WLCSP based on finite element analysis","authors":"Shuai Zhao, F. Qin, Mengke Yang, Min Xiang, Daquan Yu","doi":"10.1109/ICEPT47577.2019.245281","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245281","url":null,"abstract":"Wafer warpage has been an important problem to affect the manufacturability and reliability in Wafer Level Chip Scale package (WLCSP). In this paper, wafer warpage evolution is studied for a six-side molded WLCSP using finite element model. A method to mimic the actual fabricating process is presented based on the \"Element birth & death\" and \"Restart\" technology. Key process such as topside molding, backside grinding and backside molding is taken into account and the results match with the experiment well. The effect of the parameters and structural parameters on wafer warpage characteristics is analyzed.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"86 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73176760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245247
Jianwen Zhou, Gang Li, Pengli Zhu, R. Sun, C. Wong
Sintered silver has been used as an interconnect material for power electronic components in recent years. In the early days of development, micron-sized Ag particles were used for the silver conductive paste, however, high temperature and high pressures of up to 40 MPa were needed to achieve high performance sintered joints, which may damage the electrical component.Therefore,low pressure sintering using Ag nanoparticles has received great interest. In our work, we evaluated the properties of the silver nanoparticle conductive paste as a low-temperature, low-pressure interconnect material. Shear strength test showed that the silver paste with 60%wt Ag loading sintered under 10MPa for 20 min can achieve the best result among 10min, 20min, 30min and 40min.Moreover, as the sintering pressure increases, Cu-Cu joints clearly increased. Silver content is also an important factor affecting the shear strength. When we increase the silver loading from 60%wt to 80%wt, shear strength increases simultaneous. Shear test results show that a high shear strength of 57MPa can be achieved for the 80wt% Ag loading under 10MP at 300° C. which indicates that our silver nanoparticle conductive paste has excellent mechanical properties.
{"title":"Study on conductive paste of silver particles for power semiconductor devices package","authors":"Jianwen Zhou, Gang Li, Pengli Zhu, R. Sun, C. Wong","doi":"10.1109/ICEPT47577.2019.245247","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245247","url":null,"abstract":"Sintered silver has been used as an interconnect material for power electronic components in recent years. In the early days of development, micron-sized Ag particles were used for the silver conductive paste, however, high temperature and high pressures of up to 40 MPa were needed to achieve high performance sintered joints, which may damage the electrical component.Therefore,low pressure sintering using Ag nanoparticles has received great interest. In our work, we evaluated the properties of the silver nanoparticle conductive paste as a low-temperature, low-pressure interconnect material. Shear strength test showed that the silver paste with 60%wt Ag loading sintered under 10MPa for 20 min can achieve the best result among 10min, 20min, 30min and 40min.Moreover, as the sintering pressure increases, Cu-Cu joints clearly increased. Silver content is also an important factor affecting the shear strength. When we increase the silver loading from 60%wt to 80%wt, shear strength increases simultaneous. Shear test results show that a high shear strength of 57MPa can be achieved for the 80wt% Ag loading under 10MP at 300° C. which indicates that our silver nanoparticle conductive paste has excellent mechanical properties.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"14 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87547974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245280
Yiyi Ma, Jefferson Talledo, J. Luan
The essential functions provided by electronic packaging are, among many others, mechanical protection of the fragile electrical device subjected to harsh environmental and operational loads, electrical connection and isolation for electronic components within a system, and thermal dissipation paths for the functioning heat generating silicon chip. In the past, these functions had normally been achieved by traditional lead frame based packages such as SOIC, DIP, QFP and QFN. In many cases, while addressing reliability and thermal issues a traditional lead frame based package can easily consume 4-5 times more space than the active device it contains, resulting in a remarkable waste of the precious package footprint. In this regard, BGA (Ball Grid Array) technology is a more desirable packaging alternative due to its intrinsic size reduction capability and highly favorable electrical performance. Nevertheless, it is well known that the board level ATC (Accelerated Thermal Cycling) test performance of BGA packages is worse than its lead frame counterparts since its interconnects are much more rigid. Therefore, to ensure the reliability and durability of its solder joints is a critical task when developing a BGA package for automotive applications, where safety is extremely demanding.This paper initially investigates the solder joint reliability of the FBGA package for automotive applications during board level ATC test through Finite Element Analysis (FEA). Experiments were then carried out to assess the accuracy of the FEA model. It is found that the predictions made by the FEA simulation do not match the actual test result. The failure pattern suggests that it could be related to the excessive package warpage during testing. Viscoelastic behavior of the polymer based materials was then characterized and taken into account. The updated FEA model is found to have much better simulation result. To validate this approach, packages with standard and low CTE core materials were built and tested. Good agreement is found between the simulation and testing results. Significant improvement of the package fatigue life is observed with low CTE substrate core materials.
{"title":"Thermal Cycling Durability Assessment and Enhancement of FBGA Package for Automotive Applications","authors":"Yiyi Ma, Jefferson Talledo, J. Luan","doi":"10.1109/ICEPT47577.2019.245280","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245280","url":null,"abstract":"The essential functions provided by electronic packaging are, among many others, mechanical protection of the fragile electrical device subjected to harsh environmental and operational loads, electrical connection and isolation for electronic components within a system, and thermal dissipation paths for the functioning heat generating silicon chip. In the past, these functions had normally been achieved by traditional lead frame based packages such as SOIC, DIP, QFP and QFN. In many cases, while addressing reliability and thermal issues a traditional lead frame based package can easily consume 4-5 times more space than the active device it contains, resulting in a remarkable waste of the precious package footprint. In this regard, BGA (Ball Grid Array) technology is a more desirable packaging alternative due to its intrinsic size reduction capability and highly favorable electrical performance. Nevertheless, it is well known that the board level ATC (Accelerated Thermal Cycling) test performance of BGA packages is worse than its lead frame counterparts since its interconnects are much more rigid. Therefore, to ensure the reliability and durability of its solder joints is a critical task when developing a BGA package for automotive applications, where safety is extremely demanding.This paper initially investigates the solder joint reliability of the FBGA package for automotive applications during board level ATC test through Finite Element Analysis (FEA). Experiments were then carried out to assess the accuracy of the FEA model. It is found that the predictions made by the FEA simulation do not match the actual test result. The failure pattern suggests that it could be related to the excessive package warpage during testing. Viscoelastic behavior of the polymer based materials was then characterized and taken into account. The updated FEA model is found to have much better simulation result. To validate this approach, packages with standard and low CTE core materials were built and tested. Good agreement is found between the simulation and testing results. Significant improvement of the package fatigue life is observed with low CTE substrate core materials.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"4 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88007344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245186
Ying Yang
In current trend of miniaturization and integration of electronic devices, surface mount technology process puts higher demands on the demands on the flatness of printed circuit boards. It is a very important topic to minimize the warpage of PCB by optimizing process technology. This article discusses the main causes of PCB warpage and presents a failure analysis case for PCB warpage.
{"title":"Discussion and failure analysis of PCB warpage","authors":"Ying Yang","doi":"10.1109/ICEPT47577.2019.245186","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245186","url":null,"abstract":"In current trend of miniaturization and integration of electronic devices, surface mount technology process puts higher demands on the demands on the flatness of printed circuit boards. It is a very important topic to minimize the warpage of PCB by optimizing process technology. This article discusses the main causes of PCB warpage and presents a failure analysis case for PCB warpage.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"16 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86539855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245323
Yue Gao, Chuantong Chen, S. Nagao, K. Suganuma, A. Bahman, F. Iannuzzo
A Cu particles paste was developed as a candidate of die attach materials for next generation power devices. The evaluation including thermal shock and power cycling test were performed on SiC-DBC die-attach structure to test the reliability of sintered Cu joints. The thermal shock reliability of SiC die-attached on a DBC substrate was carried out from -50 °C to 250 °C in the ambient atmosphere. SiC MOSFETs bonded by the Cu paste were evaluated by power cycle test from 25 °C to 200 °C. In both test condition, the sintered Cu joints showed good stability. The shear strength increased with the thermal shock cycles increased, which can be attributed to Cu oxidation during test. The power cycle test also showed no obvious deterioration occurred.
{"title":"Reliability analysis of sintered Cu joints under power cycle condition","authors":"Yue Gao, Chuantong Chen, S. Nagao, K. Suganuma, A. Bahman, F. Iannuzzo","doi":"10.1109/ICEPT47577.2019.245323","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245323","url":null,"abstract":"A Cu particles paste was developed as a candidate of die attach materials for next generation power devices. The evaluation including thermal shock and power cycling test were performed on SiC-DBC die-attach structure to test the reliability of sintered Cu joints. The thermal shock reliability of SiC die-attached on a DBC substrate was carried out from -50 °C to 250 °C in the ambient atmosphere. SiC MOSFETs bonded by the Cu paste were evaluated by power cycle test from 25 °C to 200 °C. In both test condition, the sintered Cu joints showed good stability. The shear strength increased with the thermal shock cycles increased, which can be attributed to Cu oxidation during test. The power cycle test also showed no obvious deterioration occurred.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"384 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83467327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245748
Yunheng Sun, Yufeng Jin, Han Cai, Shengli Ma, Liu-lin Hu, Shuwei He
In this paper, we present a TSV interposer integrated X-band microstrip filter. It designed as working at X band with an insertion loss (IL) of 2.2dB, measuring 2.8mm×3.7mm in size. With processed sample, the measured bandwidth (BW) is about 2.33GHz, the passband insertion loss is about 2.2dB.
{"title":"Design, fabrication and measurement of TSV interposer integrated X-band microstrip filter","authors":"Yunheng Sun, Yufeng Jin, Han Cai, Shengli Ma, Liu-lin Hu, Shuwei He","doi":"10.1109/ICEPT47577.2019.245748","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245748","url":null,"abstract":"In this paper, we present a TSV interposer integrated X-band microstrip filter. It designed as working at X band with an insertion loss (IL) of 2.2dB, measuring 2.8mm×3.7mm in size. With processed sample, the measured bandwidth (BW) is about 2.33GHz, the passband insertion loss is about 2.2dB.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"14 3 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83393079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245315
Rui Cao, Fengwei Dai
With the development of 3D SIP, TSV interposers are more and more widely used, and its reliability receives broader concern. As CTEs of copper and silicon are different in TSV interposer, it is easy to be affected by thermal stress and lead to failure in the process of processing and use. Therefore, an annealing treatment is usually conducted after electroplating to release stress. Different sizes and distributions of TSV produce different stress effects in the production process. In this paper, an interposer with low opening rate and large size TSV ， frequently cracks after annealing, is simulated and analyzed.
{"title":"The failure analysis of 30um*200um TSV interposer","authors":"Rui Cao, Fengwei Dai","doi":"10.1109/ICEPT47577.2019.245315","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245315","url":null,"abstract":"With the development of 3D SIP, TSV interposers are more and more widely used, and its reliability receives broader concern. As CTEs of copper and silicon are different in TSV interposer, it is easy to be affected by thermal stress and lead to failure in the process of processing and use. Therefore, an annealing treatment is usually conducted after electroplating to release stress. Different sizes and distributions of TSV produce different stress effects in the production process. In this paper, an interposer with low opening rate and large size TSV ， frequently cracks after annealing, is simulated and analyzed.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"10 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90636281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To solve the problems of high cost and agglomeration of nanoparticle paste, a novel and inexpensive Cu micro-nano composite paste was prepared and demonstrated for low temperature Cu-Cu bonding. The composite paste was mainly composed of micro particles (1 μm), nanoparticles (10 nm), and organic solvents, and the micron particles as the nucleation sites were coated by the prepared nanoparticles. Moreover, the influences of sintering temperature on the shear strength and microstructure of the bonded joints were investigated. Consequently, the shear strengths of the bonded joints are more than 30 MPa at the sintering temperature of 225°C, 250°C, and 275°C, respectively. Furthermore, their fracture surfaces show significant ductile deformation, and the bonded interfaces between the composite particles and substrates achieve the high purity metallurgical interconnection without the cracks.
{"title":"Facile Preparation of Cu Micro-Nano Composite Particle Paste for Low Temperature Bonding","authors":"Yun Mou, Yang Peng, Junjie Li, Jiaxin Liu, Qinglei Sun, Mingxiang Chen","doi":"10.1109/ICEPT47577.2019.245766","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245766","url":null,"abstract":"To solve the problems of high cost and agglomeration of nanoparticle paste, a novel and inexpensive Cu micro-nano composite paste was prepared and demonstrated for low temperature Cu-Cu bonding. The composite paste was mainly composed of micro particles (1 μm), nanoparticles (10 nm), and organic solvents, and the micron particles as the nucleation sites were coated by the prepared nanoparticles. Moreover, the influences of sintering temperature on the shear strength and microstructure of the bonded joints were investigated. Consequently, the shear strengths of the bonded joints are more than 30 MPa at the sintering temperature of 225°C, 250°C, and 275°C, respectively. Furthermore, their fracture surfaces show significant ductile deformation, and the bonded interfaces between the composite particles and substrates achieve the high purity metallurgical interconnection without the cracks.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"42 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85346465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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