Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185321
Ofir Sharoni, Yael Sufrin, Avi Cohen, T. Scheruebl, R. Seltmann, A. Samy, T. Thamm
Advanced process control in lithography and overall patterning is of tremendous importance for advanced semiconductor Fabs to ensure enhanced chip performance and yield. The final patterning result and subsequent yield are dependent upon many process parameters such as lithography processes, exposure tool performance, etch process, and CMP etc. To control these effects, various knobs, e.g. on the scanner for both wafer inter- and intra-field process control, have been introduced recently, including sophisticated inline metrology. In this holistic lithographic concept, the metrology is supported by simulation and by inline data. Additionally, offline data such as the mask critical dimension uniformity (CDU) data, can be added as a mask wafer interaction, also significantly contributing to wafer intra-field performance. The metrology algorithm now looks for locations where the simulation finds the weakest process features due to strong deviations of focus, dose, stage dynamics or other input parameters. These concepts are optimized to find sites where the process may break. Our concept of “excursion preventions” is a complementary approach. It proactively concentrates on the task to minimize the distributions of critical input parameters as much as possible, independent of a certain pre-defined specification for whether that parameter is met or not. In this paper, we will describe this concept by improving wafer intra-field CDU using CD Correction (CDC) by mask tuning (based on wafer intra-filed data). Mask tuning by the ForTune system uses ultra-short pulse laser technology to change the mask transmission locally, subsequently improving CDU on the wafer (CDC). To ensure safe patterning with a large enough process window without any negative yield or reliability impact, our concept looks for the tail of the final CD distribution instead of traditional 3 sigma numbers. By using a calibrated 3-D resist model, we simulate the pattern result under all permutations of input parameter distributions like dose, focus and mask CDU. As a result of the simulation, we get thousands of CD-results. The tail of that CD distribution still needs to be larger than the minimum CD needed for a safe etch transfer. Secondly, we will show in detail how the pro-active optimization of wafer intra-field CDU by mask tuning using the ForTune CDC process will give us more margin patterning and process stability over any other excursion process (e.g. focus deviations). Furthermore, we will present the simulated yield improvement based on the weak points (hot spots) improvement.
{"title":"Excursion Prevention Strategy to Increase Chip Performance by Wafer Intra-Field CD Control Using Photomask Tuning","authors":"Ofir Sharoni, Yael Sufrin, Avi Cohen, T. Scheruebl, R. Seltmann, A. Samy, T. Thamm","doi":"10.1109/ASMC49169.2020.9185321","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185321","url":null,"abstract":"Advanced process control in lithography and overall patterning is of tremendous importance for advanced semiconductor Fabs to ensure enhanced chip performance and yield. The final patterning result and subsequent yield are dependent upon many process parameters such as lithography processes, exposure tool performance, etch process, and CMP etc. To control these effects, various knobs, e.g. on the scanner for both wafer inter- and intra-field process control, have been introduced recently, including sophisticated inline metrology. In this holistic lithographic concept, the metrology is supported by simulation and by inline data. Additionally, offline data such as the mask critical dimension uniformity (CDU) data, can be added as a mask wafer interaction, also significantly contributing to wafer intra-field performance. The metrology algorithm now looks for locations where the simulation finds the weakest process features due to strong deviations of focus, dose, stage dynamics or other input parameters. These concepts are optimized to find sites where the process may break. Our concept of “excursion preventions” is a complementary approach. It proactively concentrates on the task to minimize the distributions of critical input parameters as much as possible, independent of a certain pre-defined specification for whether that parameter is met or not. In this paper, we will describe this concept by improving wafer intra-field CDU using CD Correction (CDC) by mask tuning (based on wafer intra-filed data). Mask tuning by the ForTune system uses ultra-short pulse laser technology to change the mask transmission locally, subsequently improving CDU on the wafer (CDC). To ensure safe patterning with a large enough process window without any negative yield or reliability impact, our concept looks for the tail of the final CD distribution instead of traditional 3 sigma numbers. By using a calibrated 3-D resist model, we simulate the pattern result under all permutations of input parameter distributions like dose, focus and mask CDU. As a result of the simulation, we get thousands of CD-results. The tail of that CD distribution still needs to be larger than the minimum CD needed for a safe etch transfer. Secondly, we will show in detail how the pro-active optimization of wafer intra-field CDU by mask tuning using the ForTune CDC process will give us more margin patterning and process stability over any other excursion process (e.g. focus deviations). Furthermore, we will present the simulated yield improvement based on the weak points (hot spots) improvement.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"19 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84665540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185236
Jessica Gruss-Gifford, V. Mehta, Oscar van der Straten, G. Rodriguez, M. Lippitt, D. Canaperi
This paper presents a multi-step process to improve the stability of plasma ignition of a magnetic target in a multi-cathode physical vapor deposition (PVD) system. Most target materials in the system have no issues igniting a stable plasma. The material in question is a material for which it is much more difficult to ignite a reliable plasma because it is a more complex target made of different compounds, therefore this target will be affected by grain size, impurities, and other factors from its manufacturing, therefore there are more ignition faults and retries than with other conventional targets using the same recipe settings. It was found that ignition retries and faults can be improved by implementing sequence start cleans, high pressure ignition using the sputter on shield, and/or by using a higher wattage power supply to ignite the plasma with the ion gauge on. Each method was shown to decrease the number of retries and faults and can be used on PVD systems with targets which are difficult to ignite. Any combination of these solutions should result in improvement of up to 50% reduction in ignition faults.
{"title":"Method for improving stability of plasma ignition in a multi-cathode magnetron PVD system","authors":"Jessica Gruss-Gifford, V. Mehta, Oscar van der Straten, G. Rodriguez, M. Lippitt, D. Canaperi","doi":"10.1109/ASMC49169.2020.9185236","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185236","url":null,"abstract":"This paper presents a multi-step process to improve the stability of plasma ignition of a magnetic target in a multi-cathode physical vapor deposition (PVD) system. Most target materials in the system have no issues igniting a stable plasma. The material in question is a material for which it is much more difficult to ignite a reliable plasma because it is a more complex target made of different compounds, therefore this target will be affected by grain size, impurities, and other factors from its manufacturing, therefore there are more ignition faults and retries than with other conventional targets using the same recipe settings. It was found that ignition retries and faults can be improved by implementing sequence start cleans, high pressure ignition using the sputter on shield, and/or by using a higher wattage power supply to ignite the plasma with the ion gauge on. Each method was shown to decrease the number of retries and faults and can be used on PVD systems with targets which are difficult to ignite. Any combination of these solutions should result in improvement of up to 50% reduction in ignition faults.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"67 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83859052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185217
B. Egan, H. Kim, R. Solan
Controlling defectivity levels after the CMP process is critical for yield enhancement. CMP tools are equipped with an in-situ cleaning module to remove polishing byproducts, residues, and flakes. After tungsten contact CMP, metallic flakes and films can cause leakage paths between contacts. They are detrimental to final device yield, and their impact increases as the transistor nodes shrink. This paper explores the formation mechanisms of different types of tungsten flake defects and suggests methods to eliminate them from the wafer surface. The interaction between the in-situ cleaner and wafer will be examined in order to better understand the source and formation of defects caught after CMP. Keyword: Tungsten CMP, CMP in-situ Cleaning, Dryer, Brushes, Flakes
{"title":"Formation and Removal of Tungsten Flake and Metallic Film Defects in Tungsten Contact CMP","authors":"B. Egan, H. Kim, R. Solan","doi":"10.1109/ASMC49169.2020.9185217","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185217","url":null,"abstract":"Controlling defectivity levels after the CMP process is critical for yield enhancement. CMP tools are equipped with an in-situ cleaning module to remove polishing byproducts, residues, and flakes. After tungsten contact CMP, metallic flakes and films can cause leakage paths between contacts. They are detrimental to final device yield, and their impact increases as the transistor nodes shrink. This paper explores the formation mechanisms of different types of tungsten flake defects and suggests methods to eliminate them from the wafer surface. The interaction between the in-situ cleaner and wafer will be examined in order to better understand the source and formation of defects caught after CMP. Keyword: Tungsten CMP, CMP in-situ Cleaning, Dryer, Brushes, Flakes","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"29 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86727385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185226
D. Kong, D. Schmidt, M. Breton, A. A. de la peña, J. Frougier, A. Greene, Jingyun Zhang, V. Basker, N. Loubet, I. Ahsan, A. Cepler, M. Klare, Marjorie Cheng, R. Koret, I. Turovets
The methodology of measuring the lateral etch, or indentation, of SiGe nanosheets by using optical scatterometry, x-ray fluorescence, and machine learning algorithms is presented and discussed. Stacked nanosheet device structures were fabricated with different etch conditions in order to induce variations in the indent. It was found that both scatterometry in conjunction with Spectral Interferometry and novel interpretation algorithms as well as TEM calibrated LE-XRF are suitable techniques to quantify the indent. Machine learning algorithms enabled an additional solution path by combining LE-XRF data with scatterometry spectra therefore avoiding the need for a full optical model.
{"title":"Development of SiGe Indentation Process Control to Enable Stacked Nanosheet FET Technology","authors":"D. Kong, D. Schmidt, M. Breton, A. A. de la peña, J. Frougier, A. Greene, Jingyun Zhang, V. Basker, N. Loubet, I. Ahsan, A. Cepler, M. Klare, Marjorie Cheng, R. Koret, I. Turovets","doi":"10.1109/ASMC49169.2020.9185226","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185226","url":null,"abstract":"The methodology of measuring the lateral etch, or indentation, of SiGe nanosheets by using optical scatterometry, x-ray fluorescence, and machine learning algorithms is presented and discussed. Stacked nanosheet device structures were fabricated with different etch conditions in order to induce variations in the indent. It was found that both scatterometry in conjunction with Spectral Interferometry and novel interpretation algorithms as well as TEM calibrated LE-XRF are suitable techniques to quantify the indent. Machine learning algorithms enabled an additional solution path by combining LE-XRF data with scatterometry spectra therefore avoiding the need for a full optical model.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"137 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89307020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185396
Y. Hagio, K. Kasa, Sho Kawadahara, Manabu Takakuwa, Yosuke Takahata, Katsuya Kato, A. Nakae
In this paper, we demonstrate methodology of mark design for semiconductor device based on simulations, measurements and verification. We compared overlay performance of conventional overlay targets, as well as grating-over-grating imaging targets utilizing Moiré effect. Moiré target showed better accuracy, process robustness and precision with improved measurement technology.
{"title":"Overlay improvement for semiconductor manufacturing using Moiré effect","authors":"Y. Hagio, K. Kasa, Sho Kawadahara, Manabu Takakuwa, Yosuke Takahata, Katsuya Kato, A. Nakae","doi":"10.1109/ASMC49169.2020.9185396","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185396","url":null,"abstract":"In this paper, we demonstrate methodology of mark design for semiconductor device based on simulations, measurements and verification. We compared overlay performance of conventional overlay targets, as well as grating-over-grating imaging targets utilizing Moiré effect. Moiré target showed better accuracy, process robustness and precision with improved measurement technology.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"91 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75307178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185222
J. Trujillo-Sevilla, J. Ramos-Rodríguez, J. Gaudestad
In this paper we introduce a new metrology technique for measuring wafer geometry on silicon wafers. Wave Front Phase Imaging (WFPI) has high lateral resolution and is sensitive enough to measure roughness on a silicon wafer by simply acquiring a single image snapshot of the entire wafer. WFPI is achieved by measuring the reflected light intensity from monochromatic uncoherent light at two different optical planes along the optical path with the same field of view. We show that the lateral resolution in the current system is 24μm though it can be pushed to less than 5μm by simply adding more pixels to the image sensor. Also, we show that the amplitude, or Z-height resolution limit, is 0. 3nm. A 2-inch wafer was measured while resting flat on a sample holder and the nanotopography and roughness was revealed by applying a Butterworth high pass filter to the global topography data using a spatial cutoff frequency of 440μm. The same 2-inch wafer was also placed on a simulated robotic wafer handler arm, and we show that even if gravity was causing extra bow on the wafer, the same roughness and nanotopography was still being revealed at the same resolution after the same high pass filter was applied to the global wafer geometry data.
{"title":"Roughness and nanotopography measurement of a Silicon Wafer using Wave Front Phase Imaging : High speed single image snapshot of entire wafer producing sub nm topography data","authors":"J. Trujillo-Sevilla, J. Ramos-Rodríguez, J. Gaudestad","doi":"10.1109/ASMC49169.2020.9185222","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185222","url":null,"abstract":"In this paper we introduce a new metrology technique for measuring wafer geometry on silicon wafers. Wave Front Phase Imaging (WFPI) has high lateral resolution and is sensitive enough to measure roughness on a silicon wafer by simply acquiring a single image snapshot of the entire wafer. WFPI is achieved by measuring the reflected light intensity from monochromatic uncoherent light at two different optical planes along the optical path with the same field of view. We show that the lateral resolution in the current system is 24μm though it can be pushed to less than 5μm by simply adding more pixels to the image sensor. Also, we show that the amplitude, or Z-height resolution limit, is 0. 3nm. A 2-inch wafer was measured while resting flat on a sample holder and the nanotopography and roughness was revealed by applying a Butterworth high pass filter to the global topography data using a spatial cutoff frequency of 440μm. The same 2-inch wafer was also placed on a simulated robotic wafer handler arm, and we show that even if gravity was causing extra bow on the wafer, the same roughness and nanotopography was still being revealed at the same resolution after the same high pass filter was applied to the global wafer geometry data.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"58 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84560797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185196
A. Striegler, F. Flach, T. Lindner, C. Chee, P. Jain, Madhan Kanniyappan
Throughout high volume semiconductor manufacturing processing, many factors influence wafer defectivity, including the backside bevel shape of the wafer. This paper shows the relationship between the critical edge on the backside bevel of an incoming wafer and the specific defect level during manufacturing. A new methodology to characterize this critical backside bevel shape is presented. This characterization utilizes the PWG™ patterned wafer geometry metrology system and a known curvature metric (ZDD) [1]. The novelty of the methodology is the extension of the measurement radius closer to the wafer apex.
{"title":"Advanced wafer backside bevel characterization using a geometry measurement","authors":"A. Striegler, F. Flach, T. Lindner, C. Chee, P. Jain, Madhan Kanniyappan","doi":"10.1109/ASMC49169.2020.9185196","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185196","url":null,"abstract":"Throughout high volume semiconductor manufacturing processing, many factors influence wafer defectivity, including the backside bevel shape of the wafer. This paper shows the relationship between the critical edge on the backside bevel of an incoming wafer and the specific defect level during manufacturing. A new methodology to characterize this critical backside bevel shape is presented. This characterization utilizes the PWG™ patterned wafer geometry metrology system and a known curvature metric (ZDD) [1]. The novelty of the methodology is the extension of the measurement radius closer to the wafer apex.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"46 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85986429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.1109/ASMC.2017.7969227
C. Melvin, B. Roelfs
{"title":"Simultaneous front and back side Cu metallization on power chips: DP: Discrete and power devices or ET/ID: Enabling technologies and innovative devices","authors":"C. Melvin, B. Roelfs","doi":"10.1109/ASMC.2017.7969227","DOIUrl":"https://doi.org/10.1109/ASMC.2017.7969227","url":null,"abstract":"","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"11 1","pages":"189-191"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91396703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-03DOI: 10.1109/ASMC.2015.7164465
R. Preetham
The application of correcting small temperature non-uniformity on Silicon wafers using local irradiation with spatially scanning laser beams was analyzed. The objective of the study was to understand the specifications of such a laser beam to elevate the temperature of a wafer locally by 1 to 5°C. A detailed analytical model has been developed for predicting power level, exposure time, scanning speed, and the beam characteristics. The model has been derived by solving the three dimensional transient heat equation using Green's function approach. Various wafer characteristics, such as the surface reflectivity, material absorption coefficient, and thermal properties have been built into the formulation as parameters, so that several what-if scenarios can be evaluated with ease and accuracy. Existing analytical methods in literature for prediction of laser irradiated substrate temperatures assume infinite thickness of the substrate. In this study, it has been found that this approximation could result in significant errors particularly for the present application of interest, where the wafer thickness is finite and the focus is on relatively small local temperature rise in short exposure durations. Numerical models were also developed to mimic some particular cases using a commercial finite volume method solver. The numerical and analytical results show an excellent agreement. The analytical model allows for a more diverse range of variables than the finite volume numerical models.
{"title":"Local wafer temperature non-uniformity correction with laser irradiation","authors":"R. Preetham","doi":"10.1109/ASMC.2015.7164465","DOIUrl":"https://doi.org/10.1109/ASMC.2015.7164465","url":null,"abstract":"The application of correcting small temperature non-uniformity on Silicon wafers using local irradiation with spatially scanning laser beams was analyzed. The objective of the study was to understand the specifications of such a laser beam to elevate the temperature of a wafer locally by 1 to 5°C. A detailed analytical model has been developed for predicting power level, exposure time, scanning speed, and the beam characteristics. The model has been derived by solving the three dimensional transient heat equation using Green's function approach. Various wafer characteristics, such as the surface reflectivity, material absorption coefficient, and thermal properties have been built into the formulation as parameters, so that several what-if scenarios can be evaluated with ease and accuracy. Existing analytical methods in literature for prediction of laser irradiated substrate temperatures assume infinite thickness of the substrate. In this study, it has been found that this approximation could result in significant errors particularly for the present application of interest, where the wafer thickness is finite and the focus is on relatively small local temperature rise in short exposure durations. Numerical models were also developed to mimic some particular cases using a commercial finite volume method solver. The numerical and analytical results show an excellent agreement. The analytical model allows for a more diverse range of variables than the finite volume numerical models.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"47 1","pages":"179-184"},"PeriodicalIF":0.0,"publicationDate":"2015-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86865861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-11DOI: 10.1109/ASMC.2007.4595693
P. V. D. Meulen
Fabs need enhanced flexibility to manufacture smaller lots of wafers to reduce cycle time, inventory and WIP, while maintaining equipment throughput, avoiding cross-contamination and ensuring process integrity and yields. Current equipment has increasing difficulty meeting those demands. This paper describes various factors that could lead to optimized choices for the quantity of wafers in a lot of size smaller than 25 wafers, and shows the potential for decreases in cycle time associated with various equipment configurations and wafer lot sizes.
{"title":"Linear Semiconductor Manufacturing Logistics and the Impact on Cycle Time","authors":"P. V. D. Meulen","doi":"10.1109/ASMC.2007.4595693","DOIUrl":"https://doi.org/10.1109/ASMC.2007.4595693","url":null,"abstract":"Fabs need enhanced flexibility to manufacture smaller lots of wafers to reduce cycle time, inventory and WIP, while maintaining equipment throughput, avoiding cross-contamination and ensuring process integrity and yields. Current equipment has increasing difficulty meeting those demands. This paper describes various factors that could lead to optimized choices for the quantity of wafers in a lot of size smaller than 25 wafers, and shows the potential for decreases in cycle time associated with various equipment configurations and wafer lot sizes.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"5 1","pages":"111-116"},"PeriodicalIF":0.0,"publicationDate":"2007-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84616672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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