Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185390
Michael Meng, Albert Li, Andrew Zhang, Leeming Tu, Haydn Zhou, J. Mi, Xi Zou
Metrology measurements of the top copper contact in the main chip area is critical to predict the subsequent electrical performance in advanced 3D NAND technology nodes. Conventional CDSEM is used in the determination of top copper CD while the accurate measurement of copper depth remains challenging. In this paper, we propose a new approach that successfully explored the use of machine learning to combine the advantages of optical Critical Dimension (OCD) and picosecond ultrasonic technology (PULSE™) for high volume manufacturing (HVM) measurements in the main chip area. Results demonstrate that by using machine learning, we were able to combine the PULSE reference with cross-section microscopy results to successfully train the OCD data set. OCD measurements are rapid at <1s/site and meets the HVM need for extensive sampling and allows for in-line process control of the top copper contact height. This approach also opens the possibilities for application of machine learning for in-line 3D NAND monitoring process control by combining multiple methods and exploiting the full potential of each of these technologies.
{"title":"The Adoption of Machine Learning in the Measurement of Copper Contact on the Main Chip in Advanced 3D NAND Technology Nodes","authors":"Michael Meng, Albert Li, Andrew Zhang, Leeming Tu, Haydn Zhou, J. Mi, Xi Zou","doi":"10.1109/ASMC49169.2020.9185390","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185390","url":null,"abstract":"Metrology measurements of the top copper contact in the main chip area is critical to predict the subsequent electrical performance in advanced 3D NAND technology nodes. Conventional CDSEM is used in the determination of top copper CD while the accurate measurement of copper depth remains challenging. In this paper, we propose a new approach that successfully explored the use of machine learning to combine the advantages of optical Critical Dimension (OCD) and picosecond ultrasonic technology (PULSE™) for high volume manufacturing (HVM) measurements in the main chip area. Results demonstrate that by using machine learning, we were able to combine the PULSE reference with cross-section microscopy results to successfully train the OCD data set. OCD measurements are rapid at <1s/site and meets the HVM need for extensive sampling and allows for in-line process control of the top copper contact height. This approach also opens the possibilities for application of machine learning for in-line 3D NAND monitoring process control by combining multiple methods and exploiting the full potential of each of these technologies.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"78 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86889073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185322
Kevin Brew, R. Conti, I. Saraf, Cheng-Wei Cheng, Cheng-Wei Cheng, William Lee, Yin Xu, N. Saulnier, T. Masuda, T. Jimbo
Oxidation of phase-change memory (PCM) materials (e.g. $Ge_{2}Sb_{2}Te_{5}$, GST) has been shown to decrease crystallization temperature and impact film composition, thus impacting analog switching behavior [1], [2]. PCM mushroom-cell devices were engineered on a 14 nm backend test vehicle to compare the electrical switching performance of in-situ and ex-situ capped GST 225. To mitigate the electrical effects from varying top electrode processes between tools, in-situ devices were fabricated with a Ti-TiN cap on GST before exposure to air. The in-situ cap is reduced to a minimal thickness to prevent oxidation of the Ti adhesion layer and the remainder of TiN was deposited matching to the ex-situ top electrode process. TEM of in-situ capped samples were found to have less GST undercut from patterning and have less reduction of the contact area between the GST and top electrode. SET and RESET programming of in-situ capped PCM devices show comparable SET and RESET state resistances to ex-situ processed PCM devices. Current-voltage measurements show that the in-situ PCM can have slightly lower voltage threshold switching but achieves a significantly higher current after threshold switching. The increased current for in-situ capped PCM results in higher power consumption with fixed voltage programming.
{"title":"Effect of In-situ Capping on Phase Change Memory Device Performance : AEPM: Advance Equipment Processes and Materials","authors":"Kevin Brew, R. Conti, I. Saraf, Cheng-Wei Cheng, Cheng-Wei Cheng, William Lee, Yin Xu, N. Saulnier, T. Masuda, T. Jimbo","doi":"10.1109/ASMC49169.2020.9185322","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185322","url":null,"abstract":"Oxidation of phase-change memory (PCM) materials (e.g. $Ge_{2}Sb_{2}Te_{5}$, GST) has been shown to decrease crystallization temperature and impact film composition, thus impacting analog switching behavior [1], [2]. PCM mushroom-cell devices were engineered on a 14 nm backend test vehicle to compare the electrical switching performance of in-situ and ex-situ capped GST 225. To mitigate the electrical effects from varying top electrode processes between tools, in-situ devices were fabricated with a Ti-TiN cap on GST before exposure to air. The in-situ cap is reduced to a minimal thickness to prevent oxidation of the Ti adhesion layer and the remainder of TiN was deposited matching to the ex-situ top electrode process. TEM of in-situ capped samples were found to have less GST undercut from patterning and have less reduction of the contact area between the GST and top electrode. SET and RESET programming of in-situ capped PCM devices show comparable SET and RESET state resistances to ex-situ processed PCM devices. Current-voltage measurements show that the in-situ PCM can have slightly lower voltage threshold switching but achieves a significantly higher current after threshold switching. The increased current for in-situ capped PCM results in higher power consumption with fixed voltage programming.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"10 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84361233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185276
Annalisa Del Vito, I. Osherov, A. Urbanowicz, Y. Katz, Kobi Barkan, I. Turovets, R. Haupt
The mainstream of dimensional metrology development is focused towards continuous shrinking of the devices (Moore scaling). Current cutting-edge technologies are in few nanometer range (3-7nm). There is also a growing demand to characterize structures with large dimensions in microns range (pitch, CD or depth). New technology megatrends such as internet of things (IOT) additionally require More than Moore scaling and heterogeneous integration [1–3]. Due to recent developments ultra large pitch scatterometry applications growth is observed in high power, sensors and packaging areas. Here we present novel approach that is focused on ultra large pitch scatterometry and its challenges. We demonstrate how to extend usage of conventional scatterometry for micro size devices.
{"title":"Ultra large pitch and depth structures metrology using spectral reflectometry in combination with RCWA based model and TLM Algorithm : AM: Advanced Metrology","authors":"Annalisa Del Vito, I. Osherov, A. Urbanowicz, Y. Katz, Kobi Barkan, I. Turovets, R. Haupt","doi":"10.1109/ASMC49169.2020.9185276","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185276","url":null,"abstract":"The mainstream of dimensional metrology development is focused towards continuous shrinking of the devices (Moore scaling). Current cutting-edge technologies are in few nanometer range (3-7nm). There is also a growing demand to characterize structures with large dimensions in microns range (pitch, CD or depth). New technology megatrends such as internet of things (IOT) additionally require More than Moore scaling and heterogeneous integration [1–3]. Due to recent developments ultra large pitch scatterometry applications growth is observed in high power, sensors and packaging areas. Here we present novel approach that is focused on ultra large pitch scatterometry and its challenges. We demonstrate how to extend usage of conventional scatterometry for micro size devices.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89789284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185381
Yao-Yuan Chang, Zusing Yang, Ming-Tsung Wu, Hong-Ji Lee, N. Lian, Tahone Yang, Kuang-Chao Chen, Chih-Yuan Lu
For silicon selective epitaxy growth (Si-SEG) process, an ex situ pre-epitaxial treatment (PET) is applied in order to remove the damaged layer and impurities. In this work, we observe asymmetric Si recess formed at the bottom of vertical channel (VC) holes in varied staircase environments leading to non-uniform, poor Si-SEG quality. A proposed symmetric silicon oxide/nitride (ON) film stack environment around VC holes by a given REG shift or via applicable layout modification manages to provide balanced charging potential to form symmetric Si etched recess inside VC holes post PET process. Subsequently, the Si-SEG process can form uniform epitaxial Si height at the bottom of VC in 3D NAND fabrication.
{"title":"Impact of Asymmetric Memory Hole Profile on Silicon Selective Epitaxial Growth in 3D NAND Memory : AEPM: Advanced Equipment Processes and Materials","authors":"Yao-Yuan Chang, Zusing Yang, Ming-Tsung Wu, Hong-Ji Lee, N. Lian, Tahone Yang, Kuang-Chao Chen, Chih-Yuan Lu","doi":"10.1109/ASMC49169.2020.9185381","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185381","url":null,"abstract":"For silicon selective epitaxy growth (Si-SEG) process, an ex situ pre-epitaxial treatment (PET) is applied in order to remove the damaged layer and impurities. In this work, we observe asymmetric Si recess formed at the bottom of vertical channel (VC) holes in varied staircase environments leading to non-uniform, poor Si-SEG quality. A proposed symmetric silicon oxide/nitride (ON) film stack environment around VC holes by a given REG shift or via applicable layout modification manages to provide balanced charging potential to form symmetric Si etched recess inside VC holes post PET process. Subsequently, the Si-SEG process can form uniform epitaxial Si height at the bottom of VC in 3D NAND fabrication.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"86 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75980271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185215
J. A. Torres, Ivan Kissiov, M. Essam, C. Hartig, Richard Gardner, Ken Jantzen, Stefan Schueler, M. Niehoff
In the past, concepts like critical area analysis, have been successfully implemented to predict random and systematic layout induced effects. This has enabled semiconductor companies to have an initial estimate as to how a fixed process will respond to a variety of different designs. However, as the number of individual products increases, along with a reduction in the total number of wafers per product, it becomes increasingly difficult to determine which process parameters will lead to the highest possible yield for each individual product. We have outlined a methodology using machine learning that combines process and design data to greatly reduce the time needed for setting up new products. We have shown that similar designs (based on our feature extraction) behave similarly in the fab, thus allowing us to construct models that can eventually be used to find the optimal process conditions for a given design. Due to the nature or process optimization, this methodology also explores the use of SHAPley additive explanations (SHAP) in order to “interface” with existing human and physical explanations of the observations, thus providing a mechanism to assess the quality and reliability of the numerically derived models.
{"title":"Machine Learning Assisted New Product Setup","authors":"J. A. Torres, Ivan Kissiov, M. Essam, C. Hartig, Richard Gardner, Ken Jantzen, Stefan Schueler, M. Niehoff","doi":"10.1109/ASMC49169.2020.9185215","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185215","url":null,"abstract":"In the past, concepts like critical area analysis, have been successfully implemented to predict random and systematic layout induced effects. This has enabled semiconductor companies to have an initial estimate as to how a fixed process will respond to a variety of different designs. However, as the number of individual products increases, along with a reduction in the total number of wafers per product, it becomes increasingly difficult to determine which process parameters will lead to the highest possible yield for each individual product. We have outlined a methodology using machine learning that combines process and design data to greatly reduce the time needed for setting up new products. We have shown that similar designs (based on our feature extraction) behave similarly in the fab, thus allowing us to construct models that can eventually be used to find the optimal process conditions for a given design. Due to the nature or process optimization, this methodology also explores the use of SHAPley additive explanations (SHAP) in order to “interface” with existing human and physical explanations of the observations, thus providing a mechanism to assess the quality and reliability of the numerically derived models.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"26 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76120636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185377
H. Teyssèdre, F. Delachat, Jonas Khan, J. Reche, Manuela Stirner, Peter Ledel
In twenty years, consequent technical developments have been achieved to make the soft stamp nano imprint lithography (NIL technology mature for high volume production [1]. Today the up to date technology and materials from EVG have shown high repeatability and uniformity in term of critical dimension (CD) and advanced rules-based have been proposed [2],[3]. Based on this progress, this paper will focus on line width roughness (LWR) and line edge roughness (LER) extraction as a new metric to monitor quality of imprint. Evolution of these metrics are studied to provide information on stability of the imprint process.
{"title":"Repeatability of Nanoimprint Lithography Monitor Through Line Roughness Extraction","authors":"H. Teyssèdre, F. Delachat, Jonas Khan, J. Reche, Manuela Stirner, Peter Ledel","doi":"10.1109/ASMC49169.2020.9185377","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185377","url":null,"abstract":"In twenty years, consequent technical developments have been achieved to make the soft stamp nano imprint lithography (NIL technology mature for high volume production [1]. Today the up to date technology and materials from EVG have shown high repeatability and uniformity in term of critical dimension (CD) and advanced rules-based have been proposed [2],[3]. Based on this progress, this paper will focus on line width roughness (LWR) and line edge roughness (LER) extraction as a new metric to monitor quality of imprint. Evolution of these metrics are studied to provide information on stability of the imprint process.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"100 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80656801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185393
Yang Yuan-Fu, Sun Min
The individual components of an integrated circuit (IC) are extremely small and its production demands precision at an atomic level. ICs are made by creating circuit structures on a wafer made out of very pure semiconducting material, typically silicon, and interconnecting the structures using wires. In order to produce high density IC, the wafer surface must be extremely clean and the circuit layers fabricated on the previous wafer should be aligned. If these conditions are not satisfied, the high density structure may collapse.To prevent this from happening, the wafers must be constantly cleaned to avoid contamination, and to remove the left-over of the previous process steps. Then, automatic defect classification (ADC) is used to identify and classify wafer surface defects using scanning electron microscope images. However, the classification performance of current ADC systems is poor. If the defects could be classified correctly, then the root of the fabrication problem can be recognized and eventually resolved.Machine learning techniques have been widely accepted and are well suited for such classification problems. In this paper, we propose double feature extraction method based on convolution neural network. The proposed model uses the Radon transform for the first feature extraction, and then input this feature into the convolution layer for the second feature extraction. Experiments with real-world data set verified that the proposed method achieves high defect classification performance, defect pattern recognition accuracy up to 98.5%, and we confirmed the effectiveness of the proposed feature extraction technique.
{"title":"Double Feature Extraction Method for Wafer Map Classification Based on Convolution Neural Network","authors":"Yang Yuan-Fu, Sun Min","doi":"10.1109/ASMC49169.2020.9185393","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185393","url":null,"abstract":"The individual components of an integrated circuit (IC) are extremely small and its production demands precision at an atomic level. ICs are made by creating circuit structures on a wafer made out of very pure semiconducting material, typically silicon, and interconnecting the structures using wires. In order to produce high density IC, the wafer surface must be extremely clean and the circuit layers fabricated on the previous wafer should be aligned. If these conditions are not satisfied, the high density structure may collapse.To prevent this from happening, the wafers must be constantly cleaned to avoid contamination, and to remove the left-over of the previous process steps. Then, automatic defect classification (ADC) is used to identify and classify wafer surface defects using scanning electron microscope images. However, the classification performance of current ADC systems is poor. If the defects could be classified correctly, then the root of the fabrication problem can be recognized and eventually resolved.Machine learning techniques have been widely accepted and are well suited for such classification problems. In this paper, we propose double feature extraction method based on convolution neural network. The proposed model uses the Radon transform for the first feature extraction, and then input this feature into the convolution layer for the second feature extraction. Experiments with real-world data set verified that the proposed method achieves high defect classification performance, defect pattern recognition accuracy up to 98.5%, and we confirmed the effectiveness of the proposed feature extraction technique.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"9 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78538506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185337
J. Chen, F. Lie, S. Devries, C. Boye, Sanjay Mehta, T. Devarajan, M. Silvestre, W. Tseng, M. Aminpur
In this paper, a case study on control of BEOL defectivity in a systematic way for the future AI application is presented. A few novel methodologies were introduced to identify the source of defectivity in various BEOL sectors, such as, patterning, barrier deposition, plating, and CMP. We successfully reduced the defectivity to the level required to yield target AI devices.
{"title":"A Systematic Study on BEOL Defectivity Control for Future AI Application","authors":"J. Chen, F. Lie, S. Devries, C. Boye, Sanjay Mehta, T. Devarajan, M. Silvestre, W. Tseng, M. Aminpur","doi":"10.1109/ASMC49169.2020.9185337","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185337","url":null,"abstract":"In this paper, a case study on control of BEOL defectivity in a systematic way for the future AI application is presented. A few novel methodologies were introduced to identify the source of defectivity in various BEOL sectors, such as, patterning, barrier deposition, plating, and CMP. We successfully reduced the defectivity to the level required to yield target AI devices.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"4 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86931964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185204
Binay Dash, K. Iyer, J. Barker, Shiladitya Chakravorty
In a semiconductor manufacturing facility (FAB), wafers spend the majority of their manufacturing life in Front Opening Unified Pods (FOUPs), and it is essential that the environment be as clean as, or cleaner than, that of the manufacturing floor. While manufacturing equipment are usually constructed to actively purge and exchange internal environment to fab atmosphere, the FOUP is a relatively static environment that can only equalize its environment with the ambient area of storage. Hence periodic cleaning of FOUPs is essential to ensure the wafers produced meet requisite quality. However, selection of the number of FOUPs for cleaning provides challenges to the WIP flow strategy, scheduling and dispatching decisions. In this poster, we will cover the generic options for FOUP cleaning, metrology and dispatching challenges. Subsequently we will discuss the various strategies considered and employed to achieve appropriate trade-offs between various factors with respect to dispatching.
{"title":"Dynamic Dispatching for FOUP Cleaning","authors":"Binay Dash, K. Iyer, J. Barker, Shiladitya Chakravorty","doi":"10.1109/ASMC49169.2020.9185204","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185204","url":null,"abstract":"In a semiconductor manufacturing facility (FAB), wafers spend the majority of their manufacturing life in Front Opening Unified Pods (FOUPs), and it is essential that the environment be as clean as, or cleaner than, that of the manufacturing floor. While manufacturing equipment are usually constructed to actively purge and exchange internal environment to fab atmosphere, the FOUP is a relatively static environment that can only equalize its environment with the ambient area of storage. Hence periodic cleaning of FOUPs is essential to ensure the wafers produced meet requisite quality. However, selection of the number of FOUPs for cleaning provides challenges to the WIP flow strategy, scheduling and dispatching decisions. In this poster, we will cover the generic options for FOUP cleaning, metrology and dispatching challenges. Subsequently we will discuss the various strategies considered and employed to achieve appropriate trade-offs between various factors with respect to dispatching.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"5 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84213442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185301
Satyajit Shinde, Chee Huei Chan, Marcus Minchew, Lawrence Mbonu
Nitride film LPCVD (Low Pressure Chemical Vapor Deposition) process is well known in semiconductor industry. The paper covers an innovative approach in touching two aspects of improvement in LPCVD nitride process in diffusion furnace. First is the extension of quartz life use by implementation of unique LTP (Low Temperature Purge) without affecting particle performance. Secondly, the impact of extended quartz life on the wafer uniformity across the different zones and methodology to compensate it.
{"title":"Innovative Approach on Dynamic Behavior of LPCVD Nitride Process on Diffusion Furnace : Equipment Optimization/Advanced Process Control/Contamination Free Manufacturing","authors":"Satyajit Shinde, Chee Huei Chan, Marcus Minchew, Lawrence Mbonu","doi":"10.1109/ASMC49169.2020.9185301","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185301","url":null,"abstract":"Nitride film LPCVD (Low Pressure Chemical Vapor Deposition) process is well known in semiconductor industry. The paper covers an innovative approach in touching two aspects of improvement in LPCVD nitride process in diffusion furnace. First is the extension of quartz life use by implementation of unique LTP (Low Temperature Purge) without affecting particle performance. Secondly, the impact of extended quartz life on the wafer uniformity across the different zones and methodology to compensate it.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"52 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76961908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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