Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185254
V. Chan, M. Bergendahl, S. Choi, A. Gaul, J. Strane, A. Greene, J. Demarest, J. Li, C. Le, S. Teehan, D. Guo
Ring Oscillators (ROs) are used for yield learning during the research phase of a CMO technology. We performed cross-sections and showed that the open and short defects are in the middle of line (MOL) gate structures. The defects which are related to MOL or prior processes, as well as the design and density, will be discussed in the paper.
{"title":"Middle of Line (MOL) Process Investigation in Ring Oscillator failure","authors":"V. Chan, M. Bergendahl, S. Choi, A. Gaul, J. Strane, A. Greene, J. Demarest, J. Li, C. Le, S. Teehan, D. Guo","doi":"10.1109/ASMC49169.2020.9185254","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185254","url":null,"abstract":"Ring Oscillators (ROs) are used for yield learning during the research phase of a CMO technology. We performed cross-sections and showed that the open and short defects are in the middle of line (MOL) gate structures. The defects which are related to MOL or prior processes, as well as the design and density, will be discussed in the paper.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"21 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87637749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185260
Meejung Kwon, Song Han, Je Hyeok Ryu, Chiyoung Lee, Yoon Young Lee, Byung Hoon Kim
This paper investigates the oxidation behavior of Epitaxial Silicon Germanium ($Si_{1-x}Ge_{x}$) thin-film during a dry strip process. In this study hydrogen radicals generated through $H_{2}/N_{2}$ plasma, which is known to suppress surface oxidation, was examined. Oxidation behavior and Ge loss rate are compared according to Ge content.
{"title":"Characteristics of SiGe Oxidation and Ge Loss according to Ge Content","authors":"Meejung Kwon, Song Han, Je Hyeok Ryu, Chiyoung Lee, Yoon Young Lee, Byung Hoon Kim","doi":"10.1109/ASMC49169.2020.9185260","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185260","url":null,"abstract":"This paper investigates the oxidation behavior of Epitaxial Silicon Germanium ($Si_{1-x}Ge_{x}$) thin-film during a dry strip process. In this study hydrogen radicals generated through $H_{2}/N_{2}$ plasma, which is known to suppress surface oxidation, was examined. Oxidation behavior and Ge loss rate are compared according to Ge content.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"10 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84188649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185368
R. Rhoades, R. Mavliev, K. Gottfried
A novel method for selective deposition of metal features has been developed and evaluated for several different metallization applications in device manufacturing and advanced packaging technologies. Selectroplating® is based on a selective chemical modification (SCM) of field areas of a wafer and can be implemented for either a fill-based integration, such as Cu dual damascene, or an additive process such as plating of wide conductive lines. In either integration, the primary benefit of selective deposition is to prevent deposition of metal in areas between desired features thus eliminating the need to remove excess bulk metal in the next step.
{"title":"Selective Metal Deposition To Increase Productivity","authors":"R. Rhoades, R. Mavliev, K. Gottfried","doi":"10.1109/ASMC49169.2020.9185368","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185368","url":null,"abstract":"A novel method for selective deposition of metal features has been developed and evaluated for several different metallization applications in device manufacturing and advanced packaging technologies. Selectroplating® is based on a selective chemical modification (SCM) of field areas of a wafer and can be implemented for either a fill-based integration, such as Cu dual damascene, or an additive process such as plating of wide conductive lines. In either integration, the primary benefit of selective deposition is to prevent deposition of metal in areas between desired features thus eliminating the need to remove excess bulk metal in the next step.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"26 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86174577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185271
Aditya Kumar, Kyle E. Pratt, O. Famodu, Bhavyen Patel
Atomic layer deposition (ALD) TiN metal films are used in semiconductor manufacturing for various purposes, such as work function metal, metal cap, and barrier films. ALD TiN chamber and process generate different types of particle defects having different morphologies and compositions. One of the main types of defect was found to be TiN surface particle from tetrakis-dimethylamino titanium (TDMAT). This work presents a solution to reduce the surface defects that are generated from the condensation of TDMAT. In this work, heated gas lines for He carrier gas and other process gases, such as Ar and N2, were used to reduce surface defects from ALD TiN. Two methods for heating gas lines were evaluated. In one method, gas lines with in-build heater were used and, in another method, heating jackets were used to heat the gas lines. A detailed material characterization of ALD TiN film using SIMS, XRD, and XPS was carried out to understand the influence of heated process gases on ALD TiN film properties. A significant surface defects reduction of more than 30% was achieved using the heated gas lines of process gases.
{"title":"ALD TiN Surface Defect Reduction for 12nm and Beyond Technologies","authors":"Aditya Kumar, Kyle E. Pratt, O. Famodu, Bhavyen Patel","doi":"10.1109/ASMC49169.2020.9185271","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185271","url":null,"abstract":"Atomic layer deposition (ALD) TiN metal films are used in semiconductor manufacturing for various purposes, such as work function metal, metal cap, and barrier films. ALD TiN chamber and process generate different types of particle defects having different morphologies and compositions. One of the main types of defect was found to be TiN surface particle from tetrakis-dimethylamino titanium (TDMAT). This work presents a solution to reduce the surface defects that are generated from the condensation of TDMAT. In this work, heated gas lines for He carrier gas and other process gases, such as Ar and N2, were used to reduce surface defects from ALD TiN. Two methods for heating gas lines were evaluated. In one method, gas lines with in-build heater were used and, in another method, heating jackets were used to heat the gas lines. A detailed material characterization of ALD TiN film using SIMS, XRD, and XPS was carried out to understand the influence of heated process gases on ALD TiN film properties. A significant surface defects reduction of more than 30% was achieved using the heated gas lines of process gases.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"14 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88469398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185397
M. Murugesan, K. Mori, T. Kojima, H. Hashimoto, J. Bea, T. Fukushima, M. Koyanagi
Two of the major reliability issues in threedimensional (3D)-LSIs namely the back-metal contamination (i.e. diffusion of Cu into active Si during the BEOL processes), and the thermo-mechanical stress associated with through-Si-via (TSV) were meticulously studied for Ni/Cu nano-TSVs for their application in 3D-IC integration. A very good barrier ability against Cu-diffusion for Ni seed layer was confirmed from the stable C dd and the absence of metal impurities in the underneath dielectric layer and beyond by respectively the capacitance-voltage analysis and the secondary ion mass spectroscopy, even after annealing at 300 °C. Further, a cluster of 36 Ni/Cu nano-TSVs having the width value of ~500 nm spreading over ~70 μm2 area did not induce any additional thermo-mechanical stress in the vicinal Si after annealing at 300°C, whereas the conventional 5 pm- width Cu-TSVs over a similar area have induced >300 MPa of compressive stress after annealing.
{"title":"Nano Ni/Cu-TSVs with an Improved Reliability for 3D-IC Integration Application","authors":"M. Murugesan, K. Mori, T. Kojima, H. Hashimoto, J. Bea, T. Fukushima, M. Koyanagi","doi":"10.1109/ASMC49169.2020.9185397","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185397","url":null,"abstract":"Two of the major reliability issues in threedimensional (3D)-LSIs namely the back-metal contamination (i.e. diffusion of Cu into active Si during the BEOL processes), and the thermo-mechanical stress associated with through-Si-via (TSV) were meticulously studied for Ni/Cu nano-TSVs for their application in 3D-IC integration. A very good barrier ability against Cu-diffusion for Ni seed layer was confirmed from the stable C dd and the absence of metal impurities in the underneath dielectric layer and beyond by respectively the capacitance-voltage analysis and the secondary ion mass spectroscopy, even after annealing at 300 °C. Further, a cluster of 36 Ni/Cu nano-TSVs having the width value of ~500 nm spreading over ~70 μm2 area did not induce any additional thermo-mechanical stress in the vicinal Si after annealing at 300°C, whereas the conventional 5 pm- width Cu-TSVs over a similar area have induced >300 MPa of compressive stress after annealing.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"88 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88268115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185255
B. Williams, Robert Davis, Justin Yerger, D. Allman, B. Greenwood, T. Ruud
This paper will demonstrate wirebond pad design considerations for the source pad of a power trenchFET using three levels of metal. There will be a discussion of how the pad design will impact the pad mechanical strength through the bonding process. There will also be a comparison of bondpad design to thermal/electrical simulation results. An optimal design can be obtained by an analysis of these tradeoffs. Finally the proposed designs have been built on silicon and evaluated both mechanically and electrically concluding with best design found for this application.
{"title":"Bondpad Design Structural vs. Electrical Tradeoffs","authors":"B. Williams, Robert Davis, Justin Yerger, D. Allman, B. Greenwood, T. Ruud","doi":"10.1109/ASMC49169.2020.9185255","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185255","url":null,"abstract":"This paper will demonstrate wirebond pad design considerations for the source pad of a power trenchFET using three levels of metal. There will be a discussion of how the pad design will impact the pad mechanical strength through the bonding process. There will also be a comparison of bondpad design to thermal/electrical simulation results. An optimal design can be obtained by an analysis of these tradeoffs. Finally the proposed designs have been built on silicon and evaluated both mechanically and electrically concluding with best design found for this application.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"99 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86998105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185350
Robert Schmaler, C. Hammel, C. Schubert
Automated material handling systems (AMHS) in Semiconductor Fabrication Plants (Fabs) are crucial to achieve a high production throughput. When refurbishing an existing or planning a new Fab production plans are used to decide on the necessary tool park. But what about AMHS planning? To our knowledge no method exists, given an anticipated product mix, to reliably generate expected transport patterns including nonproductive transports. This paper summarizes a methodology based on a given product mix together with scheduling rules and AMHS characteristics to generate such transport patterns, including non-productive transports like test wafers and empty FOUPs, and subsequently a deep insight into actual AMHS capabilities and requirements in the planning phase. Results will be reviewed via static simulation to identify possible AMHS bottlenecks as early as possible.
{"title":"AMHS Capability Assessment Based on Planned Product Mixes","authors":"Robert Schmaler, C. Hammel, C. Schubert","doi":"10.1109/ASMC49169.2020.9185350","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185350","url":null,"abstract":"Automated material handling systems (AMHS) in Semiconductor Fabrication Plants (Fabs) are crucial to achieve a high production throughput. When refurbishing an existing or planning a new Fab production plans are used to decide on the necessary tool park. But what about AMHS planning? To our knowledge no method exists, given an anticipated product mix, to reliably generate expected transport patterns including nonproductive transports. This paper summarizes a methodology based on a given product mix together with scheduling rules and AMHS characteristics to generate such transport patterns, including non-productive transports like test wafers and empty FOUPs, and subsequently a deep insight into actual AMHS capabilities and requirements in the planning phase. Results will be reviewed via static simulation to identify possible AMHS bottlenecks as early as possible.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"66 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74387051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185290
Leon van Dijk, K. M. Adal, Mathias Chastan, A. Lam, M. Larrañaga, Richard J. F. van Haren
Virtual overlay metrology has been developed for a series of nine implant layers using a hybrid approach that combines physical modeling with machine learning. The prediction model is evaluated on production data. A high prediction capability is achieved and the model is able to follow variations in the implant-layer overlay and to identify outliers. We will use the prediction model to link excursions to a possible root cause. Furthermore, a KPI based on scanner metrology is defined that can be monitored continuously, and for every wafer, for detecting excursions with a similar root cause.
{"title":"Towards Excursion Detection for Implant Layers based on Virtual Overlay Metrology","authors":"Leon van Dijk, K. M. Adal, Mathias Chastan, A. Lam, M. Larrañaga, Richard J. F. van Haren","doi":"10.1109/ASMC49169.2020.9185290","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185290","url":null,"abstract":"Virtual overlay metrology has been developed for a series of nine implant layers using a hybrid approach that combines physical modeling with machine learning. The prediction model is evaluated on production data. A high prediction capability is achieved and the model is able to follow variations in the implant-layer overlay and to identify outliers. We will use the prediction model to link excursions to a possible root cause. Furthermore, a KPI based on scanner metrology is defined that can be monitored continuously, and for every wafer, for detecting excursions with a similar root cause.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"101 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77642350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185401
C. Edwards, C. Morgan, John D. Rudolph, Danniel Slinker, Debashis Panda
Metrology and inspection algorithms, no matter how robust, will only exhibit acceptable performance over a finite range of image variation. As our algorithms become more and more advanced, geared towards finding smaller and smaller defects with ever-increasing accuracy, tool matching/calibration has become essential for successful inspection across a large fleet of tools. We present a new calibration utility that is versatile enough to be used for a wide variety of inspection systems. It allows us to ensure that the key imaging parameters on each tool are within a defined range which guarantees that the images produced by various tools are sufficiently similar and that the algorithm will perform as qualified. This also simplifies recipe management/portability across the fleet, allowing recipes created on one calibrated tool to be used on any other calibrated tool. This work covers a variety of multidisciplinary material including the calibration tray concept/design, key imaging parameters, user interface layout/design, as well as a variety of computer vision algorithms used to extract and examine the different regions of the calibration tray.
{"title":"NextGen Calibration Utility for Tool Setup and Matching in Real-Time Automated Visual Inspection Systems","authors":"C. Edwards, C. Morgan, John D. Rudolph, Danniel Slinker, Debashis Panda","doi":"10.1109/ASMC49169.2020.9185401","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185401","url":null,"abstract":"Metrology and inspection algorithms, no matter how robust, will only exhibit acceptable performance over a finite range of image variation. As our algorithms become more and more advanced, geared towards finding smaller and smaller defects with ever-increasing accuracy, tool matching/calibration has become essential for successful inspection across a large fleet of tools. We present a new calibration utility that is versatile enough to be used for a wide variety of inspection systems. It allows us to ensure that the key imaging parameters on each tool are within a defined range which guarantees that the images produced by various tools are sufficiently similar and that the algorithm will perform as qualified. This also simplifies recipe management/portability across the fleet, allowing recipes created on one calibrated tool to be used on any other calibrated tool. This work covers a variety of multidisciplinary material including the calibration tray concept/design, key imaging parameters, user interface layout/design, as well as a variety of computer vision algorithms used to extract and examine the different regions of the calibration tray.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"45 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79198468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185250
N. Chaudhary, S. Savari, Varvara Brackmann, M. Friedrich
The estimation of line and contour geometries from real SEM images is a challenging problem due to the corruption of such images by Poisson noise, edge effects, and other SEM artifacts. We attempt simultaneous contour edge image prediction and SEM image denoising using a deep convolutional neural network LineNet2. To capture a range of edge effects in real SEM images, we simulate a training dataset of rough line SEM images with random edge effect parameters. We train the LineNet2 network on this training dataset and randomly rotate the images during the training phase. The retrained LineNet2 shows the ability to denoise real SEM images of line and contour geometries. We measure the line edge roughness (LER) parameter in isolated and dense regions of rough line images through multiple LER methods. Our experiments also demonstrate that the network can learn to recognize contour edges just by rotating rough line images.
{"title":"SEM Image Denoising and Contour Image Estimation using Deep Learning","authors":"N. Chaudhary, S. Savari, Varvara Brackmann, M. Friedrich","doi":"10.1109/ASMC49169.2020.9185250","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185250","url":null,"abstract":"The estimation of line and contour geometries from real SEM images is a challenging problem due to the corruption of such images by Poisson noise, edge effects, and other SEM artifacts. We attempt simultaneous contour edge image prediction and SEM image denoising using a deep convolutional neural network LineNet2. To capture a range of edge effects in real SEM images, we simulate a training dataset of rough line SEM images with random edge effect parameters. We train the LineNet2 network on this training dataset and randomly rotate the images during the training phase. The retrained LineNet2 shows the ability to denoise real SEM images of line and contour geometries. We measure the line edge roughness (LER) parameter in isolated and dense regions of rough line images through multiple LER methods. Our experiments also demonstrate that the network can learn to recognize contour edges just by rotating rough line images.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"1 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85268315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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