Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185326
A. Pongrácz, J. Szívós, F. Ujhelyi, Z. Zolnai, Ö. Sepsi, Á. Kun, G. Nadudvari, J. Byrnes, L. Rubin, Edward D. Moore
Photo-modulated reflectance measurements provide a powerful, non-contact, non-destructive and inline-compatible method with low-cost operation for statistical process control of ion implantation steps on monitor and on product wafers. We present case studies describing how photo-modulated reflectivity measurements (PMR) can be used for ion implantation dose, fluence and tilt angle monitoring with excellent resolution, even for low-energy ion implantation processes. This is important because precise dopant and damage profile control is crucial in state-of-the art semiconductor processes utilizing shallow junctions and complex 3D doping profiles.
{"title":"Tilt angle and dose rate monitoring of low energy ion implantation processes with photomodulated reflectance measurement : AM: Advanced Metrology","authors":"A. Pongrácz, J. Szívós, F. Ujhelyi, Z. Zolnai, Ö. Sepsi, Á. Kun, G. Nadudvari, J. Byrnes, L. Rubin, Edward D. Moore","doi":"10.1109/ASMC49169.2020.9185326","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185326","url":null,"abstract":"Photo-modulated reflectance measurements provide a powerful, non-contact, non-destructive and inline-compatible method with low-cost operation for statistical process control of ion implantation steps on monitor and on product wafers. We present case studies describing how photo-modulated reflectivity measurements (PMR) can be used for ion implantation dose, fluence and tilt angle monitoring with excellent resolution, even for low-energy ion implantation processes. This is important because precise dopant and damage profile control is crucial in state-of-the art semiconductor processes utilizing shallow junctions and complex 3D doping profiles.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"33 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76926587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185259
V. Kaushal, R. Mahadevapuram, G. Yue, A. Raviswaran
In this paper, we present the development of a new 14nm SiGe process that is designed to improve with-in-wafer uniformity to eventually improve Electrical parameters, parametric limited yield and overall average yield. In addition we showed that throughput has also improved. The methods presented involved adding cross-flows of same process gases and optimizing the flows, temperature, power and time. By doing so, significant improvement in the WIW uniformity (growth and dopant concentration) and improvement in Defects were observed. This WIW uniformity led to significant improvements in various Electrical Test parameters as well as yield.
{"title":"PMOS SiGe epitaxial growth process improvement to increase Yield and Throughput","authors":"V. Kaushal, R. Mahadevapuram, G. Yue, A. Raviswaran","doi":"10.1109/ASMC49169.2020.9185259","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185259","url":null,"abstract":"In this paper, we present the development of a new 14nm SiGe process that is designed to improve with-in-wafer uniformity to eventually improve Electrical parameters, parametric limited yield and overall average yield. In addition we showed that throughput has also improved. The methods presented involved adding cross-flows of same process gases and optimizing the flows, temperature, power and time. By doing so, significant improvement in the WIW uniformity (growth and dopant concentration) and improvement in Defects were observed. This WIW uniformity led to significant improvements in various Electrical Test parameters as well as yield.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"68 3 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91102411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185278
Alexander Fuchs, R. Priewald, F. Pernkopf
The detection of hair cracks is one of the key challenges to improve wafer-processing stability. Contrary to other defects on the wafer-edge, hair cracks have a very small geometric footprint, making them hard to detect for measurement systems. This raises the demand for a powerful data analysis tool, which can extract the relevant information even in low signal-to-noise ratio scenarios. In this paper, we investigate an approach for hair crack detection using a laser-based wafer edge inspection device and deep neural networks to analyze and classify the measured data. We propose different pre-processing methods for the raw measurement data, to improve the learning behavior of the networks. The results show that a substantial improvement, in both detection rate and false positive rate, can be achieved by appropriate pre-processing of the measured data.
{"title":"Laser-based Hair Crack Detection on Wafers","authors":"Alexander Fuchs, R. Priewald, F. Pernkopf","doi":"10.1109/ASMC49169.2020.9185278","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185278","url":null,"abstract":"The detection of hair cracks is one of the key challenges to improve wafer-processing stability. Contrary to other defects on the wafer-edge, hair cracks have a very small geometric footprint, making them hard to detect for measurement systems. This raises the demand for a powerful data analysis tool, which can extract the relevant information even in low signal-to-noise ratio scenarios. In this paper, we investigate an approach for hair crack detection using a laser-based wafer edge inspection device and deep neural networks to analyze and classify the measured data. We propose different pre-processing methods for the raw measurement data, to improve the learning behavior of the networks. The results show that a substantial improvement, in both detection rate and false positive rate, can be achieved by appropriate pre-processing of the measured data.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"67 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87637771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185191
Zusing Yang, Yao-Yuan Chang, Ming-Tsung Wu, Hong-Ji Lee, N. Lian, Tahone Yang, Kuang-Chao Chen, Chih-Yuan Lu
The challenges of oval-shaped silicon dioxide and polysilicon (OP)-layer hole etching, including shape deformation, local arcing, and adjacent hole bridging are reported. We explore the shape deformation evolution step by step and point out that wiggling of the organic mask is the most critical factor to enhance the occurrence of shape deformation. Further, the local arcing induced profile damage during hole-patterned etching could be eliminated by stacking specific capping materials on the top of OP layers. A DOE of the etch process demonstrates the ability to solve the adjacent hole bridging issue.
{"title":"Oval-Shaped OP-Layer Hole Etching: Shape Deformation, Local Arcing, and Hole Bridging Improvements","authors":"Zusing Yang, Yao-Yuan Chang, Ming-Tsung Wu, Hong-Ji Lee, N. Lian, Tahone Yang, Kuang-Chao Chen, Chih-Yuan Lu","doi":"10.1109/ASMC49169.2020.9185191","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185191","url":null,"abstract":"The challenges of oval-shaped silicon dioxide and polysilicon (OP)-layer hole etching, including shape deformation, local arcing, and adjacent hole bridging are reported. We explore the shape deformation evolution step by step and point out that wiggling of the organic mask is the most critical factor to enhance the occurrence of shape deformation. Further, the local arcing induced profile damage during hole-patterned etching could be eliminated by stacking specific capping materials on the top of OP layers. A DOE of the etch process demonstrates the ability to solve the adjacent hole bridging issue.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"23 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87540234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185247
R. Hafer, A. Stamper, J. Hsieh
For a recent replacement metal gate (RMG) FINFET technology using a silicon-on-insulator (SOI) substrate, contact to gate electrical isolation is monitored with Electron Beam Inspection (EBI). The variation in isolation could be due to either lithography overlay error or critical dimensions. The inspection is performed in a Voltage contrast mode (VC). A within reticle inspection using EBI is proposed to characterize the within-reticle and within-wafer variation.
{"title":"Electron Beam Inspection: Voltage Contrast Inspection to Characterize Contact Isolation","authors":"R. Hafer, A. Stamper, J. Hsieh","doi":"10.1109/ASMC49169.2020.9185247","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185247","url":null,"abstract":"For a recent replacement metal gate (RMG) FINFET technology using a silicon-on-insulator (SOI) substrate, contact to gate electrical isolation is monitored with Electron Beam Inspection (EBI). The variation in isolation could be due to either lithography overlay error or critical dimensions. The inspection is performed in a Voltage contrast mode (VC). A within reticle inspection using EBI is proposed to characterize the within-reticle and within-wafer variation.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"110 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82889325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185245
M. Mehendale, M. Kotelyanskii, R. Mair, P. Mukundhan, J. Bogdanowicz, L. Teugels, A. Charley, P. Kuszewski
Characterization of patterned nanostructures in modern nanoelectronic memory and logic devices using traditional optical critical dimension (OCD) metrology technique faces challenges as the structures become optically opaque. In this paper, we present the picosecond ultrasonic (PU) based acoustic metrology technique as a viable option to characterize periodically patterned nanostructures. Specifically, we evaluate the sensitivity of PU to metal line arrays of various geometries and show that the frequency profile of generated acoustics is dependent on the sample geometry including the pitch and width of the metal lines exposed. We also demonstrate that the signal is sensitive to the presence of the lines embedded under a blanket layer of the same metal.
{"title":"Characterization of Sub-micron Metal Line Arrays Using Picosecond Ultrasonics","authors":"M. Mehendale, M. Kotelyanskii, R. Mair, P. Mukundhan, J. Bogdanowicz, L. Teugels, A. Charley, P. Kuszewski","doi":"10.1109/ASMC49169.2020.9185245","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185245","url":null,"abstract":"Characterization of patterned nanostructures in modern nanoelectronic memory and logic devices using traditional optical critical dimension (OCD) metrology technique faces challenges as the structures become optically opaque. In this paper, we present the picosecond ultrasonic (PU) based acoustic metrology technique as a viable option to characterize periodically patterned nanostructures. Specifically, we evaluate the sensitivity of PU to metal line arrays of various geometries and show that the frequency profile of generated acoustics is dependent on the sample geometry including the pitch and width of the metal lines exposed. We also demonstrate that the signal is sensitive to the presence of the lines embedded under a blanket layer of the same metal.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"56 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72944423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185315
F. Niedermeier, Rolf Kammerer, W. Kipferl, Stephan Henneck, Haim Pearl
This paper describes a plan of tests and several results of experiments that were performed to determine whether wafers that were milled using an inline xenon (Xe) plasma focused ion beam (PFIB) could continue processing through the standard production flow without being scrapped for contamination, yield, or reliability issues.
{"title":"Qualifying Inline Xe Plasma FIB - Returning Milled Wafers Back to Production","authors":"F. Niedermeier, Rolf Kammerer, W. Kipferl, Stephan Henneck, Haim Pearl","doi":"10.1109/ASMC49169.2020.9185315","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185315","url":null,"abstract":"This paper describes a plan of tests and several results of experiments that were performed to determine whether wafers that were milled using an inline xenon (Xe) plasma focused ion beam (PFIB) could continue processing through the standard production flow without being scrapped for contamination, yield, or reliability issues.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"179 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74162530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185351
J. Reche, Y. Blancquaert, G. Freychet, P. Gergaud, M. Besacier
The capabilities of Small Angle X-ray Scattering (SAXS) for dimensional control of line gratings are reviewed. We first introduce different experimental methodologies used to extract the pitch, the critical dimension (CD) and the side-wall angle (SWA) of line gratings. A special focus is done on line roughness extraction. We already demonstrated that the SAXS technique has the sensitivity to measure line roughness amplitude below 1 nm on a set of line gratings designed with a controlled line roughness [1]. Fast Fourier Transforms (FFT) simulations revealed that the Line Width Roughness (LWR) defined as a Power Spectral Density (PSD) can be measured in a SAXS pattern at some specific positions in the reciprocal space [2]. In the present study, a comparison of the LWR PSD extracted by SAXS and by Scanning Electron Microscope (SEM) on one set of samples was done.
{"title":"Dimensional Control of Line Gratings by Small Angle X-Ray Scattering: Shape and Roughness Extraction","authors":"J. Reche, Y. Blancquaert, G. Freychet, P. Gergaud, M. Besacier","doi":"10.1109/ASMC49169.2020.9185351","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185351","url":null,"abstract":"The capabilities of Small Angle X-ray Scattering (SAXS) for dimensional control of line gratings are reviewed. We first introduce different experimental methodologies used to extract the pitch, the critical dimension (CD) and the side-wall angle (SWA) of line gratings. A special focus is done on line roughness extraction. We already demonstrated that the SAXS technique has the sensitivity to measure line roughness amplitude below 1 nm on a set of line gratings designed with a controlled line roughness [1]. Fast Fourier Transforms (FFT) simulations revealed that the Line Width Roughness (LWR) defined as a Power Spectral Density (PSD) can be measured in a SAXS pattern at some specific positions in the reciprocal space [2]. In the present study, a comparison of the LWR PSD extracted by SAXS and by Scanning Electron Microscope (SEM) on one set of samples was done.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"44 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81587199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185365
C. Keith, Ace Chen, Haim Albalak, Maryam Anvar
This paper presents a model to optimize the number of recipes qualified on each tool or chamber in a fleet by evaluating the trade-off between the cost in tool time required to run nonproduct wafers (NPW’s) for qualifying additional recipes versus the benefit of having as many recipes as possible qualified to maximize flexibility. The model specifically addresses an issue observed in high volume fabs such as large memory fabs, where most of the tools are qualified to run several recipes. In these situations, in which the number of tools is much greater than the number of recipes and substantial resources (such as process and metrology tool time, non-product wafers, and labor) are required to qualify each recipe, the cost in tool time for qualifying many recipes on each tool can outweigh the benefits in flexibility. Based on typical product mixes and qualification requirements in such a fab, we demonstrate that using this model could reduce the tool time required to run qualification wafers and increase the time available to run production wafers by 1% or more with minimal or no impact on cycle time.
{"title":"Output Improvement in High Volume Memory Fabs by Reducing Recipe Qualifications","authors":"C. Keith, Ace Chen, Haim Albalak, Maryam Anvar","doi":"10.1109/ASMC49169.2020.9185365","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185365","url":null,"abstract":"This paper presents a model to optimize the number of recipes qualified on each tool or chamber in a fleet by evaluating the trade-off between the cost in tool time required to run nonproduct wafers (NPW’s) for qualifying additional recipes versus the benefit of having as many recipes as possible qualified to maximize flexibility. The model specifically addresses an issue observed in high volume fabs such as large memory fabs, where most of the tools are qualified to run several recipes. In these situations, in which the number of tools is much greater than the number of recipes and substantial resources (such as process and metrology tool time, non-product wafers, and labor) are required to qualify each recipe, the cost in tool time for qualifying many recipes on each tool can outweigh the benefits in flexibility. Based on typical product mixes and qualification requirements in such a fab, we demonstrate that using this model could reduce the tool time required to run qualification wafers and increase the time available to run production wafers by 1% or more with minimal or no impact on cycle time.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"60 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84788010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185305
Thomas Nassiet, R. Duru, D. Le-Cunff, A. Arnaud, J. Bluet, G. Brémond
We present an innovative approach of bias dependent photoluminescence characterization (PL-V) involving industrial Room Temperature Photoluminescence (RTPL) combined with corona charging. PL-V is performed on silicon oxide and silicon nitride films prepared on p-type silicon substrates. Results are directly compared to Capacitance-Voltage (C-V) measurements. A linearized model for PL-V has also been developed to understand the physical properties associated with this technique and the key similarities with C-V characterization. We finally show the sensitivity of PL-V to surface state density whose determination can benefit passivation quality studies.
{"title":"Investigation of Photoluminescence Voltage PL-V Measurement: Correlation to Capacitance Voltage C-V for Si/Dielectric Interface Characterization","authors":"Thomas Nassiet, R. Duru, D. Le-Cunff, A. Arnaud, J. Bluet, G. Brémond","doi":"10.1109/ASMC49169.2020.9185305","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185305","url":null,"abstract":"We present an innovative approach of bias dependent photoluminescence characterization (PL-V) involving industrial Room Temperature Photoluminescence (RTPL) combined with corona charging. PL-V is performed on silicon oxide and silicon nitride films prepared on p-type silicon substrates. Results are directly compared to Capacitance-Voltage (C-V) measurements. A linearized model for PL-V has also been developed to understand the physical properties associated with this technique and the key similarities with C-V characterization. We finally show the sensitivity of PL-V to surface state density whose determination can benefit passivation quality studies.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"75 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86387495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：